CN1324653C - Method for improving n-type doping concentration of compound semiconductor under low growth temperature - Google Patents

Abstract

A method for increasing the n-type doping concentration in an indium gallium arsenide compound semiconductor, characterized in that it comprises the following steps: growing an indium phosphide buffer layer on an indium phosphide substrate at a growth temperature of 655°C by MOCVD ; reduce the temperature of the reaction chamber to a growth temperature of 600°C; and reduce the V/III ratio of the reaction source passing into the reaction chamber, keep the flow rate of the doping source and other growth conditions unchanged, and grow n-type doped indium gallium arsenic compound semiconductor.

Description

Method for increasing n-type doping concentration in indium gallium arsenide compound semiconductor

technical field

The invention relates to the field of semiconductor growth, in particular to a method for increasing the n-type doping concentration in indium gallium arsenic compound semiconductors.

Background technique

Due to its advantages in light absorption spectrum wavelength, circuit speed and power consumption, indium phosphide and its compound semiconductors have great application prospects in the field of long-wavelength optical fiber communication. The growth of high-quality indium phosphide and its compound semiconductors used in electrical devices (such as heterojunction bipolar transistors (HBT)) and optoelectronic devices that can be used in long-wavelength optical fiber communications is the basis for the application of this series of materials in this field.

For example, in the growth process of the HBT device, in order to increase the doping concentration of the base region, a method of growing the entire device at low temperature can be used. Since both the collection region and the emitter region of the HBT device have highly n-type doped layers, and the decomposition efficiency of silane, which is usually used as an n-type dopant source, decreases at low temperature, it is difficult to obtain a high doping concentration. The prior art methods for increasing the doping concentration include increasing the flow rate of silane or using alternative doping sources such as disilane. However, due to the limitation of growth equipment, the flow rate of silane cannot be increased infinitely, and the increase of flow rate of silane will inevitably cause unnecessary waste. In addition, if an alternative dopant source is used, the growth equipment must be modified and calibrated, which consumes time and manpower.

Contents of the invention

The object of the present invention is to provide a method for increasing the n-type doping concentration in indium gallium arsenide compound semiconductors. The method adopts the commonly used n-type doping source silane to obtain high n-type doping with a small doping source flow rate. The concentration reduces the consumption of dopant sources, simplifies the growth process and reduces the growth cost.

The technical solution of the present invention is a method for increasing the n-type doping concentration in an indium gallium arsenide compound semiconductor, which is characterized in that it comprises the following steps:

An indium phosphide buffer layer is grown on an indium phosphide substrate at a growth temperature of 655°C by MOCVD method;

reducing the temperature of the reaction chamber to a growth temperature of 600°C; and

Reduce the V/III ratio of the reaction source passing into the reaction chamber, keep the dopant source flow rate and other growth conditions unchanged, and grow n-type doped indium gallium arsenic compound semiconductor.

Wherein, the thickness of the buffer layer is 100nm to 300nm.

Wherein the V/III ratio of the reaction source passing into the reaction chamber is reduced by reducing the flow rate of the V group source.

Wherein said Group V source is phosphine.

Wherein said group V source is arsine.

Wherein the dopant source is silane.

Detailed ways

A method for increasing the n-type doping concentration in an indium gallium arsenide compound semiconductor, comprising the steps of:

Using the MOCVD method, at a high growth temperature, an indium phosphide buffer layer is grown on an indium phosphide substrate. The thickness of the indium phosphide buffer layer is 100nm to 300nm, and the highest growth temperature used for the growth buffer layer is 655 ℃;

reducing the reaction chamber temperature to a low growth temperature of less than 600°C; and

Reduce the V/III ratio of the reaction source into the reaction chamber, keep the flow rate of the doping source silane and other growth conditions constant, and grow n-type doped compound semiconductors, wherein the compound semiconductors are indium phosphide or indium gallium arsenic , wherein the V/III ratio of the reaction source passed into the reaction chamber is reduced by reducing the flow rate of the V group source, wherein the V group source is phosphine or arsine.

Embodiment one

In a specific embodiment of the present invention, first, at a high growth temperature—such as 655°C, a layer of indium phosphide buffer layer is deposited on an indium phosphide substrate by MOCVD method; the thickness of the buffer layer is between 100nm and 300nm between.

The reaction chamber temperature is then lowered to below 600°C.

While keeping the flow rate of other reaction sources constant, reduce the flow rate of the group V reaction source phosphine passing into the reaction chamber, reduce the V/III ratio of the growth source passing into the reaction chamber to less than 100, and deposit n-type doping indium phosphide layer.

Embodiment two

In another specific embodiment of the present invention, first, at a high growth temperature—for example, 655° C., a layer of indium phosphide buffer layer is deposited on an indium phosphide substrate by MOCVD; the thickness of the buffer layer is between 100 nm and 300 nm between.

The reaction chamber temperature is then lowered to below 600°C.

While keeping the flow rate of other reaction sources constant, reduce the flow rate of the group V reaction source arsine passing into the reaction chamber, so that the V/III ratio of the growth source passing into the reaction chamber is reduced to less than 100, and n-type doping is deposited. InGaAs layer.

The grown compound semiconductor layer is detected by electrochemical CV method, and the obtained results show that the n-type doping concentration greater than 1.0E19 is obtained in the indium phosphide and/or indium gallium arsenic thin films.

Claims (6)

1. a method that improves n type doping content in the indium gallium arsenide semiconductor is characterized in that, comprises following step:

Utilize the MOCVD method, under 655 ℃ of growth temperatures, growth indium phosphide resilient coating on the indium phosphide substrate;

Reaction chamber temperature is reduced to 600 ℃ growth temperature; And

Reduce to feed the reaction source V/III ratio of reative cell, keep doped source flow and other growth conditions constant, the indium gallium arsenide semiconductor that growing n-type mixes.

2. the method for n type doping content is characterized in that in the raising indium gallium arsenide semiconductor according to claim 1, and wherein, the thickness of resilient coating is 100nm to 300nm.

3. the method for n type doping content is characterized in that in the raising indium gallium arsenide semiconductor according to claim 1, and the V/III ratio that wherein feeds the reaction source of reative cell is to reduce by reducing the group V source flow.

4. the method for n type doping content is characterized in that wherein said group V source is a phosphine in the raising indium gallium arsenide semiconductor according to claim 3.

5. the method for n type doping content is characterized in that wherein said group V source is an arsine in the raising indium gallium arsenide semiconductor according to claim 3.

6. the method for n type doping content is characterized in that wherein said doped source is a silane in the raising indium gallium arsenide semiconductor according to claim 1.