Background technology
Organic Light Emitting Diode is a current driving element, its luminosity is according to the size decision by electric current, at present Organic Light Emitting Diode being applied on the matrix form display (Matrix Display) promptly is size by controller light emitting diode drive current, reaches the effect that shows different brightness (being called gray scale again).According to the difference of scanning line driving mode, matrix type organic light-emitting diode display can be divided into two kinds of passive type matrix (Passive Matrix) display and active type matrix (Active Matrix) displays.The passive type matrix display is to adopt the mode of driven sweep line in proper order, drive the pixel be positioned at different rows/list one by one, therefore the fluorescent lifetime of each pixel that go/lists can be subject to the sweep frequency and the number of scanning lines of display, is not suitable for the display of big picture and high definition (the expression sweep trace increases).The active type matrix display then forms independently image element circuit in each pixel, ask for an interview Fig. 1, and Fig. 1 is the synoptic diagram of the circuit structure of a pixel 20.The embodiment of Fig. 1 includes an electric capacity (Capacitor) C1, an Organic Light Emitting Diode D and a plurality of metal-oxide semiconductor (MOS) (Metal-OxideSemiconductor, MOS) transistor or thin film transistor (TFT) (Thin-film Transistor, TFT) T1~T4, utilize pixel 20 circuit to regulate the size of the drive current I of Organic Light Emitting Diode D, even therefore under the requirement of big picture and high definition, still can continue to provide each pixel 20 1 stabilized driving electric current I, improve the brightness uniformity of display.
In the organic light emitting diode display system, see also Fig. 2 corresponding to the data drive circuit structure of above-mentioned a plurality of pixels of arranging with matrix-style, Fig. 2 is the functional block diagram of well known data driving circuit structure 11.Please note, because the brightness of organic light emitting diode display is to utilize electric current to control, subelement about digital analog converter is necessary for the D/A conversion circuit that numerical data can be transferred to analog current, be called the digital simulation current converter, simultaneously, corresponding pixel portion is finished with the pixel (as the pixel 20 of Fig. 1) of current drives, Fig. 2 has represented the data drive circuit structure 11 in the known display element and a plurality of pixels 20 of arranging with matrix-style, has also represented the multi-strip scanning line (Scan Line) 21 corresponding to a plurality of pixels.Data drive circuit structure 11 includes a shift register 16 (Shift Register) and multi-stage data driving circuit 10, and each grade data driving circuit 10 includes a level shift circuit 12 (Level Shifter), a latch 14 (Latch) and a digital simulation current converter 18.At least one grade of data driving circuit 10 must be arranged in work in the time, in order to receive a digital signal, the digital signal that the level shift circuit 12 of this grade data driving circuit 10 will receive (being one 6 digital signal in the present embodiment) is carried out the adjustment of current potential, after latch 14 is electrically connected to the voltage shift device, function with buffering (Buffering) digital signal, latch 14 can latch this 6 position digital signal, so latch 14 is 6 a latch in the present embodiment, and shift register 16 exportable shift register signals, the digital signal that once will correspond to a pixel 20 on the display all is sent to the voltage shift device, allow the voltage shift device carry out the function of adjusting voltage and buffering, again digital signal is sent to latch 14, allows latch 14 continue to carry out the function of (boost and) buffering.
Please continue to consult Fig. 2, digital simulation current converter 18 in this grade data driving circuit 10 of work can receive the digital signal by latch 14 outputs, with digital data conversion is an analog current signal, and the output analog current signal is to a corresponding data line 19, this data line 19 links to each other with a plurality of pixels 20, and should have a sweep trace 21 to start working (current potential transfers noble potential to) this moment, pixel 20 conductings that will link to each other with this sweep trace 21, thus, the digital simulation current converter 18 of this grade data driving circuit 10 can form a path with data line and the pixel 20 that is scanned line 21 conductings, digital simulation current converter 18 can the conducting analog current signals to the pixel 20 that links to each other, 10 of this grade data driving circuits can form color according to the gray scale of the strong and weak control panel of analog current signal.Above-mentioned known basic structure is main to have relevant description in the patents of many data drive circuit designs about LCD and document, and organic light emitting diode display is just done it change slightly, for example the part of the digital analog converter of LCD is finished with above-mentioned digital simulation current converter circuit.People such as Yojiro Matsueda in 1996 at SID 96 Digest, deliver in " Low Temperaturepoly-Si TFT-LCD with integrated 6-bit Digital Data Driver " and use the fabrication techniques of LTPS on glass data drive circuit, and six digital data drive circuit structure proposed, and at US Patent 6,256,024, in " Liquid crystal display device ", people such as Maekawa also propose the structure of the LCD close with the foregoing description.
Panel with the input of 4 bit digital data is an example, people (U.of Michigan such as previous J.Kanicki, USA) a kind of simple numerical analog current converter circuit is proposed, adopting one group of (wide length) ratio is 1: 2: 4: 8 thin film transistor (TFT) (Thin Film Transistor, TFT) current source produces 16 kinds of different electric current gray scale Ig, ask for an interview Fig. 3, Fig. 3 is the wherein synoptic diagram of an embodiment of the digital simulation current converter 18 of one-level data drive circuit 10 of Fig. 2, and the digital simulation current converter 18 of this embodiment is made of a plurality of transistor T 5~T9.Since electric current gray scale Ig only by 41: 2: 4: thin film transistor (TFT) T1~T4 of 8 controls, in case wherein threshold voltage of any one thin film transistor (TFT) (Threshold Voltage) and mobility (Mobility) produce bigger variation, promptly have influence on electric current gray scale Ig at once, and then have influence on the demonstration uniformity coefficient of its corresponding panel pixel (as the pixel 20 of Fig. 1 and Fig. 2); In addition, because the output impedance (Output Impedance) of this kind digital simulation current converter 18 is not high enough, and be vulnerable to flow through the influence of the size of current of digital simulation current converter 18, make the output voltage of digital simulation current converter 18 also can change with the size of output current, make digital simulation current converter 18 and corresponding pixel (as the pixel 20 of Fig. 1 and Fig. 2) when being concatenated into a path, the electric current of its output is not the electric current of very stable 16 gray scales, therefore, still there are many spaces of improving in well known data driving circuit 10.
Embodiment
See also Fig. 4, Fig. 4 has represented the functional block diagram of combined data driving circuit structure 31 of the present invention, and this combined data driving circuit structure 31 is applied in the display element of a current drives.Fig. 4 has comprised a plurality of pixels 40 that arrangement is set in the mode of matrix in addition, and corresponding to the multi-strip scanning line 41 of a plurality of pixels 40.Combined data driving circuit structure 31 includes a level shift circuit 32 (Level Shifter), a digital simulation current converter 38 (Dieital-to-analog CurrentConverter) and the multi-stage data driving circuit 30a of the current potential that is used for adjusting received digital signal (also being one 6 digital signal in the present embodiment), 30b,, 30j.The digital signal that level shift circuit 32 will receive is carried out the adjustment of current potential, after digital simulation current converter 38 is electrically connected to level shift circuit 32, is used for digital signal is converted to an analog current signal, and multi-stage data driving circuit 30a, 30b ..., 30j is electrically connected to after the digital simulation current converter 38, and this multi-stage data driving circuit 30a, 30b ..., shared this digital simulation current converter 38 of 30j (and level shift circuit 32), can be used to drive many data line 39a of display element, 39b ..., 39j ( many data line 39a, 39b,, 39j corresponds to multi-stage data driving circuit 30a, 30b respectively,, 30j).Multi-stage data driving circuit 30a, 30b,, 30j includes electric current storage replication module (42a, a 42b all separately, 42j) with a control circuit (44a, 44b ... 44j), electric current storage replication module (42a, 42b ... 42j one of them) be used at the required predeterminated voltage of a conversion memory phase stored circulation analog current signal, and one reproduce in the sustained period conducting one duplicate current signal to corresponding to electric current storage replication module (42a, 42b ... 42j one of them) data line (39a, 39b ..., 39j one of them), and duplicate current signal is produced by predeterminated voltage, and duplicate current signal is almost equal in analog current signal.Control circuit (44a, 44b,, 44j) be electrically connected to digital simulation current converter 38 and electric current storage replication module (42a, 42b, 42j), be used for making corresponding to wherein this grade data driving circuit (30a, the 30b of a control circuit,, 30j one of them) at the conversion memory phase and reproduce between the sustained period and switch.
When reality is implemented, level shift circuit 32 can replace by latch, and the number of level shift circuit 32 (or latch) need not limit, even level shift circuit 32 removed in system also be included in the technical characterictic of the present invention, just there be not level shift circuit 32 to adjust under the situation of current potential of digital signals, digital signal is the pattern input data drive circuit 30a with big amplitude signal, 30b,, among the 30j, may be influential for the stable and power consumption of system.The embodiment of Fig. 4 combined data driving circuit structure 31 comprises a shift register 36 in addition, and shift register 36 is exportable corresponding to multi-stage data driving circuit 30a, 30b, a plurality of switching signal SWa of 30j, SWb ... SWj, and aforementioned conversion memory phase and reproduce switching between the sustained period promptly be by each grade data driving circuit (30a, 30b ... 30j one of them) control circuit (44a, 44b ..., 44j one of them) cooperate its corresponding switching signal (SWa, SWb,, SWj one of them) finish, in reality is implemented, a plurality of switching signal SWa, SWb ..., SWj can be described in Fig. 4 embodiment by a shift register 36 generation, or produced by a plurality of shift register 36, meaning is that the number of shift register 36 need not limit, even a plurality of switching signal SWa, SWb,, SWj can be produced by other relevant control module.See also Fig. 5, Fig. 5 is the synoptic diagram of Fig. 4 combined data driving circuit structure 31 1 embodiment, just especially with the digital simulation current converter 38 of Fig. 4 and the multi-stage data driving circuit 30a that links to each other, 30b,, 30j is (at each grade data driving circuit 30a, 30b, 30j one of them) in comprise an electric current storage replication module (42a, 42b ... 42j) and control circuit (44a, 44b ..., part 44j) is extracted out and is illustrated especially, and be incorporated into many corresponding data line 39a, 39b ..., 39j, note that the situation of the formerly described conversion memory phase of embodiment representative of Fig. 5.Digital simulation current converter 38 is Current Regulation formula (Current-Steering) digital simulation current converter 38 in Fig. 5 embodiment, has bigger output impedance, be not vulnerable to flow through the size of current of digital simulation current converter 38 and influence output voltage values, and each control circuit (44a, 44b,, 44j) be electrically connected to this digital simulation current converter 38 and corresponding electric current storage replication module (42a, 42b, 42j), can be considered by two transistor T10, T11 constitutes, be used for receiving a switching signal SWa, SWb ..., SWj.Each electric current storage replication module (42a of present embodiment, 42b, 42j) include a capacitor C and a plurality of metal-oxide semiconductor (MOS) (Metal-OxideSemiconductor, MOS) transistor or a plurality of thin film transistor (TFT), wherein capacitor C promptly has the function of the required predeterminated voltage of storage circulation analog current signal.Provide suitable external voltage source (Vdd for example, Vbias), current source (i, 2i ..., 2
N-1I), data inputs (D0, D1 ..., DN-1) and under the operating conditions such as ground connection, combined data driving circuit structure 31 can be carried out its associative operation.
Please continue to consult Fig. 5, when a certain level data driving circuit (30a, 30b ..., 30j one of them) control circuit (44a, 44b ..., 44j one of them) (as being the control of data drive circuit 30a among Fig. 5
Road 44a) receives corresponding switching signal SWa when being in a noble potential, this grade data driving circuit 30a is in the conversion memory phase, the digital signal that original process Fig. 4 level shift circuit 32 is adjusted is after Fig. 5 digital simulation current converter 38 is handled, output corresponding simulating current signal, and in this conversion memory phase, because switching signal SWa is in noble potential, the transistor T 11a of control circuit 44a turn-offs, control circuit 44a will cut off towards the path of data line 39a, and transistor T 10a conducting operation, meaning is that control circuit 44a connects the path between digital simulation current converter 38 and the electric current storage replication module 42a, electric current storage replication module 42a (shown in the arrow Ic that represents direction of current among Fig. 5) is gone in the analog current signal conducting, this moment, analog current signal can flow through P-type mos transistor T a and the capacitor C a that links to each other with voltage Vdd and capacitor C a among the electric current storage replication module 42a, make the required predeterminated voltage of capacitor C a storage circulation analog current signal, that is to say, in the present embodiment, the predeterminated voltage grid-source voltage of P-type mos transistor T a (Vgs) for this reason.Please note, at first, electric current storage replication module 42a can metal oxide semiconductor transistor or thin film transistor (TFT) (Thin Film Transistor, TFT) constitute, meaning promptly, predeterminated voltage also can be the grid-source voltage of P type thin film transistor (TFT), in fact, electric current storage replication module 42a major technology in the present embodiment is characterised in that the specific voltage of preservation is required for the circulation analog current signal, therefore the combination of other various forms of transistor collocation capacitor C a or circuit component also is included in the technical characterictic of present embodiment electric current storage replication module 42a, certainly, along with different circuit component combinations, reach the switching of above-mentioned conversion memory phase, the switching signal SWa that control circuit 44a is received just differs and is decided to be the described noble potential of present embodiment, must give corresponding adjustment, and this same application by analogy is in all the other all data drive circuit 30b,, 30j.
When above-mentioned switching signal SWa gets back to an electronegative potential, this grade data driving circuit 30 just transfers to and is in the reproduction sustained period, and next stage data drive circuit 30b this moment (is the next stage data drive circuit of data drive circuit 30a as data drive circuit 30b among Fig. 5) should receive the switching signal of corresponding noble potential
SWb, make data drive circuit 30b be in the conversion memory phase, produce the electric current of direction of current Ic as shown in Figure 6, see also Fig. 6, Fig. 6 is the operation chart of data drive circuit 30a in reproducing sustained period among Fig. 5 embodiment, function and coding that Fig. 6 describes element are all identical with Fig. 5, and have represented that its next stage data drive circuit 30b is in the situation of conversion memory phase when this grade data driving circuit 30a is reproducing sustained period.Hence one can see that, and conversion memory phase (or reproducing sustained period) is to appear at multi-stage data driving circuit 30a in regular turn, 30b ... among the 30j, and to each grade data driving circuit (30a, 30b,, 30j), the conversion memory phase is two kinds of operator schemes that alternately occur with reproducing sustained period.After the switching signal SWa that this grade data driving circuit 30a is received is converted to electronegative potential by noble potential, control circuit 44a (the switching signal SWa of electronegative potential turn-offs transistor T 10a) can will cut off between digital simulation current converter 38 and the electric current storage replication module 42a, this moment transistor T 11a open operation, electric current storage replication module 42a can be in reproducing sustained period conducting one duplicate current signal to data line 39a (represent the arrow Io of direction of current to represent in as Fig. 6), the pixel 40 that links to each other with data line 39a with driving.Duplicate current signal is produced by the predeterminated voltage that electric current storage replication module 42a had before been stored when changing memory phase, originally analog current signal is required to be stored and keeps for response is circulated because of predeterminated voltage, so duplicate current signal is the almost equal analog current signal that is produced in original digital simulation current converter 38.Please note, described mode of operation in like manner during with leading portion (Fig. 5) conversion memory phase, because the combination of various forms of transistor collocation capacitor C a or circuit component is included in the technical characterictic of electric current storage replication module 42a of the present invention, along with different circuit component combinations, reach the switching of above-mentioned reproduction sustained period, the current potential of the switching signal SWa that control circuit 44a is received just must give corresponding adjustment, application by analogy in like manner is in all the other all data drive circuit 30b,, 30j.
Please consult the embodiment of Fig. 4 and Fig. 6 simultaneously, as a certain level data driving circuit (30a, 30b, 30j one of them) will cut off towards the path of digital simulation current converter 38 and will be towards corresponding data line (39a, 39b, 39j one of them) the path conducting time, should there be a sweep trace 41 to begin operation (current potential transfers noble potential to), all conductings of pixel 40 that sweep trace therewith 41 is linked to each other, with data drive circuit 30a is example, the transistor T a that links to each other with the capacitor C a that has predeterminated voltage among the electric current storage replication module 42a of this grade data driving circuit 30a can go into a path with data line 39a and the pixel 40 that is scanned line 41 conductings, just there is at least one pixel 40 can be injected into electric current by electric current storage replication module 42a conducting, and analog current signal that this electric current had before converted from digital signal no better than or the electric current that is slightly less than slightly.After sweep trace 41 is turned off (current potential transfers electronegative potential to), because the pixel 40 that just has been injected into electric current is for having the pixel 40 of electric current storage replication merit model, this pixel 40 equals or is proportional to the current signal that originally injected so can duplicate one by data line 39a, make Organic Light Emitting Diode or the organic macromolecular LED diode relaying afterflow of current signal in pixel 40 logical, make Organic Light Emitting Diode in the pixel 40 or organic macromolecular LED diode can continue to keep corresponding brightness, be switched on again up to this pixel 40 corresponding scanning line 41 next time.See also Fig. 7, Fig. 7 is the sequential chart of combined data driving circuit structure 31 operations of the present invention, has represented the operational scenario of Fig. 4 to Fig. 6 embodiment among Fig. 7, and with the continuous two-stage data drive circuit 30a among Fig. 5 and Fig. 6 embodiment, the operational scenario of 30b is an example, can more clearly be represented by Fig. 7, and conversion memory phase (or reproducing sustained period) is to appear at multi-stage data driving circuit 30a in regular turn, among the 30bj, certainly application by analogy in like manner is in all data drive circuit 30a, 30b ... among the 30j, and
To each grade data driving circuit (30a, 30b ... 30j), the conversion memory phase is alternately to occur with reproducing sustained period, in addition, represented also after the sweep trace 41 of Fig. 4 is turned off (current potential transfers electronegative potential to) that at Fig. 7 corresponding pixel 40 just is in a pixel current duplicate stage.
Combined data driving circuit structure of the present invention is to be applied to an Organic Light Emitting Diode (OLED) display, organic macromolecular LED diode (PLED) display, or in other display systems by current drives, in addition, combined data driving circuit structure of the present invention is integrated a digital simulation current converter and multi-stage data driving circuit, and each grade data driving circuit possesses the technical characterictic that electric current storage and copy function are arranged, can be at a conversion memory phase stored one predeterminated voltage, and reproduce the stable gray scale electric current of conducting in the sustained period one one, reaching provides steady current and simplified structure to save functions such as power consumption.
The above only is the preferred embodiments of the present invention, and all equivalences of making according to claims of the present invention change and revise, and all should belong to covering scope of the present invention.