CN1322744C - Continuous Burst Generator Using Low Voltage Clock Signal - Google Patents

Abstract

The invention provides a continuous pulse string generator using low-voltage clock signals, which comprises a dynamic shift register, a level shifter and a buffer consisting of inverters in each stage of circuit.

Description

Continuous Burst Generator Using Low Voltage Clock Signal

technical field

The present invention relates to a sequential pulse train generator for a liquid crystal display, in particular to a sequential pulse train generator using a low-voltage clock signal.

Background technique

In a liquid crystal display, since a frame of picture is jointly formed by an array composed of multiple pixels, the continuous pulse train becomes the basic signal that must be used when driving the liquid crystal display, and the generator of the continuous pulse train also becomes a necessity in the liquid crystal display. circuit.

Figure 1 shows a conventional continuous pulse train generator circuit for liquid crystal displays. Since a continuous pulse generator consists of multiple stages, and each stage may have pulse trains with different timings, only three stages are used as an example in FIG. 1 for simplicity of description. Each stage includes a shift register 111 , 112 or 113 and a level shifter 121 , 122 or 123 . The shift registers 111, 112, and 113 of each stage receive the clock signal CK and its inversion signal CK', and after the shift register 111 of the first stage receives an initial pulse train IN, as each stage is clocked The delay on the circuit board and the potential adjustment of the level shifters 121, 122, 123 can respectively generate pulse trains with continuous different timings and sufficient voltage amplitudes.

There are resistors 131, 132 and capacitors 151, 152 of a certain size in the transmission line used to transmit the clock signal CK and its inverse signal CK', and there are also resistors 141, 142, 143 and Capacitors 161, 162, 163. These resistor and capacitor values will increase the power consumption required by the entire LCD display.

However, in the traditional continuous pulse train generator mentioned above, since the required clock signal voltage amplitude is not low, the power consumption in the transmission line will increase with the transmitted signal amplitude. The pulse train generator will have a large power consumption.

Contents of the invention

In order to solve the above problems, the present invention provides a continuous pulse train generator that can normally operate under a low-voltage clock signal to reduce power consumption caused by the clock signal voltage transmission.

An object of the present invention is to provide a continuous pulse train generator using a low-voltage clock signal, including a first and a second dynamic shift register, a first and a second level shifter and a first and a second inverter phase device. Wherein, each dynamic shift register has a first, a second, a third and a fourth input terminal, a first, a second and a third output terminal, and the first and second of the first dynamic shift register , the third and the fourth input terminals respectively receive an initial pulse train, an inversion signal of the initial pulse train, a clock signal and an inversion signal of the clock signal, the first output of the first dynamic shift register terminal is connected to the first input terminal of the second dynamic shift register, the third and fourth input terminals of the second dynamic shift register respectively receive the inversion signal of the clock signal and the clock signal, and each The dynamic shift register includes: a first transistor of the first type, whose gate is connected to the first input terminal, and whose drain is connected to the second input terminal; a second transistor of the second type, whose gate is connected to the first input terminal. Two input terminals, the source is connected to receive a first potential; a third second type transistor, the gate of which is connected to the first input terminal, the drain is connected to the first output terminal, and the source is connected to the second second type transistor The drain of the second-type transistor; a fourth second-type transistor, the grid of which is connected to the source of the third second-type transistor, the drain is connected to the source of the first first-type transistor, and the source is connected to the source of the first first-type transistor First potential; a fifth second-type transistor, the gate of which is connected to the source of the first first-type transistor, the drain is connected to the third input terminal, and the source is connected to the second output terminal; a first potential Six second-type transistors, the gate of which is connected to the second input terminal, the drain of which is connected to the source of the fifth second-type transistor, and the source is connected to the first potential; a seventh second-type transistor, whose gate The pole is connected to the gate of the fifth second-type transistor, the drain is connected to the fourth input terminal, and the source is connected to the third output terminal. Each level shifter has a first, a second input end and an output end, and the first and second input ends of the first level shifter are respectively connected to the second and third of the first dynamic shift register. output terminal, the output terminal of the first level shifter is connected to the first output terminal of the first dynamic shift register, and the first and second input terminals of the second level shifter are connected to the second dynamic shift register respectively. The second and the third output end of the shift register, the output end of the second level shifter is connected to the first output end of the second dynamic shift register, each level shifter includes: an eighth first type transistor, its gate is connected to the first potential, and its source is connected to a second potential; a ninth first type transistor, its gate is connected to the drain, and its source is connected to the drain of the eighth first type transistor ; a tenth first type transistor, the gate of which is connected to the gate of the ninth first type transistor, the source is connected to the second potential, and the drain is connected to the output terminal; an eleventh second type transistor, Its gate is connected to the drain of the eighth first-type transistor, its source is connected to the drain of the ninth first-type transistor, and its drain is connected to the first input terminal; a twelfth second-type transistor, Its gate is connected to the gate of the eleventh second-type transistor, its source is connected to the drain of the tenth first-type transistor, and its source is connected to the second input terminal. The input terminals of the first and second inverters are respectively connected to the output terminals of the first and second level shifters, and the output terminals respectively output a first and second pulse train, and the first inverter The output end of the register is connected to the second input end of the second dynamic shift register.

Another object of the present invention is to provide a continuous pulse train generator using a low-voltage clock signal, comprising: a first, a second, a third dynamic shift register, a first, a second, a third level shifter , a second, third, fourth, fifth, sixth and seventh inverters. Wherein, each dynamic shift register has a first, second and third input terminal, a first, second and third output terminal, the first, second and third of the first dynamic shift register The input terminal respectively receives an initial pulse train, an inversion signal of the initial pulse train, and a clock signal, and the first output terminal of the first dynamic shift register is connected to the second input of the third dynamic shift register end, the third input end of the second dynamic shift register receives the inversion signal of the clock signal, the third input end of the third dynamic shift register receives the clock signal, and each dynamic shift register includes : a first transistor of the first type, its gate is connected to the first input terminal, its drain is connected to the second input terminal, and its source is connected to the third output terminal; a second second type transistor, its gate The pole is connected to the first output terminal, the source is connected to a first potential, and the drain is connected to the first output terminal; a third second type transistor, the gate is connected to the first output terminal, and the drain is connected to the first output terminal. The source of the third input terminal is connected to the second output terminal; the gate of a fourth second-type transistor is connected to the second input terminal, the drain is connected to the second output terminal, and the source is connected to the first output terminal. a potential. Each level shifter has a first, a second input end and an output end, and the first and second input ends of the first level shifter are respectively connected to the second and third outputs of the first shift register terminal, the first and second input terminals of the second level shifter are respectively connected to the second and third output terminals of the second shift register, the first and second input terminals of the third level shifter Respectively connected to the second and third output ends of the third shift register, each level shifter includes: a fifth transistor of the first type, the gate of which is connected to the first potential, and the source is connected to a second potential ; a sixth first-type transistor, its source connected to the drain of the fifth first-type transistor, and the drain connected to the output terminal; a seventh second-type transistor, its gate connected to the second potential, A source is connected to the first input terminal, a drain is connected to the output terminal; a first inverter, the input terminal is connected to the second input terminal, and the output terminal is connected to the gate of the sixth first-type transistor. The input terminals of the second, third and fourth inverters are respectively connected to the output terminals of the first, second and third level shifters, and the output terminals of the second and third inverters are respectively connected to The first input terminals of the second and third dynamic shift registers, the input terminals of the fifth, sixth and seventh inverters are respectively connected to the output terminals of the second, third and fourth inverters, The output terminal of the fifth inverter is connected to the second input terminal of the second dynamic shift register, and the output terminals of the fifth, sixth and seventh inverters output a first, second and first Three bursts.

Hereinafter, an embodiment of a continuous pulse train generator using a low-voltage clock signal according to the present invention will be described with reference to the accompanying drawings.

Description of drawings

Fig. 1 is a traditional continuous pulse train generator;

Fig. 2 is a continuous pulse train generator using a low-voltage clock signal in a first embodiment of the present invention;

Fig. 3 is the dynamic shift register circuit in the first embodiment of the present invention;

Fig. 4 is the level shifter circuit in the first embodiment of the present invention;

5a and 5b are a continuous pulse train generator using a low-voltage clock signal in a second embodiment of the present invention;

Fig. 6 is the dynamic shift register circuit in the second embodiment of the present invention;

Fig. 7 is the level shifter circuit in the second embodiment of the present invention;

FIG. 8 is a timing diagram of continuous bursts generated in the first and second embodiments of the present invention.

Symbol Description

111, 112, 113: shift registers;

121, 122, 123, 221, 222, 223, 521, 522, 523: level shifter;

131, 132, 141, 142, 143: resistance;

151, 152, 161, 162, 163, 38, 65: capacitance;

211, 212, 213, 511, 512, 513: dynamic shift registers;

231, 232, 233, 531, 532, 533, 541, 542, 543, 74: inverters;

32-37, 44, 45, 62-64, 73: N-type transistors;

31, 41-43, 61, 71, 72: P-type transistors.

Detailed ways

FIG. 2 is a continuous burst generator using a low voltage clock signal in a first embodiment of the present invention. For simplicity of description, only three stages are taken as an example in FIG. . Each dynamic shift register 211, 212, 213 has input terminals S1, S2, S3, S4, and output terminals S5, S6, S7. The input terminals S3, S4, S1, and S2 of the dynamic shift register 211 respectively receive an initial pulse train IN, an inverted signal IN' of the initial pulse train IN, a clock signal CK, and an inverted signal CK' of the clock signal CK. The output terminal S7 of the dynamic shift register 211 is connected to the input terminal S3 of the dynamic shift register 222 , and the output terminal S7 of the dynamic shift register 212 is connected to the input terminal S3 of the dynamic shift register 223 . The input terminals S1 and S2 of the dynamic shift register 222 respectively receive the inversion signal CK' of the clock signal CK and the clock signal CK, while the input terminals S1 and S2 of the dynamic shift register 223 respectively receive the clock signal CK and the inversion signal of the clock signal CK. phase signal CK'.

Each level shifter 221, 222, 223 has an input terminal L1, L2 and an output terminal L3. The input terminals L1 and L2 of the level shifter 221 are respectively connected to the output terminals S5 and S6 of the dynamic shift register 211 . The input terminals L1 and L2 of the level shifter 222 are respectively connected to the output terminals S5 and S6 of the dynamic shift register 212 . The input terminals L1 and L2 of the level shifter 223 are respectively connected to the output terminals S5 and S6 of the dynamic shift register 213 . The output terminal L3 of the level shifter 221 is connected to the output terminal S7 of the dynamic shift register 211 , and the output terminal L3 of the level shifter 222 is connected to the output terminal S7 of the dynamic shift register 212 . The output terminal L3 of the level shifter 223 is connected to the output terminal S7 of the dynamic shift register 213 .

The input terminals of the inverters 231, 232, 233 are respectively connected to the output terminals L3 of the level shifters 221, 222, 223, and the output terminals thereof respectively output pulse trains OUT1, OUT2, OUT3. The output terminal of the inverter 231 is connected to the input terminal S4 of the dynamic shift register 212 , and the output terminal of the inverter 232 is connected to the input terminal S4 of the dynamic shift register 213 .

Fig. 3 shows the dynamic shift register circuit in the above continuous pulse train generator. It includes a P-type transistor 31 , N-type transistors 32 - 37 and a capacitor 38 . The gate of the P-type transistor 31 is connected to the input terminal S3, and the drain is connected to the input terminal S4. The gate of the N-type transistor 32 is connected to the input terminal S4, and the source is connected to a ground potential. The gate of the N-type transistor 33 is connected to the input terminal S3 , the drain is connected to the output terminal S7 , and the source is connected to the drain of the N-type transistor 32 . The gate of the N-type transistor 34 is connected to the source of the N-type transistor 33 , the drain is connected to the source of the P-type transistor 31 , and the source is connected to the ground potential. The gate of the N-type transistor 35 is connected to the source of the P-type transistor 31 , the drain is connected to the input terminal S1 , and the source is connected to the output terminal S5 . The gate of the N-type transistor 36 is connected to the input terminal S4, the drain is connected to the source of the N-type transistor 35, and the source is connected to the ground potential. The gate of the N-type transistor 37 is connected to the gate of the N-type transistor 35 , the drain is connected to the input terminal S2 , and the source is connected to the output terminal S6 .

The capacitor 38 is connected between the gate and the source of the N-type transistor 35 . The capacitor 38 can also be the gate-source parasitic capacitance of the N-type transistor 35 .

Fig. 4 shows the level shifter circuit in the above continuous burst generator. These include P-type transistors 41 , 42 , 43 and N-type transistors 44 , 45 . The gate of the P-type transistor 41 is connected to the ground potential, and the source is connected to a high power supply voltage VDD. The gate and drain of the P-type transistor 42 are connected, and the source is connected to the drain of the P-type transistor 41 . The gate of the P-type transistor 43 is connected to the gate of the P-type transistor 42 , the source is connected to the high power supply voltage VDD, and the drain is connected to the output terminal L3 . The gate of the N-type transistor 44 is connected to the drain of the P-type transistor 41 , the source is connected to the drain of the P-type transistor 42 , and the drain is connected to the input terminal L1 . The gate of the N-type transistor 45 is connected to the gate of the N-type transistor 44 , the source is connected to the drain of the P-type transistor 43 , and the drain is connected to the input terminal L2 .

5a and 5b are a continuous burst generator using a low-voltage clock signal in a second embodiment of the present invention. For simplicity of description, only three stages are taken as an example in FIG. 5, including dynamic shift registers 511, 512, 513, voltage shift registers 521, 522, 523, and inverters 531-533, 541 used as buffers. -543. Each dynamic shift register 511 , 512 , 513 has input terminals S1 , S3 , S4 , and output terminals S2 , S5 , S6 . The input terminals S3, S4 and S1 of the dynamic shift register 511 respectively receive an initial pulse train IN, an inverted signal IN' of the initial pulse train IN, and a clock signal CK. The output terminal S2 of the dynamic shift register 511 is connected to the input terminal S4 of the dynamic shift register 513 . The input terminal S1 of the dynamic shift register 512 receives the inverted signal CK' of the clock signal CK. The input terminal S1 of the dynamic shift register 513 receives the clock signal CK.

Each level shifter 521, 522, 523 has an input terminal L1, L2 and an output terminal L3. The input terminals L1 and L2 of the level shifter 521 are respectively connected to the output terminals S5 and S6 of the dynamic shift register 511 . The input terminals L1 and L2 of the level shifter 522 are respectively connected to the output terminals S5 and S6 of the dynamic shift register 512 . The input terminals L1 and L2 of the level shifter 523 are respectively connected to the output terminals S5 and S6 of the dynamic shift register 513 .

The input terminals of the inverters 531, 532, 533 are respectively connected to the output terminals L3 of the level shifters 521, 522, 523. The output terminals of the inverters 531, 532 are respectively connected to the input terminals S3 of the dynamic shift registers 512, 513. The input terminals of the inverters 541, 542, 543 are connected to the output terminals of the inverters 531, 532, 533, respectively. The output terminal of the inverter 541 is connected to the input terminal S4 of the dynamic shift register 512 . The output terminals of the inverters 541, 542, 543 output pulse trains OUT1, OUT2, OUT3.

Fig. 6 shows a dynamic shift register circuit in the above continuous pulse train generator. It includes a P-type transistor 61 , N-type transistors 62 - 64 and a capacitor 65 . The gate of the P-type transistor 61 is connected to the input terminal S3, the drain is connected to the input terminal S4, and the source is connected to the output terminal S6. The gate of the N-type transistor 62 is connected to the output terminal S2 , the source is connected to a ground potential, and the drain is connected to the output terminal S6 . The gate of the N-type transistor 63 is connected to the output terminal S6, the drain is connected to the input terminal S1, and the source is connected to the output terminal S5. The gate of the N-type transistor 64 is connected to the input terminal S4, the drain is connected to the output terminal S5, and the source is connected to the ground potential.

The capacitor 65 is connected between the gate and the source of the N-type transistor 63 . The capacitor 65 can also be the gate-source parasitic capacitance of the N-type transistor 63 .

Fig. 7 shows a level shifter circuit in the above continuous burst generator. It includes P-type transistors 71 , 72 , N-type transistor 73 and inverter 74 . The gate of the P-type transistor 71 is connected to the ground potential, and the source is connected to a high power supply voltage VDD. The source of the P-type transistor 72 is connected to the drain of the P-type transistor 71, and the drain is connected to the output terminal L3. The gate of the N-type transistor 73 is connected to the high power supply voltage VDD, the source is connected to the input terminal L1, and the drain is connected to the output terminal L3. The input terminal of the inverter 74 is connected to the input terminal L2 , and the output terminal is connected to the gate of the P-type transistor 72 .

FIG. 8 shows the bursts OUT1, OUT2, and OUT3 generated by the continuous burst generator using the low-voltage clock signal in the above-mentioned first and second embodiments. The pulses in the pulse trains OUT1, OUT2, OUT3 are all half a clock signal period apart. The voltage amplitude of the clock signal CK is 3.3V, and the VDD is 9V.

In summary, the present invention provides a continuous pulse train generator that can operate normally under a low-voltage clock signal. Each stage uses a dynamic shift register and a level shifter, which can receive a low-voltage clock signal and reduce the Power consumption caused by signal voltage transmission.

Although the present invention has been disclosed above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection is defined by the claims as presented.

Claims (16)

1. A continuous pulse train generator using a low voltage clock signal, comprising: First and second dynamic shift registers, each dynamic shift register has first, second, third and fourth input terminals, first, second and third output terminals, the first dynamic shift register The first, second, third and fourth input terminals respectively receive an initial pulse train, an inversion signal of the initial pulse train, a clock signal and an inversion signal of the clock signal, the first dynamic shift register The first output end is connected to the first input end of the second dynamic shift register, and the third and fourth input ends of the second dynamic shift register respectively receive the inversion signal of the clock signal and the clock signal; First and second level shifters, each level shifter has first, second input terminals and an output terminal, the first and second input terminals of the first level shifter are respectively connected to the first The second and third output ends of the dynamic shift register, the output end of the first level shifter is connected to the first output end of the first dynamic shift register, the first and third output ends of the second level shifter The two input terminals are respectively connected to the second and third output terminals of the second dynamic shift register, and the output terminal of the second level shifter is connected to the first output terminal of the second dynamic shift register; and The first and second inverters, the input terminals of which are respectively connected to the output terminals of the first and second level shifters, and the output terminals of which respectively output the first and second pulse trains, and the first inverter The output terminal of is connected to the second input terminal of the second dynamic shift register. 2. The continuous burst generator using a low voltage clock signal as claimed in claim 1, wherein each dynamic shift register comprises: A first transistor of the first type, the gate of which is connected to the first input end of the dynamic shift register, and the drain is connected to the second input end of the dynamic shift register; A second transistor of the second type, the gate of which is connected to the second input terminal of the dynamic shift register, and the source of which is connected to the first potential; The third transistor of the second type, its gate is connected to the first input end of the dynamic shift register, the drain is connected to the first output end of the dynamic shift register, and the source is connected to the second transistor of the second type Drain; a fourth second-type transistor, the gate of which is connected to the source of the third second-type transistor, the drain is connected to the source of the first first-type transistor, and the source is connected to the first potential; The fifth second type transistor, its gate is connected to the source of the first first type transistor, the drain is connected to the third input terminal of the dynamic shift register, and the source is connected to the second input terminal of the dynamic shift register. output terminal; a sixth second-type transistor, the gate of which is connected to the second input terminal of the dynamic shift register, the drain is connected to the source of the fifth second-type transistor, and the source is connected to the first potential; and The seventh second-type transistor, whose gate is connected to the gate of the fifth second-type transistor, the drain is connected to the fourth input terminal of the dynamic shift register, and the source is connected to the first input terminal of the dynamic shift register. Three output terminals. 3. The continuous burst generator using a low voltage clock signal as claimed in claim 1, wherein each level shifter comprises: An eighth first-type transistor, the gate of which is connected to the first potential, and the source of which is connected to the second potential; a ninth transistor of the first type, the gate of which is connected to the drain, and the source of which is connected to the drain of the eighth transistor of the first type; a tenth first-type transistor, the gate of which is connected to the gate of the ninth first-type transistor, the source is connected to the second potential, and the drain is connected to the output terminal of the level shifter; The eleventh second-type transistor, the gate of which is connected to the drain of the eighth first-type transistor, the source is connected to the drain of the ninth first-type transistor, and the drain is connected to the first of the level shifter. an input terminal; and The twelfth second-type transistor, the gate of which is connected to the gate of the eleventh second-type transistor, the source is connected to the drain of the tenth first-type transistor, and the drain is connected to the level shifter the second input. 4. The continuous pulse train generator using a low-voltage clock signal as claimed in claim 2, wherein each dynamic shift register further comprises a capacitor connected between the gate and the source of the fifth second-type transistor. 5. The burst generator using a low-voltage clock signal as claimed in claim 2 or 3, wherein the first type is a P type, and the second type is an N type. 6. The burst generator using a low-voltage clock signal as claimed in claim 2 or 3, wherein the first potential is a ground potential. 7. The burst generator using a low voltage clock signal as claimed in claim 3, wherein the second potential is a high supply potential VDD. 8. The continuous pulse train generator using a low voltage clock signal as claimed in claim 3, wherein the amplitude of the clock signal is smaller than the second potential. 9. A continuous pulse train generator using a low voltage clock signal, comprising: First, second and third dynamic shift registers, each dynamic shift register has first, second and third input terminals, first, second and third output terminals, the first dynamic shift register The first, second and third input terminals respectively receive an initial pulse train, an inversion signal of the initial pulse train, and a clock signal, and the first output terminal of the first dynamic shift register is connected to the third dynamic shift register. The second input end of the shift register, the third input end of the second dynamic shift register receives the inversion signal of the clock signal, and the third input end of the third dynamic shift register receives the clock signal; First, second and third level shifters, each level shifter has first and second input terminals and output terminals, the first and second input terminals of the first level shifter are respectively connected to the The second and third output terminals of the first dynamic shift register, the first and second input terminals of the second level shifter are connected to the second and third output terminals of the second dynamic shift register respectively, the The first and second input terminals of the third level shifter are respectively connected to the second and third output terminals of the third dynamic shift register; and The second, third, fourth, fifth, sixth and seventh inverters, the input ends of the second, third and fourth inverters are connected to the first, second and third level shifters respectively The output end of the positioner, the output end of the second and the third inverter is respectively connected to the first input end of the second and the third dynamic shift register, the fifth, the sixth and the seventh inverter The input ends are respectively connected to the output ends of the second, third and fourth inverters, the output end of the fifth inverter is connected to the second input end of the second dynamic shift register, and the fifth , the output terminals of the sixth and seventh inverters output the first, second and third pulse trains. 10. The burst generator using a low voltage clock signal as claimed in claim 9, wherein each dynamic shift register comprises: The first transistor of the first type, its gate is connected to the first input terminal of the dynamic shift register, the drain is connected to the second input terminal of the dynamic shift register, and the source is connected to the third input terminal of the dynamic shift register output terminal; The second transistor of the second type, its gate is connected to the first output end of the dynamic shift register, the source is connected to the first potential, and the drain is connected to the third output end of the dynamic shift register; The third transistor of the second type, its gate is connected to the third output end of the dynamic shift register, the drain is connected to the third input end of the dynamic shift register, and the source is connected to the second end of the dynamic shift register output terminal; and The gate of the fourth transistor of the second type is connected to the second input end of the dynamic shift register, the drain is connected to the second output end of the dynamic shift register, and the source is connected to the first potential. 11. The continuous burst generator using a low voltage clock signal as claimed in claim 9, wherein each level shifter comprises: A fifth first-type transistor, the gate of which is connected to the first potential, and the source of which is connected to the second potential; a sixth first-type transistor, the source of which is connected to the drain of the fifth first-type transistor, and the drain is connected to the output terminal of the level shifter; A seventh second type transistor, the gate of which is connected to the second potential, the source is connected to the first input terminal of the level shifter, and the drain is connected to the output terminal of the level shifter; and The input terminal of the first inverter is connected to the second input terminal of the level shifter, and the output terminal is connected to the gate of the sixth transistor of the first type. 12. The burst generator using a low-voltage clock signal as claimed in claim 10, wherein each dynamic shift register further comprises a capacitor connected between the gate and the source of the third transistor of the second type. 13. The burst generator using a low-voltage clock signal as claimed in claim 10 or 11, wherein the first type is a P type, and the second type is an N type. 14. The burst generator using a low-voltage clock signal as claimed in claim 10 or 11, wherein the first potential is a ground potential. 15. The burst generator using a low voltage clock signal as claimed in claim 11, wherein the second potential is a high supply potential VDD. 16. The continuous pulse train generator using a low-voltage clock signal as claimed in claim 11, wherein the amplitude of the clock signal is smaller than the second potential.

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