CN1320775C - Circuit for eliminating signal amplitude mismatch on orthogonal signal path - Google Patents

Abstract

The invention belongs to the technical field of analog signal processing and communication, and relates to a signal amplitude mismatch elimination circuit on an orthogonal signal path, comprising: two power detectors respectively connected to the signal output ends of the I path and the Q path of the orthogonal signal path, for use in It is used to detect the output power of the I and Q channels respectively; a subtractor connected to the output terminals of the two power detectors at the same time is used to calculate the power difference between the I channel and the Q channel; The connected VGA control signal generator is used to generate the gain control signals of the I-way and Q-way VGA, so as to adjust the gain of the VGA so that the powers of the I and Q output signals are equal. The invention can better solve the amplitude mismatch problem of the quadrature signal in the receiver. And it has the advantages of improving process tolerance and reducing communication bit error rate.

Description

Elimination of Signal Amplitude Mismatch Circuit in Quadrature Signal Path

technical field

The invention belongs to the technical field of analog signal processing and communication, and in particular relates to a circuit design for eliminating the amplitude mismatch of IQ two-way signals.

Background technique

If you want to demodulate frequency-modulated and phase-modulated signals, you usually use quadrature demodulation to extract the frequency and phase information contained in the signal. The modulated signal is down-converted to the baseband by the local quadrature oscillating signal, divided into I and Q (representing the real part and imaginary part of the signal) for processing, and becomes a digital signal. The mismatch of the quadrature output of the local oscillator signal, and the device mismatch of the I and Q two links during the manufacturing process will cause the amplitude mismatch of the I and Q two link signals and affect the accuracy of the analog-to-digital conversion. Figure 1 shows a common zero-IF quadrature demodulation receiver. The received radio frequency modulation signal is amplified by the low noise amplifier (LNA), divided into two IQ channels and down-converted to the baseband signal by the mixer (Mixer), and then passed through the filter (LPF), variable gain amplifier (VGA), low Pass filter (LPF) for processing, and finally into the digital-to-analog converter. Wherein the local oscillator (LO) outputs a quadrature signal whose frequency is equal to the central frequency of the radio frequency signal. Taking this as an example, it can explain the problem of the amplitude mismatch of the I and Q signals. In the figure, if the amplitude of the quadrature signal output by the local oscillator (LO) does not match, or due to the deviation of the process, the two quadrature links (I Road, Q Road in Figure 1) The device mismatch on the device will cause the amplitude mismatch of the baseband signal.

In the current CMOS process, if the symmetry of the circuit layout is strictly considered, the amplitude mismatch can only be controlled within 0.5dB. No matter what the cause is, if the amplitudes of the two quadrature signals input to the analog-to-digital converter do not match, the bit error rate and packet error rate of the receiver will be greatly increased.

The current solution to the amplitude mismatch is mainly to minimize it through layout matching. However, since process deviation always exists, the problem of amplitude mismatch cannot be solved fundamentally.

Contents of the invention

The object of the present invention is to overcome the disadvantages of the prior art, and propose a signal amplitude mismatch elimination circuit on the quadrature signal path, which can better solve the quadrature signal amplitude mismatch problem in the receiver. And it has the advantages of improving process tolerance and reducing communication bit error rate.

The technical solution of the present invention comprises: two power detectors respectively connected to the signal output ends of the I road and the Q road of the orthogonal signal path, for detecting the output powers of the I and Q two roads respectively; A subtracter connected to the output of the subtractor, used to calculate the power difference between the I-way and Q-way; a VGA control signal generator connected to the output of the subtractor, used to generate the gain control of the I-way and Q-way VGA Signal, in order to adjust the gain of VGA, so that the output signal power of I and Q is equal.

Features and technical effects of the present invention:

The invention uses a circuit to measure and eliminate the amplitude mismatch of IQ two-way signals, which is more effective in eliminating the mismatch and more reliable than the traditional way of completely relying on layout matching to achieve matching. The amplitude mismatch is improved from the traditional 0.5dB to 0.1dB. It can be widely used in quadrature demodulation links.

Description of drawings

Figure 1 is a structural diagram of a common zero-IF receiver.

FIG. 2 is a schematic diagram of the overall structure of the circuit for eliminating signal amplitude mismatch of the present invention.

FIG. 3 is a schematic structural diagram of an embodiment of a circuit for eliminating quadrature signal amplitude mismatch according to the present invention.

FIG. 4 is a schematic structural diagram of a circuit embodiment of the VGA control signal generator (VcGen) of the present invention.

Fig. 5 is a structural diagram of a zero-IF receiver applying the present invention to realize automatic gain control.

Detailed ways

The circuit for eliminating signal amplitude mismatch on the orthogonal signal path proposed by the present invention is described in detail as follows in conjunction with the accompanying drawings and embodiments:

The present invention first uses the power detection module to detect the output power of two-way baseband variable gain amplifiers (VGA), calculates the difference, thereby obtains a measure of amplitude mismatch, then uses this measure to adjust the gain of two-way VGA to make it reach the output power equal. Further details will be given below in conjunction with the accompanying drawings.

The overall structure of the circuit for eliminating signal amplitude mismatch in the present invention is shown in FIG. 2 . The VGA outputs of I and Q channels are sent to the power detector (power detector, PD) respectively, and the power values detected by the two PDs are sent to the VGA control signal generator (VcGen) after the difference of the power values detected by the two PDs is sent to the VGA control signal generator (VcGen). Generate and adjust two VGA gain control signals Vc (Vci and Vcq in the figure) according to the difference. The circuit is balanced, and the VGA outputs of I and Q are equal.

Working principle of the present invention: assume that I, Q two-way signal amplitudes are equal (that is, power is equal), VcGen is zero input at this moment, and its DC output voltage is used as the gain control signal of VGA. If it is assumed that the amplitudes of the I and Q signals are not equal, use the difference in the power of the I and Q signals (proportional to the difference in amplitude) to adjust the DC output of VcGen to achieve a VGA that makes the I and Q signals equal in amplitude output power requirements.

The structure and principle of the circuit embodiment of each part will be described in detail below.

Fig. 3 is a schematic structural diagram of an embodiment of a circuit for eliminating amplitude mismatch of quadrature signals. Road 1 VGA output is divided into two roads, one road passes through the squarer (marked as ^2 in the figure); the other road first passes through the 90° phase shifter, and then enters the squarer. The signals output by the two squarers pass through the adder (marked as + in the figure) as input, and the output of the adder is the signal power of the I channel (|I(t)|2). Similarly, the Q-channel signal is output as the Q-channel signal power ((|Q(t)|2) through the same device. The I-channel signal power (|I(t)|2) and the Q-channel signal power ((|Q( t)|2) As input into the subtractor (Minus), the output is the difference between the two powers (proportional to the difference in amplitude), and finally this difference is used as input into the VGA control signal generator (VcGen).

The embodiment of each power detector (PD) in Figure 2 includes two squarers, a 90° phase shifter, and an adder, where the input of the first squarer is directly connected to the I or Q signal output The input end of the second squarer is connected to the I or Q signal output end through a 90° phase shifter, and the output ends of the two squarers are connected to an adder. The 90° phase shift circuit and the squarer of this embodiment are both conventional technologies, which can be found in ordinary analog circuit books. The subtractor (Minus) of this embodiment is actually a kind of adder, which can also be found .

The principle of this part of the circuit is described as follows:

Considering the amplitude mismatch of the I and Q signals, the VGA output signals of the I and Q channels can be expressed as:

I(t)＝Re{A _m e ^j(ωt+θ) } (1)

Q(t)=Re{(A _m +ΔA _m )·e ^jπ/2 ·e ^j(ωt+θ) } (2) ΔA _m represents the degree of amplitude mismatch.

In Figure 3, both I and Q signals have to undergo a 90° phase shift, and then sum the square of the original signal, which is the power detection part (PD) in Figure 2. can get:

I way:

Re{A _m e ^j(ωt+θ) } ² +Re{A _m e ^jπ/2 e ^J(ωt+θ) } ²

= A _m ² (3)

Q Road:

Re{(A _m +ΔA _m ) e ^jπ/2 e ^j(ωt+θ) } ² +Re{(A _m +Δ _m ) e ^jπ e ^j(ωt+θ) } ²

＝(A _m +ΔA _m ) ² (4)

The two results are subtracted by a subtraction circuit, (4)-(3):

(A _m +ΔA _m ) ² -A _m ² =2A _m ΔA _m +ΔA _m ²

≈2A _m ·ΔA _m (5)

Generally, A _m >>ΔA _m .

In this way, the input of VcGen is an amplitude error ΔA _m amplified by 2A _m times. VcGen thus outputs gain control signals Vci and Vcq for respectively controlling the I-way and Q-way VGAs. When equilibrium is reached, ΔA _m =0 should be satisfied.

FIG. 4 is a schematic circuit diagram of an embodiment of the VGA control signal generator (VcGen) of the present invention. VcGen includes two adders (one adder and one subtractor can be used in this embodiment, and the input polarity is indicated in the figure), four voltage-controlled current sources (two PMOS transistors and two NMOS transistors can be used in this embodiment implementation) and a low-pass filter (in this embodiment, a capacitor can be used). Its connection relationship is:

The output of the subtractor in Fig. 2 is connected with the first input of the two adders in Fig. 4 (the first input polarity of the two adders is opposite), the output terminals Vci and Vcq of VcGen are connected with the two adders The second input terminals are connected, and the output terminals of the two adders are respectively connected to the control terminals of the two sets of voltage-controlled current sources (ie, the gates of the MOS transistors in the figure). Each group of voltage-controlled current sources is composed of two voltage-controlled current sources connected in parallel. The gate of the PMOS transistor is connected to the output terminal of the adder at the same time, the source terminal of the PMOS transistor is connected to the power supply, and the source terminal of the NMOS transistor is grounded). The output of each group of voltage-controlled current sources is connected to the input of a low-pass filter (implemented by a capacitor in the figure), and the outputs of the two low-pass filters are used as the outputs Vci and Vcq of VcGen. The two output voltage terminals are externally connected to the gain control terminals of the VGA on the I and Q circuits.

The above-mentioned adder, voltage-controlled current source, and low-pass filter are all conventional standard analog circuit forms, and can be found in the book.

The principle of this part of the circuit is described as follows: track the change of ΔA _m to reach the equilibrium condition ΔA _m =0, and the VcGen module must realize such a function. As shown in Figure 4. It is assumed that the function of the VGA output signal to the gain control signal Vc is a monotonically increasing function. If ΔA _m >0, then Vci rises, and the I-way VGA output signal is strengthened; Vcq falls, and the Q-way VGA output signal is weakened until ΔA _m =0. vice versa.

An example of an application of the present invention is illustrated as follows:

Fig. 5 is a structural diagram of a zero-IF receiver applying the present invention to realize automatic gain control. The received radio frequency modulation signal is amplified by the low noise amplifier (LNA), divided into two IQ channels and down-converted to the baseband signal by the mixer (Mixer), and the multiplied signal is the quadrature signal output by the local oscillator (LO). The frequency is equal to the center frequency of the radio frequency signal. Afterwards, they are respectively passed through a filter (LPF) and amplified by a variable gain amplifier (VGA). I, Q two VGA outputs will be adjusted to be completely equal. They first calculate the power through the power detector (PD), and then subtract it to get the power difference. The VcGen module adjusts the output of VGA according to the difference to make them equal. Finally, the IQ two-way signal is sent to the digital-to-analog converter through a low-pass filter (LPF).

From the above, such a circuit topology can eliminate the quadrature signal amplitude mismatch, which is extremely helpful for improving the performance of the receiver.

Claims (3)

1. Eliminate signal amplitude mismatch circuit on a quadrature signal path, it is characterized in that, comprise: be respectively connected in the I road of quadrature signal path and two power detectors of Q road signal output end, be used for detecting I respectively , Q output power; a subtractor connected to the output terminals of the two power detectors at the same time, used to calculate the difference between the power of the I channel and the Q channel; a VGA control circuit connected to the output terminal of the subtractor Signal generator, for generating the gain control signal of I road and Q road VGA, adjusts the gain of VGA with this, makes I, Q two road output signal powers equal; Described VGA control signal generator comprises two adders, Four voltage-controlled current sources and a low-pass filter; the connection relationship is: the first input terminals of the two adders are connected to the output terminals of the subtractor, the first input polarities of the two adders are opposite, and the VGA control signal The two output terminals of the generator are respectively connected with the second input terminals of the two adders, and the output terminals of the two adders are respectively connected with the control terminals of two groups of voltage-controlled current sources; each group of voltage-controlled current sources is composed of two parallel-connected Composed of voltage-controlled current sources, the output of each group of voltage-controlled current sources is connected to the input of the low-pass filter, and the output terminals of the two low-pass filters are externally connected to the gain control terminals of the VGA on the I and Q circuits. 2. The circuit for eliminating signal amplitude mismatch on the quadrature signal path according to claim 1, wherein said power detector comprises two squarers, a 90° phase shifter and an adder, wherein The input terminal of the first squarer is directly connected to the I or Q signal output terminal, and the input terminal of the second squarer is connected to the I or Q signal output terminal through a 90° phase shifter. Both outputs are connected to an adder. 3. The circuit for eliminating signal amplitude mismatch on the quadrature signal path according to claim 1, wherein the set of voltage-controlled current sources is composed of a PMOS transistor and an NMOS transistor, wherein the two MOS transistors The drain terminals of the two MOS transistors are connected to each other as output terminals, the gates of the two MOS transistors are connected to the output terminals of the adder at the same time, the source terminals of the PMOS transistors are connected to the power supply, and the source terminals of the NMOS transistors are grounded.

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