CN1317923C - A substrate structure with built-in capacitor - Google Patents

Abstract

The present invention discloses a substrate structure with built-in capacitors. The substrate structure is composed of a single layer or multiple layers of built-in capacitor substrates, and each layer of the built-in capacitor substrate includes a plurality of capacitor units. The wires connected to each capacitor unit can be connected in parallel or in series with the help of the circuit connection layers above and below the substrate structure to form various capacitors with different capacitance values and different bandwidths to meet the needs of different circuits. Each capacitor unit can also have a signal transmission line for transmitting electrical signals of electronic components above and below the substrate structure according to different circuit designs. Therefore, the purpose of electrical signal connection can be achieved by using a simple circuit setting.

Description

A substrate structure with built-in capacitor

technical field

The invention relates to a substrate structure with a built-in capacitor, in particular to a built-in capacitor substrate structure used in the integration and shrinkage of electronic circuits.

Background technique

In order to meet the development needs of high-frequency and high-speed technology products, the signal rise time (RiseTime; tr) of the circuit system is getting faster and faster, while making the timing budget (Timing Budget) and noise margin (NoiseMargin) smaller and smaller. In addition to the selection of components, the stability of the system has an absolute relationship with the noise immunity (Noise Immunity) capability of the circuit. Among them, the three major subjects of noise suppression are reflection noise (Reflection Noise) and coupled noise (Coupled Noise). And switching noise (SwitchingNoise).

To suppress reflection noise (Reflection Noise), it is necessary to do a good job of impedance matching. To deal with Coupled Noise (Coupled Noise), attention must be paid to the control of the distance and length of parallel lines, and the switching noise (or It is called simultaneous switching noise Simultaneous Switching Noise; SSN) must rely on a large number of decoupling capacitors (De-coupling Capacitor) or bypass capacitors (Bypass Capacitor) to stabilize the power supply and filter high-frequency noise.

However, a large number of capacitor components often make the product unable to take into account the development trend of light, thin, short, and small, and the longer the path of the current loop, the greater the noise interference, so these capacitors must be kept within a certain distance from the IC ( The shorter the tr, the closer the distance) will have its effect. That is to say, even if the area of the substrate is increased to place more capacitors, the expected effect may not be achieved due to the distance between them. This is a difficult problem for electrical designers.

Although the packaging specifications of passive components are getting smaller and smaller, and the surface mount device (SMD; Surface Mount Device) is from 1210→1206→0805→0603→0402 or even 0201, the smaller the area, the smaller the capacitance that can be made. It is not easy to shrink the packaging of capacitors with larger capacitance, and the more capacitor components are used, the more complicated the layout of the substrate is, because the small size of the components also causes difficulties in the surface mount manufacturing process.

It is still not easy to reduce the size of independent capacitors with large capacitances. As mentioned above, the occupied area increases the complexity of the substrate layout, and it is also difficult in the surface mount manufacturing process. And because the generation of capacitance must have a large-area conductive plane, if it is integrated into the IC wafer (Wafer) design, it will inevitably occupy a large wafer area, which is not economically beneficial. However, in the face of faster and faster operating frequencies, if the appropriate capacitance and quantity of capacitors cannot be provided to the IC, it will be more difficult to suppress the switching noise within an acceptable range.

In order to reduce the area occupied by passive components, the current trend is to embed passive components in the substrate (Embedded passive component). The built-in substrate (Build in Substrate) technology using embedded capacitor components (Embedded Capacitor) in organic substrates can embed capacitors in substrates to achieve high density. Materials with a high dielectric constant (High Dielectric Constant), the substrate of this special manufacturing process not only has a complex structure of the entire substrate, but also increases the cost of the circuit board, and increases the difficulty of circuit board setup.

And because the dielectric constant of the material itself controls the area occupied by the built-in capacitor, that is, if the dielectric constant is not high enough, the area must be increased. This measure often results in a situation where the occupied area is too large to be practical (ceramic The dielectric constant of the substrate is about 9.5, while the dielectric constant of the common FR-4 multilayer board is only 4.7, but it must be increased to more than 100 if it is to be widely used).

In addition, since most system substrates use cheap and widely used organic substrates (Organic Substrate; such as FR-4), materials that can be used with organic substrates and whose dielectric constant is high enough to be used as capacitors are still In development and expensive, the above reasons are the bottleneck of the current built-in capacitor technology of organic substrates.

In order to solve these problems, some solutions are provided in the prior art, such as the US Patent No. 5,633,785, which utilizes an interconnect substrate (interconnect substrate) with resistance, capacitance and inductance effects, and is bonded to the substrate by wire bonding. Chip bonding, and the substrate is divided into multiple block arrays, each block is a passive component, which can produce the effects of resistance, capacitance and inductance, and then use wires (trace) to connect each block to the outer edge Bond pads for the connection of electrical signals.

Although this method provides a high-performance, high-density IC package, it will produce unnecessary inductance effect and reduce the electrical quality because of the design of the wire (trace); and must match the chip size and pin arrangement (pin assignment) to make different designs, in the actual production is not convenient.

Contents of the invention

The technical problem to be solved by the present invention is to provide a substrate structure with built-in capacitors. The substrate structure has the advantages of wide frequency, low impedance, and low switching noise, and the substrate structure can be directly bonded to the chip to effectively reduce passive The number of capacitor components and the subsequent surface mount technology (Surface Mount Technology; SMT).

In order to achieve the above object, the present invention provides a substrate structure with a built-in capacitor, which is characterized in that it includes:

More than one layer of built-in capacitor substrate, the built-in capacitor substrate is composed of more than one capacitor unit, with the help of circuit settings to form any capacitance value, the capacitor unit includes:

a dielectric layer;

a positive electrode layer connected to one side of the dielectric layer;

a negative electrode layer connected to the other side of the dielectric layer;

Wherein, the positive electrode layer, the negative electrode layer and the dielectric layer each have a positive electrode lead hole, a negative electrode lead hole, and more than one signal transmission line hole, and the positive electrode layer, the negative electrode layer are connected through the connection. Layer and each of the positive electrode lead holes, each of the negative electrode lead holes and each of the signal transmission line holes of the dielectric layer to form a positive electrode lead, a negative electrode lead and more than one signal transmission line, the positive electrode lead and The signal transmission line is insulated from the negative electrode layer, and the negative electrode lead and the signal transmission line are insulated from the positive electrode layer, and the positive electrode lead, the negative electrode lead and the signal transmission line are pulled out from the upper and lower sides of the capacitor structure , for circuit setup.

The above-mentioned substrate structure with built-in capacitor is characterized in that the positive electrode layer, the negative electrode layer and the dielectric layer each have more than one signal transmission line hole, and the positive electrode layer, the negative electrode layer and the dielectric layer are connected to each other. Each of the signal transmission line holes in the dielectric layer forms more than one signal transmission line, the signal transmission line is insulated from the negative electrode layer and the positive electrode layer, and is pulled out from the upper and lower sides of the capacitor structure for circuit configuration .

The above-mentioned substrate structure with built-in capacitor is characterized in that the signal transmission line holes of the positive electrode layer, the negative electrode layer and the dielectric layer are formed by etching.

The above-mentioned substrate structure with built-in capacitor is characterized in that the signal transmission line holes of the positive electrode layer, the negative electrode layer and the dielectric layer are formed by drilling.

The above-mentioned substrate structure with built-in capacitor is characterized in that the substrate structure further includes more than one layer of circuit connection layer, which is located on the surface of one side of the built-in capacitor substrate, and is used to connect the positive electrode lead wire of each capacitor unit and the The negative electrode leads are connected to set up the circuit, and the capacitor units are connected in series or in parallel to form a capacitor with any capacitance value.

The above-mentioned substrate structure with built-in capacitor is characterized in that the circuit connection layer is fabricated on the surface of the built-in capacitor substrate by using a printed circuit board process.

The above-mentioned substrate structure with built-in capacitor is characterized in that the circuit connection layer is fabricated on the surface of the built-in capacitor substrate by using build-up substrate manufacturing technology.

The above-mentioned substrate structure with built-in capacitors is characterized in that the line connection layer further includes more than one common wiring area, which is used to connect the positive electrode lead or the negative electrode lead connected to the same potential to the same common wiring. district.

The above-mentioned substrate structure with built-in capacitor is characterized in that the substrate structure further includes more than one layer of circuit connection layers, which are located on the surfaces of both sides of the built-in capacitor substrate, and are used to connect the positive electrode leads of each capacitor unit and the The negative electrode leads are connected to set up the circuit, and the capacitor units are connected in series or in parallel to form a capacitor with any capacitance value.

The above-mentioned substrate structure with built-in capacitor is characterized in that the circuit connection layer is fabricated on the surface of the built-in capacitor substrate by using a printed circuit board manufacturing method.

The above-mentioned substrate structure with built-in capacitor is characterized in that the circuit connection layer is fabricated on the surface of the built-in capacitor substrate by using a build-up substrate manufacturing method.

The above-mentioned substrate structure with built-in capacitors is characterized in that the line connection layer further includes more than one common wiring area, which is used to connect the positive electrode lead or the negative electrode lead connected to the same potential to the same common wiring. district.

The above-mentioned substrate structure with built-in capacitor is characterized in that the dielectric layer is composed of a material with a high dielectric coefficient.

The above-mentioned substrate structure with built-in capacitors is characterized in that the dielectric layer is fabricated in a combination of sputtering, vapor deposition, coating and printing.

The above-mentioned substrate structure with built-in capacitor is characterized in that the dielectric layer is composed of insulating chip capacitor material through lamination.

The above-mentioned substrate structure with built-in capacitor is characterized in that the positive electrode layer is fabricated in one of combinations of sputtering, vapor deposition, electroplating and copper foil lamination.

The above-mentioned substrate structure with built-in capacitor is characterized in that the fabrication method of the negative electrode layer is selected from a combination of sputtering, vapor deposition, electroplating and copper foil lamination.

The above-mentioned substrate structure with built-in capacitor is characterized in that the positive electrode lead holes and the negative electrode lead holes of the positive electrode layer, the negative electrode layer, and the dielectric layer are formed by etching.

The above-mentioned substrate structure with built-in capacitors is characterized in that the positive electrode lead holes and the negative electrode lead holes of the positive electrode layer, the negative electrode layer, and the dielectric layer are formed by drilling.

The above-mentioned substrate structure with built-in capacitor is characterized in that the positive electrode layer, the dielectric layer and the negative electrode layer are fabricated on the surface of an inorganic substrate for the capacitor unit.

The above-mentioned substrate structure with built-in capacitor is characterized in that the inorganic substrate is selected from a combination of ceramics, silicon and glass.

The above-mentioned substrate structure with built-in capacitor is characterized in that when ceramics are used as the material of the inorganic substrate, the positive electrode layer, the dielectric layer and the the negative electrode layer.

The above-mentioned substrate structure with built-in capacitor is characterized in that, when silicon is used as the material of the inorganic substrate, the positive electrode layer, the dielectric layer and the negative electrode layer are manufactured by semiconductor manufacturing technology. Since the substrate structure is closer to the chip, it can provide better noise filtering effect, and does not need to occupy an extra area like an independent capacitor, so as to achieve better space utilization.

Since the substrate structure of the built-in capacitor is composed of a single-layer or multi-layer built-in capacitor substrate, and each layer of built-in capacitor substrate is composed of multiple capacitor units, users can use this substrate structure The upper circuit connection layer arbitrarily connects the positive electrode leads and negative electrode leads connected to each capacitor unit in parallel or in series, and combines them into various capacitors with different capacitance values to meet the needs of different circuits; moreover, each capacitor The unit can have more than one signal transmission line according to the user's different circuit design. This signal transmission line is used to carry out the signal transmission of the electronic components above and below the substrate structure. Therefore, it is not necessary to use complicated circuit layout to achieve electrical signals. purpose of the connection.

Users can use this substrate structure as the core layer (core) in the printed circuit board, and then use the traditional printed circuit board manufacturing process or build-up substrate process technology layer by layer on the surface of the substrate structure Create the required circuit layer by layer.

In order to have a further understanding of the purpose of the present invention, structural features and functions thereof, the accompanying drawings describe in detail below:

Description of drawings

Fig. 1 is the three-dimensional view of the substrate structure of single-layer built-in capacitance of the present invention;

Fig. 2 is the sectional view of the substrate structure of single-layer built-in capacitance of the present invention;

3 is a perspective view of capacitor units arranged irregularly;

Figure 4 is an exploded view of a single capacitor unit;

5 is a perspective view of a substrate structure with multilayer built-in capacitors;

6 is a cross-sectional view of a substrate structure with multilayer built-in capacitors;

7 is a cross-sectional view of a substrate structure with a multilayer built-in capacitor combined with a circuit connection layer;

Figure 8 is a top view of the line connection layer;

Figure 9 is a top view of the honeycomb common wiring area; and

Figure 10 shows the substrate structure of chip-type built-in capacitors.

Among them, the reference signs indicate

100 Substrate structure with single-layer built-in capacitor

111 capacitor unit

1111 positive electrode layer

1111b Negative electrode lead hole

1111c signal transmission line hole

1112 negative electrode layer

1112a Positive electrode lead hole

1112c Signal transmission line hole

1113 dielectric layer

1113a Positive electrode lead hole

1113b Negative electrode lead hole

1113c Signal transmission line hole

114 Positive electrode lead

115 negative electrode lead

116 Signal transmission line

112 capacitor unit

113 capacitor unit

200 line connection layer

201 common wiring area

201a common wiring area

201b common wiring area

201c common wiring area

201d common wiring area

201e common wiring area

201f common wiring area

210 Conductive bumps

220 chips

230 silicon substrate

300 Substrate structure with multilayer built-in capacitors

400 chip type built-in capacitor substrate structure

Detailed ways

Please refer to FIG. 1 and FIG. 2. In the perspective view and cross-sectional view of the single-layer built-in capacitor substrate structure 100 developed by the present invention, the single-layer built-in capacitor substrate 100 is composed of one or more than one Composed of capacitor units 111.

According to the needs of the circuit design, the user can set a signal transmission line 1116 in the capacitor unit 112. When the chip above the substrate structure 100 with a single-layer built-in capacitor needs to transmit signals with the electronic components below, it can directly pass through this line. The signal transmission line 1116 conducts electrical signal conduction without resorting to complex circuit configurations to achieve the purpose of electrical signal connection, and the number of signal transmission lines 1116 can be determined according to different requirements. If there is no such requirement, please refer to FIG. 1 and FIG. 5 , there is no need to set any signal transmission line 1116 in the capacitor unit 113 . The arrangement of the capacitor units 111 in the single-layer built-in capacitor substrate 100 can be as shown in Figure 1: each capacitor unit 111 is arranged in a matrix, or as shown in Figure 3: each capacitor unit 111 is arranged irregularly, and The methods are all arranged by the user according to the required capacitance or the design of different circuits. The shape of each capacitor unit 111 is not limited to the rectangle shown in FIG. 1 , but can also be any other shape: hexagonal, octagonal, etc., and the shape can be changed according to different needs of users.

The single-layer built-in capacitor substrate structure 100 can shorten the bonding distance with the chip, and reduce the number of passive capacitor components and subsequent surface mount technology (Surface Mounting Technology, SMT) manufacturing process.

After the single-layer built-in capacitor substrate 100 is completed, the capacitor units 111 can be connected in series or in parallel with the help of circuit settings, so as to be arbitrarily combined into appropriate high-bandwidth and low-impedance capacitor values and capacitor numbers, so as to be suitable for different applications. circuit needs. For example, there are three different voltage source values in the CPU, and the user can make any combination (series or parallel) of the capacitor units 111 in the built-in capacitor substrate 110 to achieve circuit matching.

Each capacitor unit is composed of three main layers: a positive electrode layer 1111 , a negative electrode layer 1112 , and a dielectric layer 1113 sandwiched between the positive electrode layer 1111 and the negative electrode layer 1112 . The positive electrode layer 1111 and the negative electrode layer 1112 are made of conductive materials, such as metal copper. The formula for capacitance is:

C=ε×(A/d)

Where C: capacitance value

ε: Permittivity of the dielectric material

A: The area of the positive and negative electrode layers

d: distance between positive and negative electrodes

From the capacitance formula, it can be seen that the capacitance value is proportional to the dielectric coefficient of the dielectric material, and is inversely proportional to the distance between the positive and negative electrodes. Therefore, the dielectric layer 1113 is formed by an insulating material with a high dielectric constant, and A higher capacitance can be achieved by using a thinner dielectric layer 1113 .

Please refer to FIG. 3 and FIG. 4. FIG. 4 is an exploded view of a single capacitor unit 111, and each capacitor unit 111 in the substrate structure 100 of the single-layer built-in capacitor has a positive electrode layer 1111 and a negative electrode layer 1112. Each of the same positions in the dielectric layer 1113 has a positive electrode lead hole 1112a, 1113a, a negative electrode lead hole 1111b, 1113b, and one or more signal transmission line holes 1111c, 1112c, 1113c.

By connecting each positive electrode layer 1111, negative electrode layer 1112, and each positive electrode lead hole 1112a, 1111a, each negative electrode lead hole 1111b, 1113b, and each signal transmission line hole 1111c, 1112c, 1113c in the dielectric layer 1113, To form a conductive positive electrode lead 1114 , negative electrode lead 1115 and one or more signal transmission lines 1116 parallel to each other.

It can be seen from FIG. 4 that the positive electrode lead 1114 is only connected to the positive electrode layer 1111, while the negative electrode lead 1115 and the signal transmission line 1116 are insulated from the positive electrode layer 1111; and the negative electrode lead 1115 is only connected to the negative electrode layer 1111. The layer 1112 is conductive, and the positive electrode lead 1114 and the signal transmission line 1116 are insulated from the negative electrode layer 1112 .

The positive electrode lead 1114 , the negative electrode lead 1115 and the signal transmission line 1116 are pulled out from the upper and lower sides of the substrate structure 100 with built-in capacitors in a single layer for circuit arrangement. The location of each signal transmission line 1116 can be determined by the user according to the setting of the circuit. The signal transmission line 1116 will pass through the middle of each capacitor unit 111 and will not conduct with the positive electrode layer 1111 and the negative electrode layer 1112. Therefore, if the chip above the substrate structure 100 with a single-layer built-in capacitor wants to transmit signals with the electronic components below, the electrical signal can be directly connected through the signal transmission line 1116 without resorting to complicated circuit layout To achieve the purpose of electrical signal connection.

Please refer to FIG. 5 and FIG. 6, which are a perspective view and a cross-sectional view of a substrate structure 300 with a multilayer built-in capacitor. After stacking a plurality of substrate structures 100 with a built-in capacitor in a single layer, a substrate structure with a multilayer built-in capacitor is formed. 300, and the capacitor units 111 can be connected in parallel or in series with the help of the setting or layout of the circuit, so as to greatly increase the range of capacitance values and increase the flexibility of use.

Please refer to FIG. 7, the upper and lower surfaces of the substrate structure 300 of the multilayer built-in capacitor have a circuit connection layer 200, which is used to connect the positive electrode lead 1114 and the negative electrode lead of each capacitor unit 111. Step 1115 connects and sets the lines, and connects each capacitor unit 111 in series or in parallel to form a capacitor with any capacitance value. The circuit connection layer 200 is fabricated by using common printed circuit board manufacturing process or build-up substrate manufacturing technology, so as to connect and combine capacitors. Some conductive bumps 210 are fabricated on the surface of the circuit connection layer 200 for electrical signal connection between the circuit drawn from the circuit connection layer 200 and the chip 220 above the substrate structure 300 with built-in capacitors.

Of course, the packaging form of the substrate structure 300 with built-in capacitors can also be applied to Ball Grid Array (BGA), flip-chip packaging (Flip-Chip), chip-level packaging (WL-CSP) or three-dimensional stacking. Package (3D stack Package) and other packaging technologies for assembly.

Please refer to FIG. 8 , which is a top view of the line connection layer 200. The line connection layer 200 includes a plurality of common wiring areas 201. The common wiring areas 201 are composed of conductors. Therefore, they are connected to the same common wiring The lines in the area 201 are connected to each other. In the past, when the capacitor units 111 were connected in parallel, the wires connected to the electrode plates were usually connected directly. However, such a point-to-point connection would have the problem of large inductance, which would generate relatively large noise. Good way to connect.

Therefore, the present invention connects the positive electrode lead 1114 or the negative electrode lead 1115 to be connected to the same potential to the same common connection area 201, for example: only two different voltage values need to be applied, then it can be divided into multiple pieces corresponding to each other. On the common wiring areas 201a and 201b with different voltage values, one voltage value is applied to the common wiring area 201a, while the other voltage value is applied to the common wiring area 201b.

Therefore, as shown in FIG. 9 , different numbers and different shapes of common wiring areas 201c, 201d, 201e, and 201f can be designed on the line connection layer 200 according to different needs of users, such as honeycomb, square, and round. Shape, etc., and the common wiring areas 201c, 201d, 201e, 201f corresponding to different voltage values are arranged in a staggered manner.

The advantage of this common wiring area 201 is that when pulling the wires, you only need to pull the wires to be connected to the same potential to the same common wiring area 201, and then the electrical signal of the entire common wiring area 201 will be turned on, so the inductance can be effectively reduced effect. However, the common wiring area 201 and the signal transmission line 1116 are insulated from each other. Therefore, the signal transmission line 1116 can pass through each capacitor unit 111 and the common wiring area 201 without circuit conduction.

In the above-mentioned substrate structure 100 with built-in capacitors in a single layer or the substrate structure 300 with built-in capacitors in multiple layers, the positive electrode layer 1111 and the negative electrode layer 1112 can be fabricated by sputtering, vapor deposition, or metal plating to form conductive positive electrodes. The electrode layer 1111 and the negative electrode layer 1112 ; and the dielectric layer 1113 can be fabricated by sputtering, vapor deposition, coating or printing to form an insulating dielectric layer 1113 .

Alternatively, the dielectric layer 1113 is formed by lamination of insulating sheet capacitor materials, and then the upper and lower positive electrode layers 1111 and negative electrode layers 1112 are produced by lamination of copper foil. After multiple lamination and lamination The substrate structure 300 of the multilayer built-in capacitor can be formed. Each positive electrode lead hole 1112a, 1113a, each negative electrode lead hole 1111b, 1113b in each layer of positive electrode layer 1111, negative electrode layer 1112 and dielectric layer 1113, and each signal transmission line hole 1111c, 1112c, 1113c, can be Each through-hole is made by etching or drilling.

And another way to make the capacitor unit 111 is to make the positive electrode layer 1111, the dielectric layer 1113 and the negative electrode layer 1112 sequentially on the surface of an inorganic substrate, and the material of the inorganic substrate can be selected from ceramics, silicon or It is glass.

When ceramics are used as the material of the inorganic substrate, each layer of the positive electrode layer 1111 , the dielectric layer 1113 and the negative electrode layer 1112 can be produced by using the mature thick film process technology or thin film process technology.

Please refer to FIG. 10, and when silicon is used as the material of the inorganic substrate, each layer of positive electrode layer 1111, dielectric layer 1113 and negative electrode layer 1112 can be fabricated on the surface of the silicon substrate 230 using semiconductor manufacturing technology. , forming a chip-type built-in capacitor substrate structure 400; the chip-type built-in capacitor substrate structure 400 uses conductive bumps 210 on its surface to connect electrical signals with the chip 220 above it, so as to effectively reduce the thickness of the entire module .

The substrate structure 100 with built-in capacitors in a single layer or the substrate structure 300 with built-in capacitors in multiple layers can also be applied to the layout of integrated circuits at the same time, so as to directly form a system chip (System on Chip; SOC) in the semiconductor manufacturing process, and there will be Facilitate the integration of the substrate with other components.

The substrate structure 100 with built-in capacitors in a single layer or the substrate structure 300 with built-in capacitors in multiple layers can be applied to different packaging forms of various chips, for example: ball grid array package (Ball Grid Array; BGA), flip-chip package (Flip- Chip), wafer-level packaging (WL-CSP) or three-dimensional stack packaging (3D StackPackage), etc.; therefore, the current mature manufacturing technology and packaging technology are used for production and packaging in real time, so as to directly carry out mass production.

The above-mentioned contents are only preferred embodiments of the present invention, and are not used to limit the implementation scope of the present invention; that is, all equivalent changes and modifications made according to the main concept of the present invention are all covered by the protection scope of the claims of the present invention. cover.

Claims (20)

1, a kind of board structure of built-in electric capacity is characterized in that, includes:

The built-in capacity substrate that one deck is above, this built-in capacity substrate is made up of more than one capacitor cell, and to form any capacitance, this capacitor cell includes by the circuit setting:

One dielectric layer;

One positive electrode layer is connected in a side of this dielectric layer;

One positive electrode layer is connected in the opposite side of this dielectric layer;

Wherein, this positive electrode layer, respectively has a positive electrode fairlead in this positive electrode layer and this dielectric layer, one negative electrode fairlead and more than one signal transmssion line hole, by connecting this positive electrode layer of conducting, respectively this positive electrode fairlead of this positive electrode layer and this dielectric layer, respectively this negative electrode fairlead and respectively this signal transmssion line hole, to form positive electrode lead-in wire, one negative electrode lead-in wire and more than one signal transmssion line, this positive electrode lead-in wire and this signal transmssion line and the insulation of this positive electrode layer, and this negative electrode lead-in wire and this signal transmssion line and the insulation of this positive electrode layer, and this positive electrode lead-in wire, this negative electrode lead-in wire and this signal transmssion line are pulled out in the both sides up and down of this capacitance structure, to carry out the circuit setting;

The circuit articulamentum that one deck is above, be positioned at the surface of these built-in capacity substrate one or both sides, and respectively this positive electrode lead-in wire and this negative electrode lead-in wire of this capacitor cell connect to carry out the setting of circuit, and respectively this capacitor cell is connected or be in parallel, to form the electric capacity of any capacitance.

2, the board structure of built-in electric capacity according to claim 1 is characterized in that respectively this signal transmssion line hole of this positive electrode layer, this positive electrode layer and this dielectric layer utilizes etched mode to form.

3, the board structure of built-in electric capacity according to claim 1 is characterized in that, respectively this signal transmssion line hole of this positive electrode layer, this positive electrode layer and this dielectric layer utilizes the mode of boring to form.

4, the board structure of built-in electric capacity according to claim 1 is characterized in that, this circuit connects series of strata and utilizes the printed circuit board (PCB) processing procedure to be made in the surface of this built-in capacity substrate.

5, the board structure of built-in electric capacity according to claim 1 is characterized in that this circuit articulamentum utilizes the Layer increasing method substrate fabrication techniques to be made in the surface of this built-in capacity substrate.

6, the board structure of built-in electric capacity according to claim 1, it is characterized in that, this circuit articulamentum more includes more than one common Wiring area, is connected to this identical common Wiring area in order to this positive electrode lead-in wire or this negative electrode lead-in wire that will be connected to same potential.

7, the board structure of built-in electric capacity according to claim 1 is characterized in that this circuit articulamentum is to utilize board, printed circuit board manufacturing method to be made in the surface of this built-in capacity substrate.

8, the board structure of built-in electric capacity according to claim 1 is characterized in that this circuit articulamentum is to utilize the Layer increasing method manufacture of substrates to be made in the surface of this built-in capacity substrate.

9, the board structure of built-in electric capacity according to claim 1, it is characterized in that, this circuit articulamentum more includes more than one common Wiring area, is connected to this identical common Wiring area in order to this positive electrode lead-in wire or this negative electrode lead-in wire that will be connected to same potential.

10, the board structure of built-in electric capacity according to claim 1 is characterized in that this dielectric layer is made up of the material of high-dielectric coefficient.

11, the board structure of built-in electric capacity according to claim 1 is characterized in that, the production method of this dielectric layer is to be selected from by sputter, evaporation, coating and printshop to become one of combination.

12, the board structure of built-in electric capacity according to claim 1 is characterized in that, this dielectric layer is to utilize insulating properties flaky electric capacity material to form through pressing.

13, the board structure of built-in electric capacity according to claim 1 is characterized in that, the production method of this positive electrode layer is to be selected from by sputter, evaporation, plating and Copper Foil pressing institute to become one of combination.

14, the board structure of built-in electric capacity according to claim 1 is characterized in that, the production method of this positive electrode layer is to be selected from by sputter, evaporation, plating and Copper Foil pressing institute to become one of combination.

15, the board structure of built-in electric capacity according to claim 1 is characterized in that, respectively this positive electrode fairlead of this positive electrode layer, this positive electrode layer and this dielectric layer, this negative electrode fairlead respectively are to utilize etched mode to form.

16, the board structure of built-in electric capacity according to claim 1 is characterized in that, respectively this positive electrode fairlead of this positive electrode layer, this positive electrode layer and this dielectric layer, this negative electrode fairlead respectively are to utilize the mode of boring to form.

17, the board structure of built-in electric capacity according to claim 1 is characterized in that this capacitor cell is to produce this positive electrode layer, this dielectric layer and this positive electrode layer in the surface of an inorganic substrate.

As the board structure of built-in electric capacity as described in the claim 17, it is characterized in that 18, this inorganic substrate system is selected from by pottery, silicon and glass institute and becomes one of combination.

19, as the board structure of built-in electric capacity as described in the claim 18, it is characterized in that, when adopting pottery, be to be selected from by thick film process technique and thin film manufacture process technology institute to become one of combination to make this positive electrode layer, this dielectric layer and this positive electrode layer as the material of this inorganic substrate.

20, as the board structure of built-in electric capacity as described in the claim 18, it is characterized in that, when adopting silicon as the material of this inorganic substrate, is to utilize semiconductor fabrication to make this positive electrode layer, this dielectric layer and this positive electrode layer.

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