CN1317747C - Semiconductor device passivation method - Google Patents

Abstract

The invention discloses a passivation method of a semiconductor device, which comprises the steps of carrying out high-pressure annealing on the semiconductor device and carrying out plasma treatment (plasma treatment) on the semiconductor device so as to eliminate electric charges accumulated in the semiconductor device after the high-pressure annealing. The process gas used for the plasma treatment may be nitrogen, hydrogen, water, nitrous oxide, oxygen, ammonia, or mixtures thereof.

Description

Semiconductor device passivation method

technical field

The invention relates to a passivating method of a semiconductor device, which is used to repair the defects of the semiconductor device produced in the front-stage process.

Background technique

Semiconductor devices are typically fabricated through multiple process steps which may include sputter deposition, photolithography, wet etch, plasma etch, chemical vapor deposition, plasma assisted chemical vapor deposition, ion implantation, and activation and drive An annealing step for implanting ions. Some of these process steps can cause defects in the semiconductor device. For example, the plasma etching process will produce silicon dangling bonds (silicon dangling bonds), and the silicon dangling bonds will further lead to a decrease in electron mobility (electron mobility), making the characteristics of the semiconductor device worse, and the ion implantation process may also damage the silicon. damage to the crystal structure.

Recently, a high pressure annealing process has been developed to reduce the problems caused by the bond breaking of silicon. In the high-pressure annealing process, the semiconductor device is generally heated by passing a high-pressure gas (such as hydrogen or ammonia). It is generally believed that the introduced hydrogen will form bonds with broken bonds of silicon in the semiconductor device, so as to remove defects generated in the front-end process in the semiconductor device. However, the high-pressure annealing process often causes charge accumulation in the semiconductor device, causing its threshold voltage (threshold voltage) to drift, thereby affecting the operation of the designed circuit.

Contents of the invention

The purpose of the present invention is to provide an improved semiconductor device passivating method to overcome or improve the problems of the prior art.

According to the semiconductor device passivation method disclosed in the present invention, it includes performing a high pressure annealing (high pressure annealing) on the semiconductor device, and performing a plasma treatment (plasma treatment) on the semiconductor device, in order to eliminate the high pressure annealing after the high pressure annealing , the charge accumulated in the semiconductor device. The high pressure annealing process includes placing the semiconductor device in a chamber; passing a reactive gas (such as nitrogen, hydrogen, water, ammonia or a mixture thereof); and heating the semiconductor device until passivation occurs.

The plasma treatment can be achieved by electron cyclotron resonance (ECR) or inductively coupled plasma (ICP). And the process gas used therein may be nitrogen, hydrogen, water, nitrous oxide, oxygen, ammonia or a mixture thereof. And the process of plasma treatment is to place the sample chamber of the semiconductor device, connect a heater and apply an electric bias (electric bias), so that the process gas that passes through can be ionized into ions or free radicals. The application of high temperature and/or electric field diffuses into the semiconductor device, thereby eliminating the charge accumulated in the semiconductor device.

The semiconductor device may be a thin film transistor containing a polysilicon film layer.

Description of drawings

1 to 4 are cross-sectional views according to an embodiment of the present invention, showing the main steps of a semiconductor device passivation method;

5 to 6 are cross-sectional views illustrating main steps of a semiconductor device manufacturing method according to an embodiment of the present invention; and

FIG. 7 is a graph of voltage applied to the gate versus current flowing through the drain.

Explanation of reference signs

100' semiconductor device

100 semiconductor device

102 buffer layer 104 substrate

110 PMOS transistor 111 Semiconductor structure

112 semiconductor structure 114 source

116 Drain 118 Gate electrode

120 NMOS transistors 124 sources

126 Drain 128 Gate electrode

130 passivation layer 132 nitride film

150 gate dielectric layer

200 CMOS circuits

Detailed ways

Referring to FIG. 1, there is shown a cross-sectional view of a semiconductor device 100' passivated in accordance with the principles of the present invention. The semiconductor device 100' has a P-channel metal-oxide-semiconductor (PMOS) transistor 110 and an N-channel metal-oxide-semiconductor (NMOS) transistor 120 . And the semiconductor device 100' can be a Complementary Metal Oxide Semiconductor (CMOS) device, a Bicarrier Complementary Metal Oxide Semiconductor (BiCMOS) device, a Dynamic Random Access Memory (DRAM) or other types of integrated circuits. And a semiconductor device suitable for the present invention may be a thin film transistor including a polysilicon film layer.

As shown in FIG. 1, the semiconductor device 100' includes: a buffer layer 102 (such as a silicon dioxide layer), formed on a substrate 104 (such as a glass substrate); two semiconductor structures 111, 121 (generally polysilicon thin films ), formed on the buffer layer 102; a gate dielectric layer 150 (such as a silicon oxide layer), formed on the semiconductor structures 111, 121; and two gate electrodes 118, 128. The source 114 and the drain 116 of the PMOS transistor 110 use the gate electrode 118 as a mask to self-align (self-align) with P-type doping by ion implantation or plasma doping. The dopant is implanted into the semiconductor structure 111 to form. The source 124 and the drain 126 of the NMOS transistor 120 are formed by implanting N-type dopants into the semiconductor structure 121 using the gate electrode 128 as a mask.

Referring to FIG. 2, after forming a passivation layer 130 (such as a silicon dioxide layer) on the entire surface of the semiconductor device 100', the defects generated in the semiconductor device 100 in the front-end process, such as dangling bonds (unsaturated silicon bond), the semiconductor device 100 is repaired by performing a high pressure annealing process (high pressure annealing). The process is to place the semiconductor device 100 in a reaction chamber, and then pass a reaction gas such as water vapor, nitrogen, ammonia or hydrogen into the reaction chamber under high pressure for heat treatment. However, in a preferred embodiment, the high pressure annealing treatment is performed between 5 atmospheres and 20 atmospheres. In one embodiment, the high pressure annealing process may be performed at a temperature lower than 600°C. The time for this high pressure annealing treatment depends on the pressure used. Since the high pressure annealing process is performed under high pressure, its temperature and time can be effectively reduced. Those skilled in the art can obtain the optimum conditions for the high pressure annealing treatment of the present invention according to the above process parameters.

However, due to the high pressure annealing process often causes charge accumulation (charges are shown in FIG. The voltage (threshold voltage) drifts, thereby affecting the operation of the designed circuit.

Therefore, referring to FIG. 4 , the present invention further performs a plasma treatment process on the semiconductor device 100 to eliminate the charge accumulated in the semiconductor device 100 after the high pressure annealing treatment. The process is to connect the sample chamber where the semiconductor device 100 is placed to a heater and apply an electric bias (electric bias), so that the incoming process gas can be ionized into the state of ions or free radicals. The electric field diffuses into the semiconductor device 100 , thereby eliminating the charges accumulated in the semiconductor device 100 . This plasma treatment can be realized by electron cyclotron resonance (ECR) or inductively coupled plasma (ICP); and the process gas used can be nitrogen, hydrogen, water, dioxide Nitrogen, oxygen, ammonia or mixtures thereof. It can be understood that the passivation method of the present invention can also be implemented before forming the passivation layer 130 .

The invention also provides another semiconductor device passivation method. First, the above-mentioned PMOS transistor 110 or NMOS transistor 120 is formed over the substrate 104 . A passivation layer 130 (such as a silicon dioxide layer) is then formed on the PMOS transistor 110 and the NMOS transistor 120, and the high-voltage annealing treatment is performed. Referring to FIG. 5 , a nitride film (nitride film) 132 (such as a silicon nitride film or a silicon oxide nitride film) is formed on the passivation layer 130 . Finally, referring to FIG. 6 , the nitride thin film 132 is reheated to eliminate the charges accumulated in the semiconductor device 100 after the high pressure annealing (charges are shown in FIGS. 5 and 6 with star symbols). The heat treatment may be furnace annealing or rapid thermal annealing.

Using the method of the present invention can effectively reduce the charge accumulated in the semiconductor device 100 , thereby effectively reducing the drift caused by the threshold voltage of the semiconductor device 100 , so that the designed circuit operates normally. Figure 7 shows the relationship between the voltage applied to the gate and the current flowing through the drain. Curve A shows the Id-Vg characteristic curve of the semiconductor device without high-pressure annealing treatment, curve B shows the Id-Vg characteristic curve of the semiconductor device after high-pressure annealing treatment, and curve C shows the Id-Vg characteristic curve of the semiconductor device after high-pressure annealing treatment and O ₂ Id-Vg characteristics of plasma-treated semiconductor devices. It can be seen from the figure that the device characteristics of the semiconductor device after the high pressure annealing treatment and the O ₂ plasma treatment are most in line with the ideal operation mode of the circuit operation.

Although the present invention is discussed in detail with respect to a complementary metal-oxide-semiconductor (CMOS) circuit for an active-matrix display device, the present invention is also applicable to a variety of Or a semiconductor device of a silicon metal oxide semiconductor field effect transistor (SOI MOSFET) on an insulating layer.

Although the present invention has been disclosed with the above-mentioned preferred embodiments, it is not intended to limit the present invention. Those skilled in the art should be able to make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection should be defined by the appended claims.

Claims (6)

1. A semiconductor device passivation method, which at least comprises the following steps to the semiconductor device: a high pressure annealing step for repairing defects generated in the semiconductor device; and A plasma treatment step is used to remove the charges generated in the semiconductor device. 2. The semiconductor device passivation method as claimed in claim 1, wherein the high pressure annealing step comprises at least: placing the semiconductor device in a reaction chamber; passing a reactive gas into the reaction chamber; and The semiconductor device is heated until sufficient to produce passivation. 3. The semiconductor device passivation method as claimed in claim 2, wherein the reactive gas is one of nitrogen, hydrogen, water, ammonia or a mixture thereof. 4. The semiconductor device passivation method as claimed in claim 1, wherein a process gas used in the plasma treatment step is one or a mixture thereof in nitrogen, hydrogen, water, nitrous oxide, oxygen, ammonia . 5. The semiconductor device passivation method as claimed in claim 1, wherein the semiconductor device is a thin film transistor comprising a polysilicon film layer. 6. The semiconductor device passivation method as claimed in claim 1, wherein the semiconductor device passivation method is performed before forming a passivation layer on the semiconductor device.

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