CN1311397C - Storage device - Google Patents
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- CN1311397C CN1311397C CNB2003101188096A CN200310118809A CN1311397C CN 1311397 C CN1311397 C CN 1311397C CN B2003101188096 A CNB2003101188096 A CN B2003101188096A CN 200310118809 A CN200310118809 A CN 200310118809A CN 1311397 C CN1311397 C CN 1311397C
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/073—Special arrangements for circuits, e.g. for protecting identification code in memory
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/073—Special arrangements for circuits, e.g. for protecting identification code in memory
- G06K19/07309—Means for preventing undesired reading or writing from or onto record carriers
- G06K19/07363—Means for preventing undesired reading or writing from or onto record carriers by preventing analysis of the circuit, e.g. dynamic or static power analysis or current analysis
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Abstract
在IC卡等存储装置中提高存储的数据的隐匿性。数据屏蔽部(124)只在从时钟信号的沿时刻经过规定的期间后输出从存储器阵列单元(121)中读出的存储数据，微型计算机(110)在时钟信号的沿时刻内取入从数据屏蔽部(124)输出的数据。因此，由于微型计算机(110)只能在时钟信号的频率处于规定范围内的情况下可以正确地取入存储数据，故可以使非法的存储数据取得变得困难。另外，在上述规定的期间以外的时间，若从数据屏蔽部(124)输出随机数据等，则进一步使存储数据的解析变得困难，可以提高隐匿性。
Improve the concealment of stored data in storage devices such as IC cards. The data masking part (124) outputs the stored data read from the memory array unit (121) only after a predetermined period has passed from the edge time of the clock signal, and the microcomputer (110) takes in the slave data within the edge time of the clock signal. Data output by the masking unit (124). Therefore, since the microcomputer (110) can correctly fetch stored data only when the frequency of the clock signal is within a predetermined range, illegally obtained stored data can be made difficult. In addition, when random data or the like is output from the data masking unit (124) at times other than the above-mentioned predetermined period, analysis of the stored data becomes more difficult, and the concealment can be improved.
Description
Technical field
The present invention relates to have the memory storages such as IC-card of semiconductor memory and processor, particularly belong to and improve the invisible technology that is stored in the data in the above-mentioned semiconductor memory.
Background technology
In recent years, see that the market of the memory storages such as for example IC-card that possess microcomputer and semiconductor storage portion enlarges rapidly, be applied to various uses.
Especially for personal data or money data storage in the purposes in the IC-card etc. is also being popularized.Be used under the situation of this purposes, what be stored in inner data invisiblely becomes important aspect.
On the other hand, for the enterprise of the manufacturing of carrying out IC-card or utilization, in exploitation during IC-card or when the IC-card of market delivery produces fault, often need to read and resolve etc. with being stored in inner data.
Therefore, seek to reach and prevent third party's sense data mala fide, simultaneously the purpose that in the exploitation of IC-card etc., inner data is read easily.
As reaching the above-mentioned secret protection and the technology of facilitation such as parsing purpose simultaneously, propose intrinsic number is remained on the IC-card, the technical scheme (for example, with reference to patent documentation 1) of switch is carried out in contrast by gate circuit from the number of host apparatus input.
In addition, also known have will storage data self encipherment, even data are read the technology that can not be understood easily.
(patent documentation 1)
The spy of Japan opens flat 6-139422 communique
Yet in a single day the method for the intrinsic number of above-mentioned contrast has just become unguard when revealing its number.In addition, also there is the possibility that secret is cracked by a series of number is imported successively.Have again, occur IC-card is decomposed, contact with wiring and during situation that its parsing is such, it also is difficult keeping secret with probe.
Have again, when the situation that data are encrypted, owing to invisiblely decide, so may not necessarily obtain high invisible according to Cipher Strength.
Summary of the invention
In view of the above problems, the objective of the invention is to, can more easily improve the invisible of memory storage such as IC-card, also can read internal data easily as required simultaneously.
In order to solve above-mentioned problem, the settling mode that one of the present invention's invention is set forth, be that a kind of constituting possesses storer and microcomputer, according to from the clock signal of outside input or the clock signal that produces therefrom, be taken into memory storage in the described microcomputer with being stored in data in the described storer, it is characterized in that
Possess: output expression is read predetermined pulse the control signal along the clock signal output circuit through the clock signal in the moment after the stipulated time from what read the storage data from above-mentioned storer in control; With according to above-mentioned clock signal, just the data that are stored in the above-mentioned storer can be taken into the sense data control circuit of controlling like that in the above-mentioned microcomputer according to having only when above-mentioned clock signal when at least 1 assigned frequency.
According to this formation, if clock signal is not the frequency of regulation, the storage data that then will not be stored in the storer are taken into microcomputer, and not to the output of the outside of memory storage, simultaneously, microcomputer also can move improperly.So the behavior of resolving the storage data under the low-clock signal frequency irrelevantly that prevents from most cases to carry out can easily improve the invisible of the data of storing in the memory storage.
In addition, the present invention's two invention in one of the present invention's memory storage, is characterized in that above-mentioned sense data control circuit constitutes according to above-mentioned clock signal, to the data of reading from above-mentioned storer whether to above-mentioned microcomputer output; At least one to the sequential that the sequential and the above-mentioned microcomputer of above-mentioned microcomputer output is taken into the data of reading from above-mentioned storer of the data of reading from above-mentioned storer controlled.
Have again, the present invention's three invention, in the present invention's two memory storage, it is characterized in that, above-mentioned sense data control circuit constitutes, according to the moment of being represented by above-mentioned clock signal and above-mentioned relativeness of reading in the control signal between the moment that produces the pulse edge after also leaning on than afore mentioned rules pulse edge, whether the data that control is read from above-mentioned storer are to above-mentioned microcomputer output.
Also have, the present invention's four invention in the present invention's two memory storage, is characterized in that, above-mentioned sense data control circuit constitutes, and the data that will read from above-mentioned storer are only exported to above-mentioned microcomputer in the specified time limit corresponding with above-mentioned clock signal.
In addition, the present invention's five invention, in the present invention's two memory storage, it is characterized in that, also possesses the screened circuit that the data of will read from storer are exported to above-mentioned microcomputer in only during regulation, simultaneously, above-mentioned sense data control circuit constituted the above-mentioned microcomputer of control and be taken into the data of exporting from above-mentioned screened circuit in the stipulated time corresponding with above-mentioned clock signal.
According to this formation, as above above-mentioned, the storage data that are stored in the storer are taken in the microcomputer.
Also have, the present invention's six invention is in the present invention's three memory storage, it is characterized in that, above-mentioned sense data control circuit constitutes, and when the data of reading from above-mentioned storer do not output to above-mentioned microcomputer, exports the data different with the data of reading from above-mentioned storer.
Also have, the present invention's seven invention in the present invention's four memory storage, is characterized in that the output data different with the data of reading from above-mentioned storer beyond above-mentioned sense data control circuit constitutes during afore mentioned rules.
Also have, the present invention's eight invention is the present invention's five a memory storage, it is characterized in that: the output data different with the data of reading from above-mentioned storer beyond above-mentioned screened circuit constitutes during afore mentioned rules.
According to this formation, certainly, in clock signal is not under the situation of frequency of regulation, the storage data are not taken in the microcomputer, simultaneously, even decomposing memory storage, probe contacted with the transmission route of storing data and under the resolved situation, because the correct storage data of identification are difficult, so can prevent easily that still illegal information from obtaining.
Have again, the present invention's nine invention, in one of the present invention's memory storage, it is characterized in that, also possesses temperature sensing circuit, above-mentioned sense data control circuit constitutes, and only when detecting the temperature of regulation by the said temperature testing circuit, just controls the data that will be stored in the above-mentioned storer and is taken in the above-mentioned microcomputer.
In addition, the present invention's ten invention, in one of the present invention's memory storage, it is characterized in that, also possesses optical detection circuit, above-mentioned sense data control circuit constitutes, and only in the light time that is detected prescribed strength by above-mentioned optical detection circuit, just controls the data that will be stored in the above-mentioned storer and is taken in the above-mentioned microcomputer.
According to this formation, owing under detected temperature or the unaccommodated situation of light intensity, the storage data can not be taken in the microcomputer, so can prevent easily further that illegal information from obtaining.
Also have, the present invention's 11 invention is that a kind of constituting possesses storer and microcomputer, according to from the clock signal of outside input or the clock signal that produces therefrom, be taken into memory storage in the above-mentioned microcomputer with being stored in data in the above-mentioned storer, it is characterized in that
Possess: the screened circuit that the data that will read from above-mentioned storer are just exported to above-mentioned microcomputer in only during regulation; Control changeably during the afore mentioned rules of the data that the output of above-mentioned screened circuit reads from above-mentioned storer, and above-mentioned microcomputer is taken into from the sequential control circuit of the data time sequence of above-mentioned screened circuit output.
In addition, the present invention's 12 invention, in the present invention's 11 memory storage, it is characterized in that, above-mentioned sequential control circuit constitutes, according to being stored in the data in the regulation zone in the above-mentioned storer, from the address of above-mentioned microcomputer output and from the specified signal of above-mentioned microcomputer output at least 1, set during the afore mentioned rules of the data that the output of above-mentioned screened circuit reads from above-mentioned storer, and above-mentioned microcomputer is taken into from the sequential of the data of above-mentioned screened circuit output.
According to this formation, when storer carries out access, because the storage data are transfused to the sequential difference of microcomputer, so can make the decomposition memory storage, the transmission route of storage data is contacted the difficulty that the operation of resolving becomes with probe, certainly raising easily is stored in the invisible of data in the memory storage.
Description of drawings
Fig. 1 is the calcspar that the integral body of the IC-card 100 of expression embodiment 1 constitutes.
Fig. 2 is the circuit diagram of concrete formation of the data mask portion 124 of presentation graphs 1.
Fig. 3 is the sequential chart of the action under suitable clock frequency of presentation graphs 1.
Fig. 4 is the sequential chart of the action under unsuitable clock frequency of presentation graphs 1.
Fig. 5 is the calcspar that the integral body of the IC-card 100 of expression embodiment 2 constitutes.
Fig. 6 is the circuit diagram of concrete formation of the data mask portion 224 of presentation graphs 2.
Fig. 7 is the sequential chart of the action under suitable clock frequency of presentation graphs 2.
Fig. 8 is the sequential chart of the action under unsuitable clock frequency of presentation graphs 2.
Fig. 9 is the calcspar that the integral body of the IC-card 100 of expression embodiment 3 constitutes.
Figure 10 is the calcspar that the integral body of the IC-card 100 of expression embodiment 4 constitutes.
Figure 11 is the calcspar that the integral body of the IC-card 100 of expression embodiment 5 constitutes.
Figure 12 is the calcspar that the integral body of the IC-card 100 of expression embodiment 6 constitutes.
Figure 13 is the calcspar that the integral body of the IC-card 100 of expression embodiment 7 constitutes.
Among the figure: 100-IC-card, 110-microcomputer, 111-register, 120-semiconductor storage portion, 121-cells of memory arrays, 121a-row decoder, 121b-column decoder, 121c-memory array, 122-sensor amplifier, 123-output buffer, 124-data mask portion, 124a-AND circuit, 125-data mask signal generating circuit, 126-access-control scheme, 224-data mask portion, 224a-selector switch, 231-random data produces circuit, 325-data mask signal generating circuit, 331-temperature sensing circuit, 431-optical detection circuit, 512-address arithmetic circuit, 513-latch signal produces circuit, 525-data mask signal generating circuit, 531-address arithmetic circuit, 613-latch signal produces circuit, 625-data mask signal generating circuit, 714-sequential control portion.
Embodiment
Below, with reference to accompanying drawing, the IC-card as memory storage of embodiments of the present invention is described.
(embodiment 1)
Fig. 1 is the calcspar that the integral body of the IC-card 100 of expression embodiment 1 constitutes.
In this figure, microcomputer 110 (processor), possesses the register 111 that is taken into the data of from semiconductor storage described later portion 120, reading, be according to the clock signal that will obtain, carry out the device of the input and output control of data of IC-card 100 or various data processing etc. from the clock signal frequency division or the frequency multiplication of outside input.More detailed saying is stored in program in the semiconductor storage portion 120 etc. by execution, will write semiconductor storage portion 120 from the data of outside input, and perhaps the data that will read from semiconductor storage portion 120 or the data of carrying out predetermined processing are exported to the outside.
Above-mentioned semiconductor storage portion 120, be used to store program or the various data that microcomputer 110 is carried out, possess: memory array cell 121, sensor amplifier 122, output buffer 123, data mask portion 124 (sense data control circuit), data mask signal generating circuit 125 (timing signal output circuit) and access-control scheme 126.
Above-mentioned memory array cell 121, be actually the parts of maintenance program or data, according to row address and column address,, carry out data and write or read zone by the memory array 121c of row decoder 121a and column decoder 121b appointment from access-control scheme 126 input.
Data mask signal generating circuit 125, for example, as shown in Figure 3, only from clock signal frequency division (or frequency multiplication) after the moment T3 that negative edge the control signal departs from time t1 that reads begin, in during the time t2 till the T5 constantly, output becomes the data mask signal of H level.Here, above-mentioned time t1, t2 if the cycle of suitable clock signal is tck, then are redefined for
t1＜tck＜t2。
Access-control scheme 126 is that control is by the parts of microcomputer 110 to the access of memory array cell 121.More detailed saying, for example, according to reading control signal, mode signal and address signal, action control signal, the latch signal of output row address signal and column address signal or 122 actions of control sensor amplifier and set the not shown mode control signal of various readout modes etc. from microcomputer 110 output.
And, usually, write circuit that data use etc. though on memory array cell 121, also be provided with, for convenience of description, in this omission.
In the IC-card of above-mentioned formation, if explanation is stored in the action of reading of data in the memory array cell 121 simply, then for example, 1 time read the sequential of action corresponding to 2 cycles of clock signal.In addition, from the control signal of reading of access-control scheme 126 outputs, in the 1 initial cycle, be the L level, only sensor amplifier 122 is in operating state in during this period.From being in the data-signal that amplifies 122 outputs of reading of this operating state,, be latched to the moment of the 2nd end cycle by output buffer 123 always.The output of output buffer 123 is by data mask portion 124 shielding, as mentioned above, exports the active data signal in only during the T3～T5 of regulation.In the moment of microcomputer 110 clock signal negative edge when the end in the 1st cycle, be taken into from the data of data mask portion 124 outputs.
Below, as more detailed action specification, when clock signal is the frequency of regulation, read the data that are stored in the memory array cell 121, describe from the action of microcomputer 110 under the situation of the outside of IC-card output.
At first, from the outside input clock signal of IC-card, simultaneously as the input data, the input expression with the data in the memory array cell 121 directly to the control data of the pattern of outside output and specify and read the address date of address.
Here, microcomputer 110, for example, and as shown in Figure 3, at mode signal and the address signal of moment T0 to access-control scheme 126 output expression readout modes.Corresponding, access-control scheme 126 is to row decoder 121a and column decoder 121b output row address signal and column address signal, the zone of sense data among the designated memory array 121c.
Then, microcomputer 110, at the moment of clock signal negative edge T1, making and reading control signal is the L level.Therefore, access-control scheme 126, to sensor amplifier 122 output action control signals (supply voltage or ground voltage), sensor amplifier 122 becomes operating state, through (T2 constantly) after the non-steady state during certain degree, export the level signal corresponding with the memory contents of memory array cell 121.Output buffer 123 will directly be exported from the level signal of sensor amplifier 122 outputs.
Access-control scheme 126, at the stable above-mentioned moment T2 of the output of above-mentioned sensor amplifier 122 in the later stipulated time, make the latch signal to output buffer 123 outputs for example be the H level, output buffer 123 keeps from the signal level of sensor amplifier 122 outputs constantly at this.Promptly, output from the action control signal of access-control scheme 126, stop at the moment T4 that reads control signal and become the H level, though the output of sensor amplifier 122 plays pendulum, but output buffer 123, for example, continue the data-signal of the output level corresponding with the memory contents of memory array cell 121 up to reading the moment T6 that control signal becomes the L level.
In addition, data mask signal generating circuit 125, only through after the stipulated time t1, only (making the data mask signal in the T3～T5) is the H level during time t2 from the decline (T1) of reading control signal.Therefore, data mask portion 124 will be output the data-signal that impact damper 123 keeps in only during above-mentioned moment T3～T5 and export.
On the other hand, microcomputer 110 at the moment T4 that clock signal descends, is taken into the data of promptly reading from memory array cell 121 from the data-signal of data mask portion 124 outputs, after the processing of data was carried out in inside, to the output of the outside of IC-card.That is, in the frequency of clock signal, (T1～T4) is under the situation of the frequency in the scope of t1+t2, and the storage data are taken in the microcomputer 110 rightly, and are output to the outside of IC-card for its cycle.
Yet, the frequency of clock signal is not under the situation in above-mentioned scope, for example, as shown in Figure 4, when also longer, at the moment T4 of clock signal decline, because data mask portion 124 and storage data independence than the cycle t1+t2 of clock signal, the signal of output L level is so microcomputer 110 is taken into the signal of this L level.Therefore, memory contents is not exported to the outside from IC-card.(and, in fact, owing to the instruction code that microcomputer 110 is carried out can not correctly be read from memory array cell 121 too, so the action of microcomputer 110 self can not correctly be carried out.)
Here, general, with the digital circuit of clock signal synchronization action, even also correct operation of the frequency that reduces clock signal.Therefore, usually, the third party think illegally to resolve IC-card with the situation that reads memory contents under, carry out easily for the circuit operation that slows down makes parsing, adopt low-frequency clock signal mostly.Yet, as mentioned above, under the clock signal frequency of regulation, just can read memory contents by making 110 of microcomputers, can easily prevent illegally obtaining of data etc.
And, the data mask signal be the H level during, be not defined in 1 time, also can take place for several times.In this case, because can correct operation under multiple clock signal frequency, for example, when IC-card switches clock signal frequency by the pattern of high speed motion pattern and low consumpting power, no matter with which pattern, can correct operation, and under other frequency, can not carry out suitable action.
In addition, as mentioned above, be not limited to moment of departing from from data mask portion 124 output storage data at edge from clock signal, even make either party moment of beginning or stop from the output of data mask portion 124 (screened circuit) storage data with the edge of clock signal synchronous in, the time that is taken into of the storage data of microcomputer 110 becomes the moment that begins only to depart from the stipulated time from the edge of clock signal, or make the output of storage data begin and stop, either party moment also becomes the moment of departing from from the edge of clock signal in being taken into, and also can obtain same effect.
In addition, even above-mentioned data mask signal be the H level during in, when having the edge of clock signal (reading control signal), store data from the output of data mask portion, and when when not existing, not exporting the storage data, promptly, even the output according to the relativeness control store data between data mask signal and the clock signal has or not, equally also can only under clock signal frequency, will store data and be taken in the microcomputer 110 for regulation.
In addition, the method for present embodiment is not defined in independent use, for example and with the method for password contrast or the various known method such as method of encryption storage data itself makes up, and can further improve invisible.
(the 2nd embodiment)
Below, the IC-card of embodiment 2 is described.And, in the following embodiments,, pay identical symbol, and omit explanation for the inscape that has with above-mentioned embodiment 1 identical function such as grade.
The IC-card of embodiment 2 as shown in Figure 5, is compared with the IC-card of above-mentioned embodiment 1, and different is, replaces data mask portion 124, but possesses data mask portion 224, also possesses random data simultaneously and produces circuit 231.
Above-mentioned random data produces circuit 231, output data-signal at random in official hour.
In addition, data mask portion 224 specifically, as shown in Figure 6, constitutes the selector switch 224a that possesses the number corresponding with the bit number of data.
According to above-mentioned formation, for example, as shown in Figure 7, from data mask portion 224, at the data mask signal is under the situation of H level, similarly exports the data-signal of reading from memory array cell 121 with above-mentioned embodiment 1, on the other hand, at the data mask signal is under the situation of L level, and output produces the random data signals of circuit 231 outputs from random data.
That is, under the appropriate situation of clock signal frequency, the random data signals that produces circuit 231 outputs with random data is irrelevant, microcomputer 110, in the moment of data mask portion 224 outputs, be taken into this data-signal at the signal of reading from memory array cell 121, appropriate action.On the other hand, for example, under the low situation of the frequency of clock signal, as shown in Figure 8, because microcomputer 110 is taken into from the random data signals of data mask portion 224 outputs, so can not appropriately move.
In addition, for example, even IC-card is decomposed the third party, probe is contacted with LSI chip or wiring pattern, under the situation of the signal of parsing IC-card inside, because the difficult difference of distinguishing storage data and random data is difficult so in fact unlawfully obtain the memory contents of memory array cell 121.Have again, even the clock signal of appropriate frequency has been adopted in supposition, under the situation that microcomputer 110 normally moves, only in the inner data to outside output (according to program and the data of handling like this) of using not of IC-card, not only difficult and random data difference, and unlawfully read and remain difficulty.
Here, as above-mentioned random data, might not be the high data of proper randomness, so long as the in disorder dummy data different with the storage data gets final product.Therefore, for example, can use the data of bit positions such as replacing storage data or address, perhaps the data after implementing the regulation conversion on these data.
In addition, though the cycle that random data changes limit especially, if with the data mask signal become the H level during corresponding, with the identification of storing data will be more difficult.
(embodiment 3)
The IC-card of embodiment 3, as shown in Figure 9, compare with the IC-card of above-mentioned embodiment 2, different is, also possesses temperature sensing circuit 331, replace data mask simultaneously and produce circuit 125, only possess and detecting by said temperature testing circuit 331 under the situation of the temperature in the specialized range, with the same sequential of above-mentioned embodiment 2 in to make the data mask signal be the data mask signal generating circuit 325 of H level.
By above-mentioned temperature sensing circuit 331 and data mask signal generating circuit 325 are set, only in the temperature range of regulation and provide under the situation of clock signal of assigned frequency, microcomputer 110 normally moves, in other cases, because the storage data are not read out, can further improve the invisible of storage data easily.
Have again, even as mentioned above IC-card is decomposed, resolved, under the unfavorable situation of temperature range, because the storage data are not upward transmission of the signal wire (data bus) between data mask portion 124 and microcomputer 110 fully, so also can more easily prevent to contact and resolved operation with probe.
Here, though from memory array cell 121 to the data mask portion 124, the storage data are transmitted, but because from memory array cell 121 to output buffer 123, usually the signal that is transmitted is faint or the output impedance height, is difficult so come detection signal by contact probe.In addition, the circuit from memory array cell 121 to data mask portion 124 forms owing to usually closely connect ground, is difficult so want to be familiar with by parser circuitry the route of data-signal, and physically contact probe also is not easy in addition.So, as mentioned above, between data mask portion 124 and the microcomputer 110, promptly be familiar with data bus with comparalive ease from wiring pattern etc., also have at length of arrangement wire long and with the exposed to contact signal routes of probe on, by only exporting random data signals (not exporting the storage data), in fact can quite improve invisible.
And, the condition that data mask signal generating circuit 325 is used as the data mask signal of output H level, having more than is the temperature that merely detects specialized range, for example also can will detect the variation of high temperature, low temperature, high temperature as condition.
In addition, replace, also can in microcomputer 110, stop being taken into of the storage data exported from data mask portion 124 from data mask portion 124 output storage data.
(embodiment 4)
The temperature sensing circuit 331 that replaces above-mentioned embodiment 3 as shown in figure 10, is provided with optical detection circuit 431, and according to detected light intensity, making the data mask signal is the H level, thereby equally also can easily improve the invisible of storage data.
In addition, about light intensity, the also variation of the light intensity of pattern according to the rules is from data mask portion 124 outputting data signals.Have again, also can be used in combination above-mentioned temperature detection and light and detect.
(embodiment 5)
The IC-card of embodiment 5, as shown in figure 11, compare with the IC-card of above-mentioned embodiment 1, different is, replace data mask signal generating circuit 125 with data mask signal generating circuit 525, also possess address arithmetic circuit 531 simultaneously, and microcomputer 110 possess address arithmetic circuit 512 and latch signal generation circuit 513.
Above-mentioned address arithmetic circuit 531, according to (also the comprising the situation of not carrying out whatever) such as computings of stipulating from the address signal of microcomputer 110 output, and with this operation result to 525 outputs of data mask signal generating circuit.Specifically, for example, the value of the value of the LSB of OPADD or a plurality of bits of regulation also has the value etc. of these having been implemented the regulation conversion.And, also can be according to carrying out computing from the row address or the column address of access-control scheme 126 outputs.
Data mask signal generating circuit 525 (sequential control circuit), though be identical with embodiment 1 aspect the read output signal output timing of control data shielding part 124 (screened circuit), but beginning up to the data mask signal from the negative edge of clock signal is the time t1 of H level, and the data mask signal is at least one side among the time t2 of H level, is to be set according to the operation result from above-mentioned address arithmetic circuit 531 outputs.Promptly, be set to specified length in advance with respect to above-mentioned time t1, t2 in the IC-card of above-mentioned embodiment 1, in the IC-card of present embodiment, the data mask signal becomes the moment of H level, changes according to the address of this access in each access of storer.
In addition, the address arithmetic circuit 512 of microcomputer 110 constitutes and carries out the computing identical with above-mentioned address arithmetic circuit 531, and latch signal produces circuit 513 (sequential control circuit) and constitutes, according to operation result, to register 111 output latch signals from the output of address arithmetic circuit.Above-mentioned latch signal produces circuit 513, more detailed saying, according to the operation result of address computing circuit 512, during time t2 in, promptly in the data mask signal is the time of H level, make the level of above-mentioned latch signal change (generation pulse edge).
In the IC-card of above-mentioned formation, latch signal in data mask signal and the microcomputer 110, because it is corresponding all the time on sequential, though so frequency-independent of microcomputer 110 and clock signal, regular event, but owing to, in each access of storer, change, become difficult so can make by contacting with signal wire (data bus) between data mask portion 124 and the microcomputer 110 with probe to resolve etc. from the sequential of the correct storage data of data mask portion 124 output.
(embodiment 6)
The IC-card of embodiment 6, as shown in figure 12, being in the regulation zone in memory array cell 121, is time (time t1, t2) the corresponding shielding time series data of H level by storage with the data mask signal, thereby can setting-up time t1, t2 or time that is taken into of microcomputer 110.
Specifically, compare with the IC-card of embodiment 5, different is, replace address arithmetic circuit 531 and data mask signal generating circuit 525, but possesses data mask signal generating circuit 625, microcomputer 110 replaces address arithmetic circuit 512 and latch signal produces circuit 513, produces circuit 613 and possess latch signal.
In above-mentioned data mask signal generating circuit 625 (sequential control circuit), Input Address signal and the data-signal of exporting from output buffer 123, in reference-to storage array element 121 regulation the address area time, according to shielding time series data from output buffer 123 outputs, set above-mentioned time t1, t2, control data shielding part 124 (screened circuit).
In addition, latch signal at microcomputer 110 produces in the circuit 613 (sequential control circuit), Input Address signal and the data-signal of importing from data mask portion 124, corresponding to setting-up time t1, t2 in above-mentioned data mask signal generating circuit 625, set the edge moment to the latch signal of register 111 outputs.
According to above-mentioned formation, owing to can set flexibly, become difficult so certainly further make by probe being contacted with data bus resolve etc. from the sequential of the correct storage data of data mask portion 124 output.
And, also can store a plurality of above-mentioned shielding time series datas, thereby optionally use.
(embodiment 7)
The IC-card of embodiment 7, as shown in figure 13, compare with the IC-card of embodiment 5, replace address arithmetic circuit 512,531, possesses sequential control portion 714 (sequential control circuit), latch signal produces circuit 513 and data mask signal generating circuit 525, and according to the output of above-mentioned sequential control portion 714, the control data shielded signal becomes the time of H level or the register 111 of microcomputer 110 was taken into from the moment of the data-signal of data mask portion 124 (screened circuit) output.
Above-mentioned sequential control portion 714 specifically, for example is read out or microcomputer 110 when beginning action and waiting in the storage data, can export random number or the output value by the program decision, also can export the value to each IC-card setting.
Thus, certainly same with above-mentioned embodiment 6,7, can further make by probe being contacted with data bus resolve to wait and become difficult, can improve and store the invisible of data.
And, in above-mentioned example, example as the memory storage that possesses storer and microcomputer, though for example understand IC-card, but be not limited to this, can be memory storage of so-called label cassette etc., can be by splicing ear being contacted carry out the contact that is connected with host apparatus in addition, also can be to utilize electromagnetic wave to wait carry out contactless.
In addition, the formation of the respective embodiments described above or variation can be carried out various combinations in the logic allowed band.Specifically, for example, as enforcement mode 3～7, can replace the output random data signals, as implement to export the mode 1 signal of L (or H) level, and have again, embodiment 3,4 such temperature sensing circuit 331 or optical detection circuit 431 also can be set in the formation of embodiment 5～7.
(invention effect)
As mentioned above, according to the present invention since by only in clock signal during for the frequency of regulation, To be taken in the microcomputer from the data that memory is read, or make above-mentioned be taken into constantly variable, from And can make storage data that the third party carries out illegally read or resolve difficult, so can hold Change places and improve the invisible of the storage devices such as IC-card, and, by the clock letter of assigned frequency is provided Number etc., as required, also can easily read internal data.
Claims (10)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002348774A JP2004185134A (en) | 2002-11-29 | 2002-11-29 | Storage device |
| JP2002348774 | 2002-11-29 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1504954A CN1504954A (en) | 2004-06-16 |
| CN1311397C true CN1311397C (en) | 2007-04-18 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2003101188096A Expired - Fee Related CN1311397C (en) | 2002-11-29 | 2003-11-28 | Storage device |
Country Status (3)
| Country | Link |
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| US (1) | US7171533B2 (en) |
| JP (1) | JP2004185134A (en) |
| CN (1) | CN1311397C (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4586755B2 (en) * | 2006-03-22 | 2010-11-24 | ヤマハ株式会社 | General-purpose logic circuit |
| US20070283104A1 (en) * | 2006-05-31 | 2007-12-06 | International Business Machines Corporation | Concurrent Hardware Selftest for Central Storage |
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| US6115317A (en) * | 1998-05-14 | 2000-09-05 | Samsung Electronics Co., Ltd. | Semiconductor memory device for masking data by controlling column select line signals |
| US6208582B1 (en) * | 1998-10-08 | 2001-03-27 | Fujitsu Limited | Memory device including a double-rate input/output circuit |
| US6311299B1 (en) * | 1999-03-01 | 2001-10-30 | Micron Technology, Inc. | Data compression circuit and method for testing embedded memory devices |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3221935B2 (en) | 1992-10-27 | 2001-10-22 | 富士写真フイルム株式会社 | Memory protector for IC memory card |
| KR100225790B1 (en) * | 1994-03-18 | 1999-10-15 | 아끼구사 나오유끼 | Optical deflector optical scanner informational readout system and projector |
| JP3272213B2 (en) * | 1995-10-02 | 2002-04-08 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Authentication method for IC card and information processing device |
| JP3756231B2 (en) * | 1995-12-19 | 2006-03-15 | 株式会社ルネサステクノロジ | Synchronous semiconductor memory device |
| US5875142A (en) * | 1997-06-17 | 1999-02-23 | Micron Technology, Inc. | Integrated circuit with temperature detector |
| JP3727778B2 (en) * | 1998-05-07 | 2005-12-14 | 株式会社東芝 | Data high-speed transfer synchronization system and data high-speed transfer synchronization method |
| CN1302433A (en) * | 1999-02-26 | 2001-07-04 | 松下电器产业株式会社 | Optical information recording and reproducing device |
| KR100308216B1 (en) * | 1999-03-15 | 2001-09-26 | 윤종용 | Unauthorized unsealing detection apparatus for sealed electronic device |
| JP2001319500A (en) * | 2000-05-10 | 2001-11-16 | Mitsubishi Electric Corp | Semiconductor integrated circuit device |
| JP2002216483A (en) * | 2001-01-18 | 2002-08-02 | Toshiba Corp | Semiconductor storage device |
| JP2002298580A (en) * | 2001-03-28 | 2002-10-11 | Mitsubishi Electric Corp | Semiconductor storage device |
| US20030233562A1 (en) * | 2002-06-12 | 2003-12-18 | Sachin Chheda | Data-protection circuit and method |
-
2002
- 2002-11-29 JP JP2002348774A patent/JP2004185134A/en active Pending
-
2003
- 2003-11-26 US US10/721,097 patent/US7171533B2/en not_active Expired - Fee Related
- 2003-11-28 CN CNB2003101188096A patent/CN1311397C/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6115317A (en) * | 1998-05-14 | 2000-09-05 | Samsung Electronics Co., Ltd. | Semiconductor memory device for masking data by controlling column select line signals |
| US6208582B1 (en) * | 1998-10-08 | 2001-03-27 | Fujitsu Limited | Memory device including a double-rate input/output circuit |
| US6311299B1 (en) * | 1999-03-01 | 2001-10-30 | Micron Technology, Inc. | Data compression circuit and method for testing embedded memory devices |
Also Published As
| Publication number | Publication date |
|---|---|
| US20040107351A1 (en) | 2004-06-03 |
| CN1504954A (en) | 2004-06-16 |
| JP2004185134A (en) | 2004-07-02 |
| US7171533B2 (en) | 2007-01-30 |
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