CN1310471A - Method for forming double-layer low-dielectric barrier-layer using for interconnection and its forming apparatus - Google Patents
Method for forming double-layer low-dielectric barrier-layer using for interconnection and its forming apparatus Download PDFInfo
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Abstract
公开一种在铜导体上形成双层低介电阻挡层的方法与形成的装置。首先提供带有形成在绝缘体层内的铜导体的经预处理的衬底。然后沉积一层含磷或含硼薄膜。在第一退火处理中此结构在还原气氛中加热,延续时间足以使含磷或含硼合金扩散到铜导体顶面的2－4个原子层内。然后在上面沉积一层低介电薄膜。在第二热处理中把此结构在还原气氛中加热至至少1小时。还公开一种在半导体结构内的导电体,其双层阻挡层表现出对铜导体优良的阻挡与附着性能。
Disclosed are a method and a device for forming a double-layer low-dielectric barrier layer on a copper conductor. A preprocessed substrate is first provided with copper conductors formed in an insulator layer. A thin film containing phosphorous or boron is then deposited. The structure is heated in a reducing atmosphere in a first annealing treatment for a time sufficient to diffuse the phosphorus- or boron-containing alloy within 2-4 atomic layers of the top surface of the copper conductor. Then deposit a layer of low dielectric film on it. The structure is heated in a reducing atmosphere for at least 1 hour in a second heat treatment. Also disclosed is a conductor within a semiconductor structure, the double barrier layer exhibiting excellent barrier and adhesion properties to copper conductors.
Description
Relate generally to of the present invention forms the method for a low-dielectric barrier-layer using that is used to interconnect and the device of formation, relate to the method that forms a double-layer low-dielectric barrier-layer using on the copper-connection in semiconductor structure in more detail, the layer of deposition is subsequently stopped diffusion and improves adhesion property being used for, and the device that forms of method thus.
Making is used for providing the interconnection technique of through hole, circuit and other groove of semiconductor chip structure, flat-panel monitor and package application to develop for many years.For example, when the interconnection technique of exploitation integrated very on a large scale (VLSI) structure, adopt aluminium as the semiconductor regions or the contact of device and the base metal source of interconnection that are positioned on the single substrate.It is because its low price, good ohmic contact and high conductance that aluminium becomes selected material.But the fine aluminium thin film conductor has for example low melting point metal of undesirable performance, and this has limited it and has been used for K cryogenic treatment, thereby silicon may be diffused into the inefficacy that causes in the aluminium contacting with node during annealing, with bad electromigration resistance.When causing that ion drifts about only in the thermal diffusion at random of electric field coincidence in metal solid, the electromigration phenomenon takes place.Thereby, developed many aluminium alloys that have above the advantage of fine aluminium.For example, U.S. Patent number US 4566177 weight content that discloses silicon, copper, nickel, chromium and a manganese up to 3% aluminium alloy conductive layer in order to improve electromigration resistance.U.S. Patent number US 3631304 openly contains the aluminium alloy of aluminium oxide, is used to improve electromigration resistance equally.
Recently VLSI and ULSI technology are because high current densities and the quicker operation speed of these matching requirements proposes stricter requirement to line.This causes that higher current density is arranged in more and more thinner lead.As a result, require the aluminium alloy wire of lead or larger cross-section, or the lead of making by the different conductor material with high electrical conductivity.In view of the high conductivity that meets the requirements of copper, the obvious selection of industrial quarters is the exploitation latter, promptly uses copper.
Forming VLSI and ULSI interconnection structure for example when through hole and circuit, copper is deposited in circuit, through hole or other groove with interconnection is being positioned at semiconductor regions or device on the same substrate.Known copper is because it is having problem with the fast reaction speed of silicon aspect the semiconductor device connection.Any copper atom or ions diffusion can cause device fault in silicon substrate.Copper is diffused in the inter-metal dielectric and also can causes device fault by producing short circuit and open circuit in addition.Therefore, the coat of having covered for the interconnection of copper to prevent copper and the mutual diffusion of material around is absolutely necessary to the reliability of assurance copper-connection.These layers are commonly referred to " laying ", " barrier layer " and " cover layer ", and also must show has good tack between copper-connection and various dielectric layer and contact through hole.
When being used for the wafer network interconnection metalized of copper wire rear end (BEOL); the standard sequence program is used in the metallization of through hole and groove: the thick dielectric deposition; through hole and groove opening; deposition of thin lining on the wall of through hole and groove is with copper filling vias and groove, the copper top surface of flattening; at last; cover upper surface with protective layer, be used for when depositing the upper strata dielectric, preventing that copper is diffused into the upper strata dielectric, and the reaction with copper is minimized.Last cap rock also plays the active-ion-etch trapping layer to next upper strata dielectric.Interconnection wiring to each layer repeats this metalized.
In common process, the dielectric substance that is most commonly used to cover each copper BEOL layer is silicon nitride (SiN).It is manufactured in copper reliably is inter-metal dielectric and silicon dioxide (SiO
2) be among the ULSI of interconnect dielectric.Yet in order to continue to improve the interconnection performance, the direction of ULSI industry forward low-k (low k) inter-metal dielectric advances.SiN has 7 to 8 high dielectric constant and significantly increases effective layer capacitance.The application of SiN in BEOL interconnection in the future will be reduced to minimum or be substituted to satisfy low k requirement.
Other people has proposed to solve the way of the low k BEOL difficulty of copper.For example, a kind of solution is to use an autoregistration metal cap rock to cover the upper surface with the protection copper wire, big adhesive force is provided and and then plays the effect of copper diffusion barrier layer.But for the copper barrier layer performance of satisfy wishing, the thickness of metal cap rock must be at least 1000-2000 , and when the spacing between circuit during less than 3000 , this thickness may cause short circuit between lead.Only use crown cap also to bring and handle the dielectric difficulty of one deck down.During active-ion-etch (RIE) top layer dielectric, do not have etching to stop function and following metal and dielectric to be easy to etched and be subjected to the pollution of this RIE processing.
Also have other people to propose to form solution up to the low K dielectrics film of 800 thickness by using by the material that for example comprises Si, C, H or Si, C, O, H.But, the copper diffusion barrier layer that these low k films (having the dielectric constant less than 4) do not play a part usually.During making the BEOL interconnection to the oxidation of copper they neither good barrier layer, and can weaken adhesive force greatly and form the space owing to the formation of CuO and cause catastrophic fault.Compare therewith, SiN passes through SiH usually
4With NH
3Plasma enhanced chemical evaporation deposition method (PECVD) deposition, the method itself does not cause that the oxidation of copper and known SiN are good oxygen barrier layers.
Therefore, an object of the present invention is to provide a method that on copper conductor, forms the barrier layer of the defective do not have conventional copper barrier layer and shortcoming.
Another object of the present invention provides one and reduces SiN lid thickness and improve its method to the tack of copper.
A further object of the present invention provides one and form a method of improving the low-dielectric barrier-layer using of diffusion barrier and adhesion property on copper conductor.
Another purpose of the present invention provides a method that forms a double-layer low-dielectric barrier-layer using on copper conductor, wherein sequentially deposits the alloy firm and the siliceous dielectric materials of one deck of the phosphorous or boracic of one deck on copper conductor.
Another purpose of the present invention provides one and connect an annealing in process to form the method for a double-layer low-dielectric barrier-layer using by is used to adhere to the independent stratum with diffusion barrier in 2 of depositions on the copper conductor after.
Form the method for double-layer low-dielectric barrier-layer using on the copper conductor that also has a purpose to provide a through hole that is used for the copper wire back-end processing or interconnection of the present invention.
Of the present invention also have a purpose to provide a method that forms a double-layer low-dielectric barrier-layer using on copper conductor, connects an annealing in process after one of them phosphorous or boron-containing alloy film is handled and arrive in the atomic layer of 2-4 at least of copper conductor to cause alloy diffusion.
Of the present invention also have a purpose to provide electric conductor in the semiconductor structure, and it comprises a metallic conductor, and the alloy film of the phosphorous or boracic of one deck is with the low K dielectrics material membrane of one deck at the top.
Of the present invention have a purpose to provide the interior electric conductor of a semiconductor structure again, wherein, deposit the low K dielectrics material of a layer thickness between 100 and 500 above the alloy firm at this then at first at the phosphorous or boron-containing alloy film of deposition one layer thickness between 50 and 200 on the metallic conductor.
According to the present invention, a kind of method of a double-layer low-dielectric barrier-layer using and structure of formation of forming on copper conductor disclosed.
In a most preferred embodiment, a kind of can be by following operating procedure enforcement in the method that forms a double-layer low-dielectric barrier-layer using on the copper conductor: provide one have the copper conductor that in an insulator layer, forms through pretreated substrate; Phosphorous or the boron-containing alloy film of deposition one deck on copper conductor; In first heat treatment, be at least and be long enough to 300 ℃ of perdurabgilities make phosphorous or boron-containing alloy is diffused in the atomic layer of 2-4 at least of copper conductor upper surface in reducing atmosphere, be heated to temperature through pretreated substrate; At phosphorous or deposition one deck thin dielectric film above the boron-containing alloy film; In reducing atmosphere, be heated to temperature with handle in second heat treatment through pretreated substrate and be at least 300 ℃ of continuities at least 1 hour.When regulation during reducing atmosphere, mean and comprise vacuum, H
2, forming gas and inert gas atmosphere.
Perhaps, can sequentially deposit 2 layers (metal and dielectrics), after connect once in reducing atmosphere 2 hours annealing in process step of continuity under 400 ℃ of temperature.
Form in the method for a double-layer low-dielectric barrier-layer using on copper conductor, first heat treatment can continue at least 2 hours under at least 325 ℃ of temperature.Second heat treatment can continue at least 2 hours under at least 350 ℃ of temperature.The reducing atmosphere that uses in first and second heat treatment can be hydrogen nitrogen forming gas (H
2+ N
2) or vacuum.Phosphorous or boron-containing alloy depositing of thin film is handled and can be undertaken by the electroless plating membrane technology.Perhaps, also can then deposit thin dielectric film by the first phosphorous or boron-containing alloy film metal level of deposition ground floor, double-deck then in nitrogen or comprise forming gas, H
2, the last heat treatment that continues 2 hours in the reducing atmosphere of nitrogen or vacuum under 400 ℃ is merged into 2 annealing in process once.Thin dielectric film can be by plasma enhanced chemical hydatogenesis deposition techniques phosphorous or above the boron-containing alloy film.The method also can be included in before the phosphorous or boron-containing alloy film of deposition the step at deposition one deck palladium forming core layer on pretreated substrate.Phosphorous or boron-containing alloy film can be Me-X-P or Me-X-B, and wherein Me is the fundamental component of alloy firm and X is the alloy conditioning agent.
The method that forms a double-layer low-dielectric barrier-layer using on copper conductor can comprise that also the dilute sulfuric acid palladium solution in using sulfated deposits one deck palladium forming core layer by selecting ion-exchange process on copper conductor.Phosphorous or boron-containing alloy film also can comprise the Me of weight content between about 86% and about 90%, and weight content is P or the B between about 6% and about 12% at X between about 2% and about 4% and weight content.The dielectric film of deposition can have and is not more than 5 dielectric constant.The method also can comprise the phosphorous or boron-containing alloy film of deposition to thickness between about 50 and about 300 , be preferably in the step between about 100 and about 200 .The method also can be included in the hypophosphites solution that comprises cobaltous sulfate, ammonium tungstate, natrium citricum and boric acid, in temperature be between about 70 ℃ and about 80 ℃, the pH value under the condition between about 8 and about 9, the step of or boron-containing alloy film phosphorous by the electroless deposition process deposition.The method can be included in also that temperature is between about 325 ℃ and about 400 ℃, cycle perdurabgility is to carry out the first heat treated step under the condition between about 0.5 hour and about 2 hours.The method also can comprise the step of the thin dielectric film of a kind of material that deposition is selected from the group that comprises a kind of material that comprises silicon, carbon, oxygen, nitrogen and/or hydrogen, a kind of material that comprises silicon, carbon, hydrogen, nitrogen and diamond-like carbon.The method can comprise that also deposition thin dielectric film to thickness is between about 100 and about 500 , is preferably in the step between about 250 and about 350 .The method can be included in also that temperature is between about 350 ℃ and about 400 ℃, carry out the second heat treated step perdurabgility under the condition between about 1 hour and about 5 hours.Phosphorous or boron-containing alloy film can be Me-X-P or Me-X-B, and wherein Me is Co or Ni, and X is W or Sn.
The invention still further relates to an electric conductor in semiconductor structure, it comprises a metallic conductor that is positioned at insulating barrier, phosphorous or the boron-containing alloy film of one deck on metallic conductor, or dielectric substance film boron-containing alloy film above phosphorous at this with one deck.
In the electric conductor in a semiconductor structure, phosphorous or boron-containing alloy is present in the metallic conductor top surface at least in 2-4 atomic layer.This metallic conductor can comprise copper.Phosphorous or boron-containing alloy can be binary or the ternary alloy three-partalloy of Me-P, Me-B, Me-X-P or Me-X-B, and wherein Me is Co or Ni, and X is Si, W or Sn.Phosphorous or boron-containing alloy can be deposited into thickness between about 10 and about 1000 , is preferably between about 50 and about 200 .Phosphorous or boron-containing alloy can deposit by electroless plating techniques.The dielectric substance of deposition can be by selecting from the group that comprises a kind of material that comprises silicon, carbon, oxygen, nitrogen and hydrogen.Dielectric substance can be deposited into thickness between about 10 and about 5000 , is preferably between about 100 and about 500 .Semiconductor structure can form at the substrate of selecting from the group that comprises silicon, SiGe, silicon-on-insulator and GaAs.
These and other purpose of the present invention, feature and advantage, will be by to the investigation of this specification and accompanying drawing and clear and definite, in these accompanying drawings:
Fig. 1 is the amplification view of a double-layer low-dielectric barrier-layer using that has second dual-damascene structure that forms on end face that forms on the copper conductor with dual-damascene structure (damascene structure) of the present invention.
Fig. 2 is the amplification view of bilayer diffusion barrier/adhesion enhancement layer of forming on copper conductor of illustrating of an alternative embodiment of the invention.Fig. 3 is a curve chart that illustrates the secondary ion number of various elements in a multilayer barrier layer test structure as the dependence of the function of the degree of depth that enters structure of the present invention.In this example, the Co-W-P film is that 300 are thick, and low K dielectrics SiCOH film is at the top.
Fig. 4 is a curve chart that illustrates the secondary ion number of various elements in a multilayer barrier layer structure as the dependence of the function of the degree of depth that enters structure of the present invention.In this example, the CoSnP film is 300 , is that 500 are thick at the low K dielectrics SiCOH at top film, and wherein alloy firm was annealed 2 hours down at 350 ℃.
Fig. 5 is an explanation adhiesion test result for the form of the dependence of the structure of the silicon nitride film on the copper that wherein has one deck alloy firm and processing.
Fig. 6 is an explanation adhiesion test result for the form of filling out with the dependence of the structure on the double-deck barrier layer of SiCOH/ liner metal and annealing in process.
The present invention discloses a kind of by at first providing one to lead with the copper that is formed in the insulator layer The pretreated substrate of body, then at the phosphorous or boron-containing alloy film of copper conductor deposition one deck, Then pretreated substrate is heated to temperature in reducing atmosphere and is at least 300 ℃ when continuing Between in the superficial layer that is long enough to make alloy diffusion arrive copper conductor, then on alloy firm Deposition one deck thin dielectric film then is heated to temperature to pretreated substrate in reducing atmosphere Degree is at least and is at least 1 hour 300 ℃ of perdurabgilities, is used for the two of interconnection thereby form one The method of layer low-dielectric barrier-layer using.
The present invention also discloses an electric conductor in semiconductor structure, and it comprises that one is positioned at one Metallic conductor in the individual insulating barrier, the phosphorous or boron-containing alloy film of one deck on metallic conductor, With the dielectric substance film of one deck on phosphorous or boron-containing alloy film.
In method provided by the invention or device, phosphorous or boron-containing alloy film can be by Me-X-P Or Me-X-B represents that wherein Me is the fundamental component of alloy firm, and X to be alloy regulate Agent. Me can be Co or Ni, and X can be W or Sn. P and B represent phosphorus and boron. Phosphorous or boron-containing alloy also can comprise the Me of weight content between about 86% and about 90%, and is heavy Amount content at the X between about 2% and about 4% and weight content between about 6% and about 12% P or B. Alloy firm is deposited into thickness between about 50 and about 300 .
The heat treatment of using in the novel method of the present invention or annealing in process are for the bilayer of last formation The performance of dielectric barrier layer is important. For example, in first annealing in process, Semiconductor substrate Be heated to temperature and be at least 300 ℃ or preferably between about 350 ℃ and about 400 ℃, perdurabgility Be long enough to make phosphorous or boron-containing alloy is diffused into the superficial layer that enters at least copper conductor, namely enter Copper conductor is 2-4 atomic layer at least. Diffusion time can be between about 0.5 hour and about 2 hours. Second heat treatment of carrying out after the low-dielectric barrier-layer using in deposition can be 300 ℃ or in temperature Fortunately carry out between about 350 ℃ and about 400 ℃, cycle perdurabgility is little with about 5 at about 1 hour The time between. Perhaps, can continue 2 hours by heating is double-deck under 400 ℃ in reducing atmosphere, Annealing in process is merged in the twice annealing processing one time.
Dielectric layer can be by a kind of deposition of material that for example contains silicon, carbon, oxygen, nitrogen and/or hydrogen and Become. The thickness of thin dielectric film of deposition or is preferably between about 100 and about 500 Between about 100 and about 350 .
Novel method of the present invention is the electroless metallic film of one deck and the low k (dielectric constant) of one deck The dielectric covers sequential combination be deposited on through the polishing (for example by chemically mechanical polishing) copper/ On the dielectric end face to produce a double-deck barrier layer. This double-deck barrier layer provides the copper of hope to expand The barrier properties that looses, good to the copper tack, low dielectric constant keeps simultaneously on the next one The prevention performance of the dielectric active-ion-etch of layer (RIE). Double-deck barrier layer of the present invention Fringe benefit be to make the thickness of dielectric covers reduce to the thinnest. This reduces interconnection structure usually Effective dielectric constant also provides and shows that the electromigration of sening as an envoy to reduces to minimum conductor redundancy.
Double-deck barrier layer structure of the present invention can form by following process. Comprise copper with leveling The structure of wiring begins, and this copper wiring is imbedded in the dielectric, and a copper surface is exposed to dielectric Layer. In first step, carry out one to the copper surface have strong adhesive metal cap rock from Aim at and select to cover the bonding that is formed a metal to metal. The thickness of this metal cap rock is about Between 100 and 400 , thereby provide higher electric reliability and the electromigration resistance of improvement. This metal cap rock also is provided at closed space and has higher stability with the ability aspect of unusually separating out The copper surface. (this type of is processed, and part is more detailed in the back carrying out the annealing first time or heat treatment Carefully describe) afterwards, carry out depositing for the second time the processing of one deck spreadability dielectric covers. This Preferably the material of low-k forms the spreadability dielectric covers by having very, for example a kind of bag The material of siliceous, carbon, oxygen, nitrogen and/or hydrogen, or a kind of material that comprises silicon, carbon, hydrogen, nitrogen With diamond-like carbon. Perhaps, also can use SiN, but its thickness to liken and is single layer barrier to The thin thickness that Shi Tongchang requires many.
From by the Double layer lid of selective cobalt-based electroless treatment preparation (specifically but be not limited to Co-W-P, With SiN, SiCH or SiCOH film combinations) result that obtains, demonstrate fine Adhewsive action and the stability that obtains copper and control to the copper diffusion.
Forming the chemical step for diffusion barrier and the Double layer lid that adheres to of the present invention can be more detailed Be described below: the catalogue of novel method of the present invention be at copper after CMP processes Set up a double-level-metal/thin dielectric film on the surface. The first step that deposits on the copper surface In, selectively deposit a layer thickness by electroless plating between about 100 and about 400 Metallic film. This layer formed by the alloy with Me-X-P universal architecture, and wherein Me represents The fundamental component of alloy, X are a kind of alloy conditioning agents, and it has film to strengthen adheres to copper Very special performance and the diffusion barrier performance of effect, and P is illustrated in during the processing of formation film Certain a certain amount of phosphorus that deposits together. In a most preferred embodiment of the present invention, alloy firm Middle selection X is 3 to 5atomic% W, and P is 7 to 9atomic% the order of magnitude.
In the second step that the present invention processes, be in for example forming gas at the end face alloy firm Or in the reducing atmosphere of hydrogen with 350 ℃ temperature under, annealed copper structure at least 2 hours. This temperature Degree is processed and is made the composition of alloy closely merge and to be diffused in several atomic layers on top copper surface Thereby good in the copper adhewsive action to provide chemistry and metallurgical bonding to form. Perhaps, this annealing Step can be carried out between the dielectric depositional stage or afterwards.
In the third step that the present invention processes, on metallic film, cover and add one deck dielectric Film is to form double-decker. This is usually by a plasma enhanced chemical hydatogenesis (PECVD) finish dealing with. In the reason, dielectric substance was deposited on before and was deposited on herein On the Me-X-P layer on the copper, and thickness is usually between about 100 and about 500 . Send out Existing best thin dielectric film be those take silicon compound for example SiCOH, SiCH or SiN as The film on basis. Also can use for example low-k material of diamond-like carbon (DLC). Best dielectric substance is SiCOH, because it presents minimum dielectric constant.
In the 4th step that the present invention processes, in the reducing atmosphere of hydrogen, nitrogen or forming gas The continuity of annealing in process bilayer film is at least 2 hours under at least 300 ℃ of temperature. This is last Annealing in process is removed and to be impaired the organic of crown cap/dielectric interface of obtaining good adhesion property Impurity and presumable other volatile product.
The end-results that forms by each chemical step of the present invention is illustrated among Fig. 1.Fig. 1 illustrates the amplification view of the dual damascene interconnect structure 10 that contains in first most preferred embodiment of the present invention.Expression structure 10 has 2 dielectric interconnection layers 20 and 30 among the figure, and they comprise through hole 22,32 and groove 24,34.This structure is based upon on the Semiconductor substrate 12, and this substrate 12 has an active device 14 that forms in end face 16.First dielectric layer 18 is deposited on the substrate 12 and is patterned into the opening that has a through hole 32 and the opening of a groove 34.Be that through hole and groove lining are given in barrier layer 36 with liner then, fill metal 38, obtain on the groove 34 by the end face 40 of equating by cmp method.
In the next procedure that novel method of the present invention is handled, the electroless deposition cap rock 44 of a Co-W-P of deposition, a selective deposition is on groove 34.Cap rock 44 prevents that metal 38 is diffused into dielectric layer 50 and prevents and pollutes channel metal 34 owing to handling continuously.Metal level 44 with one for the dielectric covers 52 of choosing as after during the processing that connects or semiconductor device run duration basic device that trench metal is isolated with any interaction.Can be used for further improving the barrier properties of Co-W-P alloy-layer 40 for the cap rock 52 of choosing, or be used as for example trapping layer of active-ion-etch (RIE) of integrated enhancement layer.Second dielectric layer 50 as shown in Figure 1, is used for handling the dual damascene chamber that the back forms through hole 22 and groove 24 at RIE.In this case, dielectric covers 52 is as the RIE trapping layer.When using it, etching RIE trapping layer is to get through second layer groove 24 when handling beginning, and repetitive coatings laying 36 is until the interconnection layer that needing to obtain number simultaneously.
Fig. 2 is an amplification view that is used for the double-deck barrier layer of the present invention who forms at end face is carried out the copper test carrier of adhiesion test and diffusion impervious layer performance test.Can see on the end face of silicon substrate 12, at first depositing a barrier layer 36 that it comprises the thick metal liner bed course of about 800 of one deck.The thick copper conductor 38 of about 2000 of sputtering sedimentation one deck on laying 36 then.The metal cap rock 44 of electroless deposition can be Co-W-P layer or the Co-Sn-P layer of thickness between 300 and 500 .Depositing a layer thickness then in the above is the SiCOH low K dielectrics layer 52 of 500 .For strengthening the SIMS signal, deposition one deck diamond-like carbon 54 on SiCOH leads 52.
Fig. 3 and Fig. 4 are shown in the SIMS/ curve chart that obtains on the structure shown in Fig. 2.As shown in Fig. 3 and Fig. 4, when the thick SiCOH layer of the Co-W-P that only deposits the thick electroless deposition of one deck 300 or Co-Sn-P alloy-layer and one 500 , understand promote that copper diffuses through the annealing in process that the layer on surface of metal layer enters the SiCOH layer after, copper remain on fully electroless deposition alloy-layer 44 the back and following and not penetrated bed 44 enter dielectric layer 52.These results show that structure of the present invention stops the migration of copper and possible copper by the effect of oxygen molecule oxidation, and oxygen molecule can pass the SiCOH layer at least under the effect of heat energy.Therefore, structure shown in is an effective system as copper and oxygen atom thermophoresis inhibitor.
Fig. 5 is the form of an explanation about the adhesive strength data of (the various alloy firms of middle employing) between copper conductor and SiN dielectric layer.Its shows that copper is relevant strongly with the preliminary treatment on copper surface before operating in nitrogenize to the adhewsive action of silicon nitride.Optimum is obtained by the nitride that uses Co-Sn-P internal layer, Co-Sn-P internal layer and high-density plasma (HDP) deposition.The adhesive strength of pointing out in the table of Fig. 5 is with MPa * m
1/2Unit representation.
The Double layer lid that has the electroless deposition cap rock among Fig. 6 on the expression copper is with the result of the test of the dielectric adhewsive action of SiCOH.Tested and had Si-SiO
26 samples of/liner metal/copper (2000 ) structure.These samples do not have electropaining and cover Co-W-P, Co-P or Co-Sn-P.Then these samples of test in instrument wherein cover on the cap rock surface and add the thick SiCOH dielectric substance of 500 .Some sample is being heat-treated after the electroless deposition process with behind the deposition SiCOH layer, and other sample is only heat-treated behind deposition SiCOH layer.The result who represents among Fig. 6 shows that the Co-W-P layer produces best adhesive strength value.
The sample of representing among Fig. 6 also passes the hot copper migration of Co-W-P film with inspection by the sims analysis test.The SIMS data show that copper rests on the cap rock back and not to the dielectric migration, as the situation of prediction.
Show among Fig. 6 that test data shows by using the Co-W-P internal layer to strengthen the adhewsive action of SiCOH to copper.Found can by use one cover add dielectric after preliminary treatment in reducing atmosphere strengthen the adhewsive action of SiCOH dielectric layer significantly to copper.Can obtain optimum at least 2 hours by using the Co-W-P cap rock and behind deposition SiCOH, in forming gas, under 350 ℃, annealing.These samples show lost efficacy occur in correct interface be the SiCOH layer to the electroless deposition layer at the interface, and occur in the situation at the film place of adhering to through annealing below the copper layer with losing efficacy when system is unannealed behind additional SiCOH opposite.
So far, novel method of the present invention is proved absolutely in the accompanying drawing of above narration and Fig. 1 to Fig. 6 with the device of method formation thus.Shown that in the technical problem of using separately the low K dielectrics material for example to occur during SiCOH be because SiCOH does not have good adhewsive action and the SiCOH fact of oxygen permeable a little to copper.Thereby so these two factors unite the oxidation that causes copper with dielectric/copper at the interface delamination cause reliability generation problem.Therefore, novel method of the present invention uses a double-deck barrier layer, and for example Cu/Co-W-P/SiCOH and Cu/Co-Sn-P/SiCOH, the alloy cap layer that makes copper not pass electroless deposition move and remain on its back, even at 380 ℃ down after the annealing 2 hours.
Though the present invention is described in illustrative mode, should understands the term that uses in the narration and be intended to have descriptive nature but not finitude.
In addition, though the present invention is described by most preferred embodiment and alternate embodiment, should understand that those skilled in the art will easily be applied to other possible variation of the present invention to these technology.
The imbody of the present invention of application exclusive right or royalty right is determined in claims.
Claims (33)
1. method that forms double-layer low-dielectric barrier-layer using on copper conductor comprises step:
Provide one have the copper conductor that is formed in the insulator layer through pretreated substrate;
The film of the phosphorous or boron-containing alloy of deposition one deck on described copper conductor;
In first heat treatment, in reducing atmosphere, be heated to temperature through pretreated substrate and be diffused at least 3 atomic layers of described copper conductor end face at least 300 ℃ of perdurabgilities being long enough to make described phosphorous or boron-containing alloy described;
At described phosphorous or deposition one deck thin dielectric film above the boron-containing alloy film; With
In second heat treatment, in reducing atmosphere, be heated to temperature through pretreated substrate and be at least 300 ℃ of continuities at least 1 hour described.
2. according to the method that forms double-layer low-dielectric barrier-layer using on copper conductor of claim 1, wherein said first heat treatment was carried out 1 hour under at least 325 ℃ of temperature at least.
3. according to the method that forms double-layer low-dielectric barrier-layer using on copper conductor of claim 1, wherein said second heat treatment was carried out 2 hours under at least 350 ℃ of temperature at least.
4. according to the method that on copper conductor, forms double-layer low-dielectric barrier-layer using of claim 1, wherein sequentially depositing metal layers and dielectric layer and only dielectric layer deposition after, carried out once last heat treatment in 2 hours by in reducing atmosphere, heating at 400 ℃ times.
5. according to the method that forms double-layer low-dielectric barrier-layer using on copper conductor of claim 1, wherein said described deposition processes phosphorous or the boron-containing alloy film is undertaken by electroless plating techniques.
6. according to the method that on copper conductor, forms double-layer low-dielectric barrier-layer using of claim 1, wherein said thin dielectric film by plasma enhanced chemical hydatogenesis deposition techniques on described phosphorous or boron-containing alloy film.
7. according to the method that forms double-layer low-dielectric barrier-layer using on copper conductor of claim 1, wherein the described reducing atmosphere that uses in described first and second heat treatment is meant forming gas, nitrogen or hydrogen.
According to the method forming double-layer low-dielectric barrier-layer using on the copper conductor of claim 1 also be included in before the described step of the described phosphorous or boron-containing alloy film of deposition described on pretreated substrate the step of deposition one deck palladium forming core layer.
9. according to the method that forms double-layer low-dielectric barrier-layer using on copper conductor of claim 1, wherein said phosphorous or boron-containing alloy film is Me-X-P or Me-X-B, and wherein Me is the fundamental component of described alloy firm, and X is a kind of alloy conditioning agent.
10. the method that forms double-layer low-dielectric barrier-layer using on copper conductor according to claim 1 comprises that also the dilute sulfuric acid palladium solution that uses in the sulfuric acid deposits the step of a palladium forming core layer by selecting ion-exchange process on described copper conductor.
11. the method that on copper conductor, forms double-layer low-dielectric barrier-layer using according to claim 9, wherein said phosphorous or boron-containing alloy film also comprises the Me of content between about 86wt% and about 90wt%, the X of content between about 2wt% and about 4wt%, and P or the B of content between about 6wt% and about 12wt%.
12. according to the method that forms double-layer low-dielectric barrier-layer using on copper conductor of claim 1, the thin dielectric film of wherein said deposition has and is not more than 5 dielectric constant.
13. comprise also that according to the method forming double-layer low-dielectric barrier-layer using on the copper conductor of claim 1 described phosphorous or boron-containing alloy film to the thickness of deposition is the step between about 50 and about 300 .
14. comprise also that according to the method forming double-layer low-dielectric barrier-layer using on the copper conductor of claim 1 described phosphorous or boron-containing alloy film to the thickness of deposition is between about 50 and 300 , and be preferably the step between about 100 and about 200 .
15. the method that forms double-layer low-dielectric barrier-layer using on copper conductor according to claim 1 also is included in the hypophosphites solution that contains cobaltous sulfate, ammonium tungstate, natrium citricum and boric acid, under the temperature between about 70 ℃ and about 80 ℃, under the pH value between about 8 and about 9, deposit the step of described phosphorous or boron-containing alloy film by electroless deposition process.
16. also be included in according to the method forming double-layer low-dielectric barrier-layer using on the copper conductor of claim 1 and continue the time cycle under the temperature between about 350 ℃ and about 400 ℃ and between about 0.5 hour and about 2 hours, carry out the described first heat treated step.
17. the method for deposition double-layer low-dielectric barrier-layer using on copper conductor according to claim 1 also comprises the step that is deposited described thin dielectric film from the group that comprises Si, C, O, N and H by a kind of material of selecting.
18. the method forming double-layer low-dielectric barrier-layer using on the copper conductor according to claim 1 comprises that also the described thin dielectric film of deposition is to the step of thickness between about 100 and about 500 .
19. according to the method forming double-layer low-dielectric barrier-layer using on the copper conductor of claim 1 also comprise the described thin dielectric film of deposition to thickness between about 100 and about 500 , and be preferably in step between about 250 and about 350 .
20. also be included in according to the method forming double-layer low-dielectric barrier-layer using on the copper conductor of claim 1 and continue the time cycle under the temperature between about 350 ℃ and about 400 ℃ and between about 1 hour and about 5 hours, carry out the described second heat treated step.
21. according to the method that forms double-layer low-dielectric barrier-layer using on copper conductor of claim 9, wherein said Me is Co or Ni, described X is W or Sn.
22. the electric conductor in semiconductor structure comprises:
Be positioned at the metallic conductor of an insulator layer;
Phosphorous or the boron-containing alloy film of one deck on described metallic conductor;
One deck dielectric substance film on described phosphorous or boron-containing alloy film.
23. according to the electric conductor in semiconductor structure of claim 22, wherein said phosphorous or boron-containing alloy be present at least 2 atomic layers in the described metallic conductor end face below.
24. according to the electric conductor in semiconductor structure of claim 22, wherein said metallic conductor comprises copper.
25. according to the electric conductor in semiconductor structure of claim 22, wherein said phosphorous or boron-containing alloy is binary or the ternary alloy three-partalloy of Me-P, Me-B, Me-X-P, Me-X-B, wherein Me is Co or Ni, and X is Si, W or Sn.
26. the electric conductor in semiconductor structure according to claim 22, wherein said phosphorous or boron-containing alloy is binary or the ternary alloy three-partalloy of Me-P, Me-B, Me-X-P, Me-X-B, wherein Me is Co or Ni, and X is Si, W or Sn, is deposited into thickness between about 10 to 1000 .
27. the electric conductor in semiconductor structure according to claim 22, wherein said phosphorous or boron-containing alloy is binary or the ternary alloy three-partalloy of Me-P, Me-B, Me-X-P, Me-X-B, wherein Me is Co or Ni, and X is Si, W or Sn, is deposited into thickness and is preferably between about 50 and about 200 .
28. the electric conductor in semiconductor structure according to claim 22, wherein said phosphorous or boron-containing alloy is binary or the ternary alloy three-partalloy of Me-P, Me-B, Me-X-P, Me-X-B, wherein Me is Co or Ni, and X is Si, W or Sn, is deposited into thickness between about 10 and about 1000 by electroless plating techniques.
29. according to the electric conductor in semiconductor structure of claim 22, wherein said dielectric substance has and is not more than 5 dielectric constant.
30. according to the electric conductor in semiconductor structure of claim 22, wherein said dielectric substance comprises Si, C, O, N and H.
31. according to the electric conductor in semiconductor structure of claim 22, wherein said dielectric substance is selected from the group of the material of the material that comprises a kind of Si of comprising, C, O, N and H and a kind of Si of comprising, C, H and is deposited into thickness between about 10 and about 5000 .
32. according to the electric conductor in semiconductor structure of claim 22, wherein said dielectric substance comprises Si, C, O, N and H, is deposited into thickness between about 100 and about 500 .
33. according to the electric conductor in semiconductor structure of claim 22, wherein said semiconductor structure forms on a kind of substrate of selecting from the group that comprises silicon, SiGe, silicon-on-insulator and GaAs.
Applications Claiming Priority (2)
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|---|---|---|---|
| US51025900A | 2000-02-22 | 2000-02-22 | |
| US09/510,259 | 2000-02-22 |
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| CN1310471A true CN1310471A (en) | 2001-08-29 |
| CN1195322C CN1195322C (en) | 2005-03-30 |
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| CNB011046740A Expired - Fee Related CN1195322C (en) | 2000-02-22 | 2001-02-21 | Method for forming double-layer low-dielectric barrier-layer using for interconnection and its forming apparatus |
Country Status (5)
| Country | Link |
|---|---|
| JP (1) | JP4502528B2 (en) |
| KR (1) | KR100403063B1 (en) |
| CN (1) | CN1195322C (en) |
| SG (1) | SG102613A1 (en) |
| TW (1) | TW476134B (en) |
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- 2001-02-07 KR KR10-2001-0005950A patent/KR100403063B1/en not_active Expired - Fee Related
- 2001-02-08 SG SG200100695A patent/SG102613A1/en unknown
- 2001-02-09 JP JP2001033861A patent/JP4502528B2/en not_active Expired - Fee Related
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Also Published As
| Publication number | Publication date |
|---|---|
| CN1195322C (en) | 2005-03-30 |
| JP2001284453A (en) | 2001-10-12 |
| KR100403063B1 (en) | 2003-10-23 |
| TW476134B (en) | 2002-02-11 |
| JP4502528B2 (en) | 2010-07-14 |
| SG102613A1 (en) | 2004-03-26 |
| KR20010083163A (en) | 2001-08-31 |
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