CN1310299C - Hazard detection and elimination method based on circuit static time-delay property - Google Patents

Abstract

The present invention relates to methods for detecting and eliminating hazards in integrated circuits. Including: hazard detection and elimination methods for circuit static time delay characteristics. Eliminate or reduce hazards by appropriately adjusting the length of some paths in the circuit. When only one original input jumps, if two paths with different delays converge at a certain point in the circuit, and the number of gates (NAND gates, NOR gates, NOT gates) with inverting functions on these two paths If the parity is different, hazards may occur at this point; when multiple original inputs jump at the same time, as long as the path delays of the convergence are different, it is considered that hazards may occur at the convergence point. For the risk caused by a single original input transition, we selectively increase the delay of some gates to eliminate or reduce it. For the hazard caused by multiple original input transitions, we eliminate or reduce the hazard by adding a certain number of logic gates to make the transitions propagate synchronously in the circuit.

Description

Hazard detection and removing method based on the static delay character of circuit

Technical field

The present invention relates to the technical field of integrated circuit.Particularly relate to a kind of method of taking a risk in the integrated circuit that detects and eliminate.It is a kind of method by the analyzing and testing and the elimination of circuit timing characteristic are taken a risk.

Background technology

The analysis of the phenomenon of competition and risk in the circuit is an important subject in the integrated circuit low power dissipation design.Two input signals of gate circuit are called competition to the phenomenon of opposite logic level saltus step simultaneously.We are called risk to the spike that produces at circuit output end owing to compete.Fig. 1 has represented that the saltus step of door input causes the principle of taking a risk.With two input A of door g, saltus step (logical value changes to 1 from 0) and following saltus step (logical value changes to 0 from 1) take place to go up respectively in B simultaneously among Fig. 1.Because these two saltus steps arrive the delay difference of g, cause that two input logic values of g are 1 in a certain period, thereby the output Y of g kept logical value 1 for some time before being stabilized to logical value 0.Because logical value 1 is different in the logical value 0 of stable state with we Y of expection, we claim such pulse for taking a risk.The saltus step of Here it is door input causes the principle of taking a risk in the circuit.

The increase of chip power-consumption has not only increased the packaging cost of chip, has reduced the market competitiveness of chip, and excessive power consumption also can reduce chip reliability.The power consumption of cmos circuit mainly is made up of four parts: the function upset, take a risk short circuit current and leakage current.When switching transistor, cause occurring instantaneous short circuit between power supply and the ground wire, thereby cause the short circuit current power consumption, this part power consumption is very little usually.The leakage current power consumption still has small amount of current to flow through when being in the quiescent operation state owing to transistor to cause.In the technology less than .18 μ m, if transistor is working properly, this part electric current is very little, and the power consumption that it causes is usually than other several parts several magnitude low in energy consumption.The power of taking a risk to consume in cmos circuit is because (concrete principle is referring to Fig. 2 and hereinafter explanation) that the saltus step before the circuit arrival stable state causes.This part power consumption accounts for 20% to 40% of circuit total power consumption.In the circuit that has even reach more than 60%.So the risk phenomenon in the research circuit also finds and detects and eliminate the method for taking a risk, and for the power consumption that reduces circuit, guarantees the reliability of circuit, has crucial meaning.

Fig. 2 has represented in the circuit because the power consumption that risk causes.Transistor among the figure has the impedance of non-zero.Transistor single in this model can be replaced by several PMOS transistors or nmos pass transistor, thereby represents various CMOS door.Before the trailing edge of input pulse arrived, N conducting P disconnected.We suppose that the impedance of transistor when disconnecting is for infinitely great.So there is not electric current, the output voltage of not gate is zero.The capacitor C of output is not recharged.When the input trailing edge arrives (t=0), the P conducting, N disconnects, and charging current i (t) flows through the path of being made up of impedance R and capacitor C.Have this moment

$i\left(t\right)=\frac{V_{\mathrm{DD}}}{R}{e}^{-\frac{\mathrm{\τ}}{\mathrm{RC}}}$ Formula 1

The charging of capacitor C makes output voltage improve, and when t=τ, the input rising edge arrives.The electric energy that consumes in this process is:

$\underset{0}{\overset{\mathrm{\τ}}{\∫}}{V}_{\mathrm{DD}}i\left(t\right)=\mathrm{dt}={\mathrm{CV}}_{\mathrm{DD}}^2(1-e^{\frac{\mathrm{\τ}}{\mathrm{RC}}})$ Formula 2

Because resistance R, half of these energy lost in the mode of heat energy.Second half is stored in the capacitor C.Therefore, the energy of a door consumption and the number of transitions of its output are proportional, and saltus step is many more, and the energy of consumption is also just many more.If pulse duration τ is far longer than time constant RC, output end voltage rises to V _DDThe Shi Zaocheng maximum power dissipation.Be expressed from the next:

$E_{\max }={\mathrm{<figure-callout\; id="2"\; label="CV\; DD"\; filenames="C0312512700133.png,C0312512700153.png"\; state="\{\{state\}\}">CV</figure-callout>}}_{\mathrm{DD}}^{},\mathrm{\&tau;}>>\mathrm{RC}$ Formula 3

The input rising edge arrives during t=τ, and at this moment P is disconnected N and is switched on capacitor discharge.Because the impedance R of N, the energy that is stored in the electric capacity scatters and disappears with the form of heat again.

Because the delay of door has filtration to narrower pulse, if i.e. Men delay spike can not occur at the output of door so greater than the width of pulse, so, adopt which type of gate delay model can influence estimation to the risk number in the circuit.Relatively commonly used have three kinds of gate delay models: (1) 0 model: suppose that each nothing postpones; (2) unit delay model: the delay of supposing each is 1; (3) fan-out delay model: if the output of door A is the input of a B in the circuit, we just claim that door A is the fan-in of a B so, and claim that door B is the fan-out of an A.The fan-out delay model is to suppose that the delay of each equals the number of its fan-out.The method that we propose all is suitable for for above-mentioned three kinds of delay models.In following example, all adopt the fan-out delay model.

The object of the present invention is to provide a kind of method of taking a risk based on the detection and the elimination of circuit static timing characteristic.

Summary of the invention

Hazard detection in the integrated circuit and to eliminate the subject matter faced be how can be than judging the point that wherein may produce risk faster and how reducing or eliminate these risk points by increasing the less hardware expense for larger circuit.At this, we propose a kind of method of coming the risk point in the testing circuit by the analysis circuit delay character.This method fully takes into account that single original input generation saltus step in the circuit causes taking a risk and a plurality of original inputs saltus step takes place simultaneously cause the difference of taking a risk, and adopts different principles in Hazard detection, thereby can make judgement to the point of the risk in the circuit more accurately.This detection method speed is very fast.Also proposed to eliminate or reduce the method for the risk point in the circuit at this.It reaches the purpose of eliminating or reducing risk by the length of adjusting circuit middle part sub-path.This method can not increase the length of critical path in the circuit.

The method that the present invention proposes is made differentiation according to the delay character of circuit to producing the condition of taking a risk, and eliminates or reduce risk by the length of suitable adjustment circuit middle part sub-path.When having only an original input generation saltus step, if converge at the circuit point in two different paths of time-delay, and have the number parity difference of the door (NAND gate, NOR gate, not gate) of inverter functionality on this two paths, then may produce risk at this point; When a plurality of original inputs simultaneously saltus step take place,, the path delay difference that converges to produce risk at convergent point as long as then thinking.We eliminate the risk that causes for single original input saltus step by some delay of selectable increase or reduce.We eliminate the risk that causes for a plurality of original input saltus steps saltus step synchronous transmission in circuit by the gate that increases some or reduce risk.

The method of the risk that causes in the single original input saltus step of the detection of this proposition is as follows: at first from the original original output marking circuit element one by one that is input to, to be recorded in the mark of this element from the original time delay information that is input to this electric circuit element, the possibility of risk will take place at this element according to the marker for judgment of element then.The original output of circuit be labeled as 0.The mark of other element is generated by the mark of the precursor element of this element and the delay of this element in the circuit.Concrete labeling method is referring to 2 in the 4th part embodiment of this specification: the explanation of marking circuit element and accompanying drawing 3.After mark is finished, the mark of each in the testing circuit one by one, if there are two numbers in the mark of certain, the difference of their opposite in sign and absolute value greater than this delay we just think and may take a risk at this output.

The method of the risk that causes in a plurality of original input saltus steps of the detection of this proposition is as follows: for the circuit that has been labeled, in the testing circuit each door one by one, if there are two numbers in the mark of certain, the difference of their absolute value greater than this delay we have risk with regard to thinking at this output.

In the elimination of this proposition or the method that reduces the risk that single original input saltus step causes be: according to detect the opposite order of risk tag sequence and expand the mark of each, obtain to eliminating a risk point, should how many those delays with this spot correlation be increased, after expansion finishes, calculate the increment in each the extending marking, thereby select a suitable door, increase this delay.The flow chart of the method for giving is referring to Fig. 5.

The method of eliminating the risk that a plurality of original input saltus steps cause is as follows: (1) at first is input to original output according to following formula classification with circuit from original,

(2) then, begin door (having only the door of a fan-in to disregard) the treatment circuit step by step from original input, if a plurality of fan-ins of a door are on different levels, we keep that fan-in of progression maximum constant, and on the less fan-in of those progression, increase delay gate, make the progression of these fan-ins all equal the maximum progression that this door leaf is gone into.

Description of drawings

Fig. 1 is that the saltus step of an input produces risk figure at output;

Fig. 2 is a schematic diagram of taking a risk to cause power consumption;

Fig. 3 is the mark figure as a result of full adder;

Fig. 4 is the testing result figure of full adder;

Fig. 5 is a method flow diagram of eliminating the risk that original input saltus step causes;

Fig. 5 .1 is the signature of the original output 14 of expansion;

Fig. 5 .2 is the signature of extensible element 12;

Fig. 5 .3 is the signature of extensible element 11 and 9;

Fig. 5 .4 is the signature of extensible element 8;

Fig. 5 .5 is the signature of extensible element 3;

Fig. 5 .6 is the delay figure that increases door 9;

Fig. 6 is through the full adder figure after the Synchronous Processing.

The saltus step of Fig. 1 door input causes the principle of the risk of gate output terminal.The risk that the saltus step of door input produces.The front is described in detail, in this omission.

Fig. 2 takes a risk to cause the principle of power consumption.Here the saltus step of door input may be because the fan-out of an original input saltus step heavily converges and causes, also may since a plurality of original input saltus steps cause.Describe in detail in front, in this omission.

Fig. 3 is the full adder circuit through mark, and among Fig. 3, the function of full adder circuit is to bring 1 addition of position into.1 to 14 is electric circuit element (original input, gate, original output) numberings among the figure.The mark of each electric circuit element has been represented the time delay information that is input to this electric circuit element from original.For example, the mark of element 7 (with door) is 1 (5,3) 2 (5,3), and this is marked with two nodes forms, and these two nodes are respectively 1 (5,3), 2 (5,3).Wherein, node 1 (5,3) expression has two paths from original input 1 to element 7, skip signal is respectively 5 and 3 along the time delay that they propagate into element 7, and along length be 5 propagated during to element 7 the saltus step meeting by anti-phase (go up saltus step and be saltus step down by anti-phase, following saltus step by anti-phase be last saltus step).Similarly, node 2 (5,3) expression is information in the path delay of time from original input 2 to element 7.

Fig. 4 is the testing result of full adder circuit.Among Fig. 4, in the mark of the original output 14 of circuit, there is the saltus step at the original input of a node 3x (4,2) expression 3 places to cause a risk at original output 14 places.X expresses possibility to produce and takes a risk.The saltus step that the path that two thick lines are represented among the figure has shown 3 places is heavily converged through fan-out in communication process and is formed the path of taking a risk.

Fig. 5 is a flow chart of eliminating the method for taking a risk.

Fig. 5 .1-5.6 is the process of expansion full adder circuit.We increase a unit to eliminate the risk at original output 14 places with the delay of door 9 according to the circuit behind the extending marking.The method of concrete expansion process and modification circuit is referring to accompanying drawing.

Fig. 5 .1 expands in the mark of the original output that is marked at spike of original output 14 and adds increment.Have the node of risk to add in the original output 6 to become behind the increment 3x (4+0,2+1).

The mark of Fig. 5 .2 expander gate 12

In the mark of element 12, add increment.Element 12 unique fan-out elements are elements 14, and element 14 is original output, and time-delay is 0, and anti-phase coefficient is 1.Element 12 is identical with increment in element 14 marks.Mul can omit in 1 o'clock, did not mark on figure.

Fig. 5 .3 is the signature of extensible element 11 and 9;

Fig. 5 .4 is the signature of extensible element 8;

Fig. 5 .5 is the signature of extensible element 3;

Fig. 5 .6 is the delay figure that increases door 9;

Fig. 6 is the full adder circuit after the Synchronous Processing.

Among Fig. 6, be example, obtain according to our stage division: level (1)=level (2)=level (3)=0 with the full adder circuit, level (4)=2, level (5)=1, level (6)=3, level (7)=5, level (8)=7, level (9)=6, level (10)=8, level (11)=8, level (12)=9, level (13)=8, level (14)=9.According to above data, we are respectively at the fan-in element 5 of door 7, the fan-in element f of door 9 ₆, the fan-in element f of door 10 ₇Increase delay gate with the fan-in element 9 of door 12, make that the signal in the circuit is propagated synchronously.

More than explanation is the result to the element classification of full adder circuit.

Realization should comprise following step according to the method that the delay character of circuit carries out Hazard detection:

1. realize the internal data structure of circuit, electric circuit element is sorted.

2. marking circuit element.

Rubidium marking composed as follows: we specify a value number of representing this original input to each original input of circuit.To each electric circuit element G, we introduce a mark and write down the time delay information that is input to this element from original, and the mark of G is made up of a series of node.Each node is made up of an original input numbering and a path sequence.For arbitrary element G, be recorded in the path sequence of element G with this original node that is input as numbering from certain original all path that are input to it.If have the number of the door (not gate, NAND gate, NOR gate) of inverter functionality on certain paths and be odd number so this paths length be negative value, be even number if having the number of the door of inverter functionality, so the length of this paths be on the occasion of.

The method of marking circuit element is as follows: at first each original input I is labeled as I (0).Other element in the marking circuit in regular turn then.The mark of an element is that the mark by its all fan-in elements generates as follows: (1) is by the node in the mark of all fan-in elements of this element of ascending order merger of original input numbering.To the node of identical original input numbering, their path sequence of ascending order merger of sequence by path. (2) revise each path sequence of merger: the absolute value of each path is added this element delay, if this element is not gate, NAND gate, NOR gate, then with the symbol negate of original path value.Fig. 3 is the full adder circuit through mark.

3. according to the mark of electric circuit element, judgement may produce the electric circuit element of risk.

Have a node in the ifs circuit in the mark of certain, have two values in its path sequence, their opposite in signs, and the difference of absolute value is greater than gate delay are then thought may produce risk at this output.Fig. 4 is the testing result of full adder circuit.We find, are numbered in 3 the node with original input in the mark of door l2 to have two values-4,2, and the difference of their opposite in sign and absolute value is greater than the delay of door 12, so 12 output may produce a risk.

Based on the risk removing method of the static delay character of circuit, eliminate the risk that single original input saltus step produces by the delay of some in the selectable increase circuit; Eliminate the risk that a plurality of original input saltus steps produce by the propagation that increases delay gate synchronous circuit signal.

The method of the risk that the single original input saltus step of elimination or minimizing causes:

Suppose to detect the risk point as stated above, eliminate the path sequence of the method for the point of taking a risk based on expansion.The path sequence of expansion is to be expanded as follows and get by path sequence: in back increment family of adding of each path value of path sequence, the path after the expansion is become:

Form.

In order to eliminate a risk point, we are from this point, according to the path sequence of expanding each from the original order that outputs to original input.This is equivalent to provide for eliminating a risk point, according to detect the opposite order of risk tag sequence and expand the path sequence of each, how many those delays with this spot correlation should be increased.After expansion finishes (expanding original input), calculate in the increment family in each the extensions path sequence all summations of expectation number of times, note is made this total expectation number of times.Find out and always expect in the circuit that number of times maximum and increment all are not 0 door, increase the minimum value of increment in its all increment families for this.Specific implementation comprises following step:

1. in the mark of the electric circuit element that is judged as risk, add increment.

If the time-delay of door G is δ, one of the absolute value maximum is MAX in the path sequence of G, and then the increment of path adjustment is MAX-δ in this sequence.To each path length in the path sequence, if | length| 〉=MAX-δ, just no longer to adjust, this increment is made as 0.If | length|＜MAX-δ, increment that then will this item be made as MAX-δ-| length|.

2. expand the mark of other electric circuit element one by one according to inverted order from outputing to input

We expand the path of this element as follows.

The first step: from the node of all fan-out elements of this element, be each path of this element, find out in its fan-out element extensions path length with this path-length match.Be τ the time of delay of supposing certain fan-out element of this element, and anti-phase coefficient is Rev (the anti-phase coefficient of NOR gate is-1 for not gate, NAND gate, and the anti-phase coefficient of other door is 1).The extensions path length of the path of this element and its fan-out element is complementary, and the path value that refers to this element (is designated as SPL ₁) (be designated as SPL with path value in the extensions path length of its fan-out element ₂) have such relation: (SPL ₁+ τ) * Rev=SPLX

Second step: the increment family that merges the extensions path length of mating in all fan-out elements of this element obtains the increment family of this element.All unequal increment sizes in the increment family of its fan-out element should be contained in the increment family of this element, and the expectation number of times of the increment correspondence of this element should be the expectation number of times sum of the same increment of all fan-out elements.

3. find to be requested to add the maximum electric circuit element of increment number of times, increase the gate delay of this element.

Concrete steps are referring to Fig. 5 .1-5.5.Fig. 5 .1-5.5 shows the process of expansion full adder circuit element.The delay that Fig. 5 .6 shows electric circuit element 9 increases by 1, thereby has eliminated the risk at original output 14 places.

Method that realize to eliminate or reduce the risk that a plurality of original input saltus steps cause comprises following step:

1. be input to original output to the electric circuit element classification from original.

We specify and originally are input as the 0th grade.The progression of other electric circuit element is determined according to formula 4 by the delay of its all fan-in elements and this element, the progression of Level in the formula 4 (G) expression element G, f _iThe fan-in element of expression element G.

Formula 4

The explanation of Fig. 6 in the description of drawings has provided the result to the element classification of full adder circuit.

2. circuit is carried out Synchronous Processing.The treatment circuit element makes signal identical from the delay that original input arrives this grade element step by step.

We begin door (having only the door of a fan-in to disregard) the treatment circuit step by step from original input.If a plurality of fan-ins of a door are on different levels, we keep that fan-in of progression maximum constant, and increase delay gate on the less fan-in of those progression, make the progression of these fan-ins all equal the maximum progression that this door leaf is gone into.Fig. 6 shows the full adder circuit of using after this method is handled.

Claims (7)

1. based on the Hazard detection method of the static delay character of circuit, the delay character of considering circuit comes decision circuitry may produce the point of risk, it is characterized in that the original original output marking circuit element one by one that is input to from circuit, to be recorded in the path sequence of this element from the original information in the path delay of time that is input to this electric circuit element, produce the possibility of taking a risk according to these information decision circuitry points then.

2. according to the Hazard detection method based on the static delay character of circuit of claim 1, it is characterized in that the method for marking circuit element is as follows: at first each original input I is labeled as I (0), then other element in the marking circuit in regular turn; The mark of an element is that the mark by its all fan-in elements generates as follows: (1) is by the node in the mark of all fan-in elements of this element of ascending order merger of original input numbering; To the node of identical original input numbering, their path sequence of ascending order merger of sequence by path; (2) revise each path sequence of merger: the absolute value of each path is added this element delay, if this element is not gate, NAND gate, NOR gate, then with the symbol negate of original path value.

3. according to the Hazard detection method based on the static delay character of circuit of claim 1, it is characterized in that, there is a node in the ifs circuit in the mark of certain, there are two values in its path sequence, their opposite in signs, and the difference of absolute value is greater than gate delay, then thinks may produce risk at this output.

4. based on the risk removing method of the static delay character of circuit, it is characterized in that eliminating the risk that single original input saltus step produces by the delay of some in the selectable increase circuit; Eliminate the risk that a plurality of original input saltus steps produce by the propagation that increases delay gate synchronous circuit signal.

5. eliminate the method for the risk that single original input saltus step causes, step is as follows; According to detect the opposite order of risk tag sequence and expand the path sequence of each, obtain to eliminating a risk point, should how many those delays with this spot correlation be increased, after expansion finishes, calculate in the increment family in each the extensions path sequence all summations of expectation number of times, remember total expectation number of times of doing this, find out and always expect in the circuit that number of times maximum and increment all are not 0 door, give the minimum value in these its all increments of increase.

6. the method for the risk that causes according to the single original input saltus step of the elimination of claim 5 is characterized in that specific implementation comprises following step: add increment in the mark of the electric circuit element that is judged as risk;

If the time-delay of door G is δ, one of the absolute value maximum is MAX in the path sequence of G, then the increment of path adjustment is MAX-δ in this sequence, to each path length in the path sequence, if | length| 〉=MAX-δ, just no longer to adjust, this increment is made as 0, if | length|＜MAX-δ, increment that then will this item be made as MAX-δ-| length|; Expand the mark of other electric circuit element one by one according to inverted order from outputing to input:

Expand the path of this element as follows;

The first step: from the node of all fan-out elements of this element, each path for this element, find out in its fan-out element extensions path length with this path-length match, be τ the time of delay of supposing certain fan-out element of this element, anti-phase coefficient is the Rev not gate, NAND gate, the anti-phase coefficient of NOR gate is-1, the anti-phase coefficient of other door is 1, the extensions path length of the path of this element and its fan-out element is complementary, and the path value that refers to this element is designated as SPL ₁Be designated as SPL with the path value in the extensions path length of its fan-out element ₂Has such relation: (SPL ₁+ τ) * Rev=SPL ₂,

Second step: the increment family that merges the extensions path length of mating in all fan-out elements of this element obtains the increment family of this element, all unequal increment sizes in the increment family of its fan-out element should be contained in the increment family of this element, and the expectation number of times of the increment correspondence of this element should be the expectation number of times sum of the same increment of all fan-out elements;

Find to be requested to add the maximum electric circuit element of increment number of times, increase the gate delay of this element.

7. eliminate the method for the risk that how original input saltus step causes, step is as follows; (1) at first circuit is input to original output according to following formula classification from original,

(2) then, begin door the treatment circuit step by step from original input, have only the door of a fan-in to disregard, if a plurality of fan-ins of a door are on different levels, we keep that fan-in of progression maximum constant, and on the less fan-in of those progression, increase delay gate, make the progression of these fan-ins all equal the maximum progression of this all fan-in.

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