CN1308378A - Buried metal contact structure and manufacture of semiconductor FET device - Google Patents

Abstract

An SOI MOSFET is described having a body region between and separating the source and drain. A buried metal path is placed directly under the body region and aligned with the gate. The buried metal is in contact with the body region but not with the source and drain. The structure includes a metal interconnect directly below the device, wherein one or more metal interconnect layers contact the silicon insulator from below the device through a buried metal oxide layer. In this method, the lower part of the source/drain diffusion region and the body region can be coupled together. In particular, the body contacts here have considerably lower resistance across the device width than conventional body contacts.

Description

Buried metal body contact structure and method of fabricating SOI MOSFET devices

More generally, the present invention relates to semiconductor integrated circuit devices and methods of making these devices. More specifically, the present invention relates to SOI (silicon-on-insulator) CMOS devices with buried metal body contacts for improved performance and reduced size.

Silicon-on-insulator (SOI) has emerged as an alternative to conventional bulk growth techniques commonly used in high-performance VLSI (large-scale integration) device production. The main difference between the two technologies is how the body of the transistor (the region directly under the gate of the CMOS device, and more precisely, the region between the source and drain) is connected. In bulk growth techniques, the bulk exists in a well or in a substrate. Therefore, the body can be easily connected to a fixed potential without sacrificing area or performance. However, applying a typical body switch design like a DTMOS (Dynamic Threshold Voltage MOS) FET to bulk growth technology is not feasible because of the critical junction between the well and the substrate. Information about DTMOS devices is described in detail in US Patent No. 5,559,368 "Ultra-Low Voltage Dynamic Threshold Voltage MOS FET with Gate-to-Body Connection Structure". In this article it was found that threshold voltage IGFETs such as MOSFETs can operate at 0.6V or less. A voltage-controlled channel is provided in the body of the device, and by interconnecting the gate contact with this body, the threshold voltage of the transistor can be reduced to zero or less.

F. Assaderaghi made the first report on the dynamic threshold MOS FET (DTMOS) in 1994. The article was published in Electron Device Letters (USA) Vol.15, No.12, pp.510-512, titled "Ultra-low Voltage VLSI with Dynamic Threshold Voltage MOSFET (DTMOS)". By connecting the gate and body together, the threshold voltage at large gate voltages is lowered. This phenomenon leads to a large current drive, which is much higher than that in a standard MOSFET operating at a low supply voltage, while still maintaining a low leakage current at Vgs=0.

Figure 1 shows a schematic diagram of the layout design of a traditional SOI body contact device. Source 40 , drain 30 and body contact 10 are located within a single SOI island 60 . To facilitate body contact under the gate 50 , the gate needs to be extended to include an additional region 20 . Due to the low conductivity of the well, the resistance from the body contact to the middle of the device is high. In addition, since the channel length is usually much shorter than the channel width, the number of squares (that is, the aspect ratio) and the total resistance value are also large. A DTMOS device can be made by connecting the gate extension region 20 to the body contact 10 with an additional interconnect layer. The extended region 20 of the gate for body contact does not contribute to current drive, but it is worth noting that it significantly increases the overall gate capacitance. All of this translates into performance degradation (typically >20%) and increased layout area. The drawbacks of these non-ideal conditions are so severe that DTMOS technology is almost an impractical behavior relative to SOI technology.

In SOI technology, body connection is more difficult, because SOI technology requires a special layout for body connection. These layouts usually increase the occupied area of the device, and at the same time reduce the performance of the device due to the addition of more capacitors. Considering the foregoing, the transistor body in SOI VLSI technology is usually suspended, leaving only a few transistors to connect them. However, body floating can cause circuit instability as the potential of the floating body fluctuates, causing the delay of the circuit to depend on its previous history. In order to ensure the function of the circuit, the transistor designer needs to be more conservative. For example, in order to improve the noise margin, the threshold voltage of the device must be made higher. All of these factors involving body float affect the performance of SOI circuits. Therefore, it is very beneficial to obtain a body contact that is considered efficient without adding additional area and capacitance. This body contact can substantially improve the switching characteristics of the bulk, as is the case with bulk DTMOS currently used in SOI, for example. For example, DTMOS is the only process that can make CMOS circuits work at a low power supply of 0.2V while obtaining satisfactory performance. When operating on the same power supply as a conventional CMOS circuit, the power dissipation provided by DTMOS is much smaller than that provided by a CMOS circuit. In order for a DTMOS to work properly, the alternate resistance must be dropped small enough so that the body potential varies with the switching input. The only process that reduces resistance by an order of magnitude is to lay metal directly under the body, as detailed in the following article.

In an article published in Symposium on VLSI Technology Digest of Technical Papers, PP.23-24 in 1997, entitled "0.25μmWpolycide dual gate and buried metal on diffusion layer (BMD) technology for DRAMembedded logic devices (α25μm of DRAM buried logic devices Polysilicon Double Gate and Buried Metal Diffusion Layer Technician)” describes a logic processing process suitable for high-speed, low-voltage operation logic and DRAM integration on a single chip. In order to manufacture buried DRAM, the method of chemical oxide layer is deliberately used when growing large-grained polysilicon, thus obtaining a W poly-acid double-gate process with high thermal stability. Annealing at 1000°C for 10 seconds followed by annealing at 850°C for 30 minutes prevented the diffusion and penetration of lateral dopants and boron into the 5nm thick gate oxide. The buried metal process uses high-energy metals (such as Ti) to implant a metal silicide layer (such as TiSi ₂ ) to reduce the diffusion resistance. However, the described process does not provide a second interconnection layer, nor does it have a connection to the MOSFET body. Furthermore, this process is not compatible with SOI technology.

A similar method is also described in U.S. Patent No. 5,236,872 "Method of manufacturing a semiconductor device having a semiconductor body with a buried silicide layer (semiconductor body with a semiconductor device manufacturing method of buried silicon layer)", in this article In this method, a thin layer of buried silicide is fabricated inside the semiconductor device by implantation. This process includes the first step of forming an amorphous layer by implantation, followed by thermal treatment, and then converting this layer into buried silicide. layer. In this way it is possible to obtain a buried silicide layer with a thickness of 10 nm, which structure is then suitable for the production of, for example, metal-body transistors. Like the previous quote, this process is not compatible with SOI technology.

In Proceeding of the Third International Symposium on Semiconductor Wafer Bonding: Physical and Application (1995), PP.553-560, another article entitled "Buried metallic layer with silicon direct bonding (buried metal layer directly bonded to silicon)" In the article, a fabrication method for bonding a low-resistivity buried metal silicide layer with an insulating isolated silicon substrate is described. The corresponding silicide is formed by the solid-phase chemical reaction generated by sputtered W or Ti. Stress and wafer warpage are avoided by completing the bond before silicide formation. Tungsten lamination bonding is obtained by first covering a layer of polysilicon and polishing it before bonding. Annealing is performed at 1000° C. to consolidate the bonding and form WSi ₂ with a resistivity of 300 hm/square. The WSi ₂ layer is refractory and resistivity will not increase when subjected to heat treatment at 1000°C for 6 hours. A low-energy, small-dose phosphorus implant is performed on the m-type active wafer to ensure ohmic contact with _WSi2 . A buried _TiSi2 layer can be obtained by bonding a Ti layer to a silicon or silicon covered oxide substrate. Rapid thermal treatment (RTA) at 800°C for 10 seconds can simultaneously form TiSi ₂ and bond. The resistivity of TiSi ₂ is 180hm/square. Due to the non-uniform heating during RTA, the bonded wafer will have air voids around its periphery. The TiSi ₂ layer, although refractory, can react with boron to reduce conductivity. In order to separate the TiSi ₂ layer from the oxidized wafer, a silicon spacer layer is added. The described process forms a metal layer under the silicon prior to any device formation. The metal pattern on one side of the wafer is bonded to the other wafer. The surface of the other wafer must be silicon, not oxide. However, no hint is given whether the process can be used to build SOI transistors and connecting bodies.

There is also an article published in IEEE Transactions of Electron Devices, Vol.45, No.5, May 1998, PP.1084-91 entitled "SOI MOSFET with buried body strapby wafer bonding (wafer bonded to form SDI MOSFET with buried body straps) )” describes a device with a buried oxide in an SOI MOSFET, which enables higher performance. This structure allows for various body-floating effects, including kink effects, leakage current transient effects, and history-dependent effects on output characteristics. As mentioned earlier, adding an effective contact to the bulk is very difficult due to the constraints imposed by the SOI structure. In order to maintain the symmetry of the device, side body contacts can be chosen. However, due to the very high lateral bulk resistance, such contacts are only functional in narrow-width devices. Buried lateral body contacts in SOI consist of low resistance polysilicon strips running across the width of the device under the body of the MOSFET. MOSFETs with an effective channel length of 0.17 μm combined with this buried-body-strip process have been fabricated and demonstrated improved breakdown voltage characteristics. The described process forms only buried polysilicon and no buried metal. Buried polysilicon is formed by bonding prior to device formation.

In addition, there is an article entitled "Thin film quasi SOIpower MOSFET fabricated by reversed silicom wafer direct bonding" published in IEEE Transactions of Electron Devices, Vol.45, No.1, Jan.1998, PP.105-109 Formation of Thin Film Quasi-SOI Power MOSFET by Direct Bonding)” describes a quasi-SOI power MOSFET made by direct bonding of silicon wafers on the back side. In this power MOSFET, the buried oxide under the channel and source regions is removed, and in order to reduce the reference resistance of the parasitic npn diode transistor, the channel region is directly connected to the body contact electrode of the source. Quasi-SOI power MOSFETs suppress parasitic transistor action and exhibit lower on-state (ON) resistance than conventional SOI power MOSFETs. The chip-level quasi-SOI power MOSFET exhibits an on-state resistance of 86mΩ.mm ² and an on-state breakdown voltage of 30V. Although the process mentions SOI CMOS devices, it does not mention buried metal.

In the U.S. Patent No. 5,332,913 "Buried interconnect structure for semiconductor devices (buried interconnect structure for semiconductor devices)", a semiconductor device with an improved concentration of a buried interconnect structure is described. The buried interconnection forms an electrical connection with the electrical device region on the semiconductor substrate, so that other structures can directly cover the buried interconnection without forming an electrical connection with the conductive part of the interconnection. Interconnects consist of buried conductors and conductive parts. The conductive portion is electrically bonded to the conductor to form a conductive path. First, a buried conductor is formed in the oxidized portion of the first field oxide. A selective multi-epitaxial silicon layer is then grown on the surface of the substrate. A non-conductive portion of a layer of selective poly-epitaxial silicon is then formed on the buried conductor by oxidizing at least a portion of the selective poly-epitaxial silicon layer. The non-conductive portion of this selective poly-epitaxial silicon allows other structures to be fabricated on the buried conductor without making direct electrical contact with the buried interconnect. Thus, the buried metal is formed by using selective poly-epitaxial silicon growth.

In the U.S. Patent No. 5,702,957 "Method of making buried metallization structure (method of making buried metallization structure)", a method that can directly provide wires for paths in the semiconductor substrate under the active IC device level IC structure. These buried wires are insulated from each other by dielectric regions formed directly under the active devices in the form of an insulating plane, similar to conventional silicon-on-insulator (SOI) structures. However, in this plane, buried wires provide vias for various active device components to form circuit connections, such as inter-cell connections for gate arrays. Thus, buried wires replace some of the vias from the metallization/dielectric layer stack on the active area. Here, the buried metal is formed by implanting a high-energy metal into the substrate prior to device processing.

In the U.S. Patent No. 5,306,667 "Process for forming novel buried interconnect structure for semiconductor devices (process of novel buried interconnect structure for semiconductor devices)", an improved concentration of buried interconnect structure is described. Semiconductor device. The buried interconnect combines a raised source/drain structure (formed by selective poly-epitaxial silicon growth) and a silicon-treated source-drain-gate interconnect portion. First, a buried conductor is formed on the oxidized portion of the first field oxide. Then grow a layer of selective multi-epitaxial silicon layer on the surface of the substrate. Selected regions of the multi-epitaxial silicon layer are oxidized. The refractory metal layer is deposited, annealed and etched to form buried interconnects. Thus, the buried metal is formed by selective poly-epitaxial silicon growth.

In the U.S. Patent No. 5,260,233 "Semiconductor device and wafer structure having a planar buried interconnect by wafer bonding (semiconductor device and wafer structure of planar buried interconnection formed by wafer bonding)", a wafer structure is described, The structure is suitable for forming semiconductor devices on it, and has a buried interconnection structure, and the selected semiconductor devices can be interconnected according to predetermined interconnection patterns and similar methods. The wafer structure consists of a base substrate formed with first layers of just the right thickness for the fabrication of the desired semiconductor devices. The base substrate further includes: a) a second layer thickness formed on the lower surface of the base substrate according to a predetermined interconnect pattern, that is, conductive interconnection pads; b) a third layer formed between the conductive interconnection pads on the lower surface of the base substrate layer thickness, i.e. the first insulating disk; c) the fourth layer thickness formed on the surface of the interconnection disk opposite to the base substrate, i.e. the interconnection disk cap, wherein the interconnection disk cap is made of a suitable It is formed by the material used for wafer bonding, and the total thickness of the second layer and the fourth layer is equal to the thickness of the third layer. The structure also includes a second substrate having an oxide layer thereon bonded to the interconnect pad cap and the first insulating pad of the base wafer. Here, the buried metal is formed by bonding prior to the device process.

In the U.S. Patent No. 4,977,439 "Buried multilevel interconnect system (buried multilevel interconnection system)", methods and devices for providing interconnection between various levels of semiconductor substrates include: in the substrate A plurality of moats are formed, and then a conductive layer is formed on the bottom of the moats. The trenches are then filled with oxide to form a flat surface on the substrate. Cross-connects are provided for each level of trenches by forming a bridge layer of conductive material over the oxide in the lower level trenches. Use the corrosion method to make an opening from the surface through the oxide layer to the bottom of the trench, and then fill the opening with a metal plug, so that the contact in the vertical direction is formed. Here, the formation of the buried metal starts at the upper surface. This approach is limited in that the buried metal must be highly positioned, and in addition the buried metal cannot be placed underneath the device.

In the U.S. Patent No. 4,778,775 "Buried interconnect for silicon on insulator structure (buried interconnection of silicon-carrying insulator structure)", an improved process is mentioned, which can form a recrystallized polysilicon layer on the insulating layer The interconnection is realized in the process. Recrystallization occurs through multiple seeding windows formed in the insulating layer. Before the polysilicon is deposited, a doped region is formed on the substrate. The polysilicon layer is in contact with at least part of the doped region through the opening in the insulating layer. Recrystallization occurs through these openings, and the doped region forms an electrical connection with the source or drain region of the semiconductor device formed in the recrystallized layer. Buried metal or doped silicon is formed prior to any device processing, and SOI material is formed by selective epitaxial growth through the seeded window.

Accordingly, the object of the invention is not only to reduce the size of SOI MOSFET or DTMOS devices but also to increase their performance and density by introducing buried metal body contacts in the structure.

Another object is to provide additional interconnect layers under the active area of the device.

Yet another object is to eliminate body floating in devices fabricated in SOI technology.

Yet another object is to form a three-dimensional integrated circuit by laying metal directly under the active regions.

It is also a special purpose to fabricate a high-density, high-speed lateral bipolar device with buried body contacts.

In a part of the present invention, a structure and process are presented, which can form metal interconnection directly under the device fabricated by conventional SOI CMOS process. One or more layers of interconnection begin below the device through the buried oxide to contact the silicon insulator. In this way, the bottom of the source or drain diffusion region and the body of the MOSFET can be contacted together. Additionally, the structure and process provide an extremely low resistance ground connection to the bottom of the MOSFET body region.

The advantage of this structure is that it eliminates body floating effects - an important consideration in SOI technology. Furthermore, body contacts can reduce standby power by applying a reverse-biased body voltage to achieve power savings. More importantly, DTMOS devices can be fabricated by adding a gate to the body. In this DTMOS device, the threshold voltage is reduced in the turn-on state, thus increasing the current drive.

The invention fully utilizes the advantages of DTMOS technology. In addition to providing body contacts for SOI devices, the method also allows the formation of multiple layers of metal beneath the device, thereby increasing device density and performance.

In another part of the present invention, an SOI MOS device having a source, a drain and a gate is provided, and the SOI MOS device includes: a body region positioned between the source and the drain and separating the source and the drain; The buried metal under the body region and combined with the gate, the buried metal does not have any contact with the source or drain when it is in contact with the body region.

Another part of the present invention provides a dynamic threshold MOS device with source, drain and gate. The dynamic threshold MOS device includes: a body region located between the source and drain; a body region directly laid under the body region and connected to The buried metal with the gates bonded together; the buried metal does not have any contact with the source or drain when in contact with the body region, and the buried metal extends along the gate and contacts the gate.

Although the specification summarizes the object of the present invention by way of specifically pointing out and directly declaring claims, the advantages of the present invention can be understood more deeply from the following description of the present invention and reading the accompanying drawings.

Figure 1 shows a schematic top view of a prior art SOI device layout with body contacts;

Fig. 2a is a schematic top view of a buried SOI DTMOS device layout according to the present invention;

Figure 2b is a schematic top view of an SOI device layout with buried metal body contacts according to the present invention;

Figure 3 is a side view of a representative SOI CMOS wafer when it is just formed, especially showing the bulk silicon substrate, buried oxide (BOX) and the body of the SOI MOSFET;

Figure 4 illustrates the structure when a handle substrate is added to the structure of Figure 3;

Figure 5 illustrates the structure of Figure 4 with bulk silicon removed;

Figure 6 shows pores opened in the oxide (BOX) layer;

Figure 7 shows that the aforementioned hole is now filled with hole filler;

Figure 8 shows several interconnection layers on top of the BOX layer for making contact with the terminals of the MOS devices; and

Figure 9 illustrates the layout of an SOI flanked bipolar transistor with buried metal-body contacts, similar to the SOI device with buried metal body contacts described in Figure 2b.

The general process for laying metal directly under the active region of an SOI wafer is first described, followed by the process for providing the body contact for SOI MOSFETs. Finally, a description will be given of how to connect the gate to the body in order to form the DTMOS.

Referring to FIG. 2a, there is shown a top view of a SOIDTMOS device with the gate placed on the buried metal body according to the present invention. Although the buried metal pattern can be wider or narrower depending on the chosen process, the buried metal pattern is shown here as wider than the gate pattern for clarity. The buried metal is aligned with the gate pattern.

The drain 30 and source 40 described in prior art FIG. 1 remain unchanged. The extended gate region 20 in FIG. 1 is replaced by a gate terminated in a reduced configuration. Both source and drain are fabricated on the first SOI island 60 . The gate-to-body connection is made by a contact 70 through the gate oxide. In the through gate oxide contact, the gate oxide is removed to provide a contact between the gate and the second SOI island in contact with the buried metal 80 . As shown, the gate-to-body connection does not require additional area compared to conventional MOSFET layouts, thus avoiding the appearance of non-ideal additional gate capacitance.

Figure 2b shows a top view of a body contact MOS device according to the second solution of the present invention. In Fig. 2a, the gate contact and body contact are integrated. Unlike Fig. 2a, in Fig. 2b, separate gate contact 50 and body contact 10 are provided, so that the bulk voltage can be independently controlled. Note that the structure shown in Figure 2b does not require an extended gate region 20, thus eliminating the additional added capacitance caused by the extended gate. It is evident that the device shown in Figure 2b occupies a much smaller area than the prior art device shown in Figure 1 .

Referring now to FIG. 3, there is illustrated a cross-sectional view of an SOI CMOS device according to the present invention, which explicitly shows bulk silicon substrate 100, buried oxide (BOX) 110, and body 130 of the SOI MOSFET. Also shown are through gate oxide contacts 70 connecting the gate 50 and the second silicon island 60 together. This sketch represents a cross-section viewed from the line B-B'. When looking over line A-A', it will be seen that the contacts (eg, 120) connect the source and drain with other circuits, devices, etc. (not given).

Referring to FIG. 4, there is shown a processing die 170 attached to the upper side of the wafer of FIG. The handle layer is preferably made of silicon or glass of sufficient thickness for machining (eg, on the order of 0.5 ^mm2 for an 8 inch wafer). The shape of the handle layer is preferably the same shape as the wafer, and the edges should match the edges of the wafer. Since the buried metallization process will be carried out later, the bonding material needs to be able to withstand high temperatures above 300°C. The handle substrate can be bulk, SOI, or even glass. It only acts as a mechanical support.

The bulk silicon on the original wafer is etched away from the backside using chemical and/or mechanical polishing until the buried oxide (BOX) is exposed (see Figure 5). This backside etch process is similar to the bond and backside etch process designed for SOI, except here the chemical etch, usually KOH, a solution of potassium hydroxide, can easily stop at the buried oxide . This results in a fairly flat and clean oxide surface. This surface is very important for high-resolution photolithography, which will be discussed further below. Since mechanical grinding cannot stop on the oxide, chemical etching must be the last etching step.

Referring to Figure 6, standard photolithography processes create a path for etching. This path is aligned with the front side pattern of the original wafer. Since the thickness of the buried oxide is generally 100-300nm, it is transparent. In this way, most of the structures on the original wafer, such as STI (Shallow Trench Isolation) and gate patterns, can be very easily aligned visually. To achieve alignment properly, the path is mirrored. Afterwards, the oxide in the open area is removed by an etching technique such as RIE. The etch should stop right at the oxide-silicon interface. Overetch is allowed if the etch does not touch the source, drain, and gate regions.

Referring to Fig. 7, the opened path is then filled with a suitable filler, preferably a metal such as tungsten. If the opening is wide enough, the metal (Al or Cu) can be formed in one damascene process. In order to ensure a good contact with the MOS body region 130, it is required that the inner surface forming the interface with the path 190 must be metal or properly doped silicon.

Referring to FIG. 8, multiple layers of metal 140 (preferably Cu or Al) are formed on top of BOX 110 using conventional metal deposition and etching processes. These metal layers provide interconnections between buried metal paths.

Referring now to FIG. 9, there is shown a top view of an SOI sided bipolar phase fabricated in accordance with the present invention. This structure is similar to the body contact MOS device shown in Figure 2b. Here, the body region becomes the base of the bipolar device, and the emitter region and the receiver region correspond to the source and drain of the MOS device, respectively. To save space, the gate is preferably left floating. Alternatively, the gate can be tied to a fixed voltage, at the expense of increased layout area.

Through the description of the above structure, the following advantages are proved:

Instead of connecting the body to the gate of the same transistor, it can be connected to the node of another device. Depending on the condition of the output load, the bulk voltage can be boosted to increase the current drive when needed.

High performance lateral bipolar device

With effective body contact, the device can be made to operate as a bipolar transistor. This bipolar transistor is notable for its high speed due to the low substrate resistance and substrate-to-collector capacitance. Since bipolar transistors are superior to CMOS in analog applications, the present invention enables complete integration of high performance analog and digital circuits. For example, the impact on wireless communication is very important.

general physical contact

DTMOS is just one example of the benefits of introducing body contacts that can reduce area and have low resistance in SOI technology. In addition, this brand new physical contact can also play a role in the following aspects:

A. Eliminate volume floating effect

All the disadvantages of floating the body can be eliminated by body biasing the voltage and/or connecting the body to the source. This not only enhances the performance of the circuit, but also improves the stability of the circuit.

B. Save power consumption

Standby power can be reduced by applying a negative body bias voltage to the NFET device, or a positive body bias voltage to the PFET. This technique cannot be generalized to conventional SOI technology, because adding body contact to conventional SOI technology sacrifices area. According to the present invention, no problem arises in applying the techniques described above. From an area perspective, this technique may be more efficient than bulk-effect techniques, since the body contact established at the lower portion can be independent of the connection to the transistor located above.

Several typical schemes have been described above for the purpose of illustrating and elaborating several conceptual points of the present invention. But the present invention is not limited to these schemes, more precisely, various changes and modifications can also be made from the details without departing from the gist of the present invention and the scope and scope specified by the claims.

Claims (11)

1. the MOS device of long silicon (SOI) on insulator with source, leakage and grid, this SOIMOS device comprises:

This tagma that between above-mentioned source and leakage, also this source and leakage is separated; With

One is directly placed under above-mentioned this tagma and the buried metal path of aiming at above-mentioned grid formation; When contacting with above-mentioned this tagma, this buried metal can not run into above-mentioned source or leakage.

2. according to the SOI MOS device in the claim 1, wherein, above-mentioned buried metal and buried oxide layer are with being in the same plane.

3. according to the SOI MOS device of claim 1, wherein, an interconnection that is positioned under the above-mentioned buried metal is connected to buried metal on other circuit.

4. dynamic threshold MOS device with source, leakage and grid, this dynamic threshold MOS device comprises:

This tagma between above-mentioned source and above-mentioned leakage; With

One is directly placed under above-mentioned this tagma and the buried metal path of aiming at the formation of above-mentioned grid region, this buried metal path can not be run into above-mentioned source or leakage when contacting with above-mentioned this tagma, above-mentioned buried metal forms along above-mentioned grid expansion and with above-mentioned grid and contacts.

5. according to the dynamic threshold MOS device of claim 4, wherein, above-mentioned buried metal path is passed a SOI island and is contacted with above-mentioned grid formation, this SOI island and above-mentioned source and leakage insulation, and this SOI island further forms with above-mentioned grid and contacts.

6. according to the dynamic threshold MOS device of claim 5, wherein, the resistance in above-mentioned this tagma of resistance ratio that above-mentioned SOI island has is an order of magnitude extremely when young.

7. according to the dynamic threshold MOS device of claim 4, wherein, above-mentioned buried metal path is contacted with above-mentioned grid formation by metal filled path by one.

8. a manufacturing has the method for the SOI MOS device of buried metal contact, and the method comprising the steps of:

A SOI substrate is provided, and this SOI substrate has one deck silicon thin film on a buried oxide layer, and this buried oxide layer is placed on the body silicon substrate;

Form a plurality of SOI island, form isolation on the electricity by insulating material between these islands;

On above-mentioned SOI island, form one deck and apply the shape insulating barrier;

Swing at above-mentioned at least one insulated SOI and to make grid;

Above-mentioned at least one have making source and leakage on the SOI island of above-mentioned grid, this source and leak between by this tagma they are separated;

Forming interconnection between above-mentioned leakage, source and the grid and thereby this interconnection is being connected to formation circuit on each element;

Insulating material is inserted in zone between above-mentioned each interconnection;

Trade mark face to above-mentioned insulating material carries out complanation;

An accessible substrate is adhered to above-mentioned through on the surface of complanation;

Thereby remove above-mentioned body silicon substrate and expose above-mentioned buried oxide layer;

Offer at least one window in above-mentioned buried oxide layer, this window is aimed at above-mentioned this tagma formation under the situation that does not cover above-mentioned source-drain area; With

Form buried path by in above-mentioned window, inserting metal.

9. according to the method for claim 8, also be included in the step of the other interconnection layer of adding under the above-mentioned buried path.

10. a manufacturing has the method for the SOI dynamic threshold MOS device of buried metal contact, and the method comprising the steps of:

A SOI substrate is provided, and this SOI substrate has one deck silicon thin film on a buried oxide layer, and this buried oxide layer is placed on the body silicon substrate;

Form a plurality of SOI island, form isolation on the electricity by insulating material between these islands;

On above-mentioned SOI island, form one deck and apply the shape insulating barrier;

On above-mentioned at least one insulated SOI island, make grid and these grid are expanded up to surpassing above-mentioned SOI island;

The above-mentioned grid that are expanded are contacted with second above-mentioned SOI island;

Above-mentioned at least one have making source and leakage on the SOI island of above-mentioned grid, and in this source with stay this tagma between leaking they are separated;

Forming interconnection between above-mentioned leakage, source and the grid and thereby this interconnection is being connected to formation circuit on each element;

Insulating material is inserted in zone between above-mentioned each interconnection;

Trade mark face to above-mentioned insulating material carries out complanation;

An accessible substrate is adhered to above-mentioned through on the surface of complanation;

Thereby remove above-mentioned body silicon substrate and expose above-mentioned buried oxide layer;

Offer at least one window in above-mentioned buried oxide layer, this window is aimed at above-mentioned this tagma formation under the situation that does not cover above-mentioned source-drain area, and above-mentioned window is expanded above-mentioned SOI island and contacted with above-mentioned grid through above-mentioned second SOI island; With

Form buried path by in above-mentioned window, inserting metal.

11., also be included in the step of the other interconnection layer of adding under the above-mentioned buried path according to the method for claim 10.

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