CN1306820C - Fractional pixel filter system and its filter method for video frequency decoding chip - Google Patents
Fractional pixel filter system and its filter method for video frequency decoding chip Download PDFInfo
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Abstract
The present invention relates to a fractional pixel filtering system and a filtering method for a video decoding chip. The system comprises a memory, a data transmission circuit with a register array, and a low pass filter with four data selectors, wherein the low pass filter is a low pass filter base on a production line. The data transmission circuit is connected with an external memory. A whole pixel matrix which is received from an interface of the external memory is stored in the memory in a row mode. Positions of whole pixels which are sent by the memory are circularly moved by the register array, and movable whole pixels after circulation are sent into the low pass filter. 1/2 filtering and 1/4 filtering are carried out in the low pass filter. A flow mode of a data is controlled by the data selectors according to positions of fractional pixels, and the positions of the fractional pixels are outputted. The movement search of the fractional pixels is realized by the present invention by using a hardware mode, and the efficiency of a decoder is enhanced. The present invention is suitable for the interpolation of the fractional precision pixels of a video decoding chip.
Description
Technical field
The invention belongs to digit image coding/decoding technology and SOC (system on a chip) technology (SOC, system onchip) technical field, specifically, is a kind of video decoding chip fraction pixel filtering system and filtering method thereof based on the AVS standard.
Background technology
The effective video encoding and decoding technique is to realize multi-medium data storage and the key of transmitting, and advanced video coding and decoding technology exists with the form of standard usually.The MPEG series international standard that the Motion Picture Experts Group (MPEG, MovingPicture Expert Group) that at present typical video compression standard has International Organization for Standardization to divide into releases; The H.26x series video compression standard that International Telecommunication Union proposes, and the video encoding standard A VS that formulating of China oneself.
Motion search is an of paramount importance part in the video encoding standard, traditional motion search all can only search integer-pel precision, but in order to improve search precision, new video standard such as mpeg4, h.264 all support the search of fraction pixel precision, AVS also supports the search of 1/4 pixel precision, in order to realize the search of fraction pixel precision, must use low pass filter to obtain the value of fraction pixel.But low pass filter algorithm is very complicated, and as if the time of realizing with software then needing to exhaust decoder nearly 1/3rd, decoding efficiency is lower.Simultaneously, the data multiplex rate is also lower, has wasted the bandwidth of memory.
Summary of the invention
At above-mentioned problems of the prior art, the purpose that the present invention carries is to provide a kind of video decoding chip fraction pixel filtering system and filtering method thereof, to improve the efficient that low pass filter carries out the fraction pixel precision search.
For finishing the foregoing invention purpose, the technical solution used in the present invention is: video decoding chip fraction pixel filtering system, comprise memory, the data transmission circuit of band register array, the low pass filter of band data selector, low pass filter is based on the low pass filter of streamline, data transmission circuit is connected with external memory, to deposit register array in the form of going from the whole picture element matrix that the external memory control unit interface receives, the whole location of pixels of being sent by memory is moved in the register array circulation, and the whole pixel of the activity after will circulating is sent into low pass filter, low pass filter carries out 1/2 and 1/4 filtering, data selector is exported the fraction pixel position according to the type of flow of the Position Control data of fraction pixel.
Described data selector is 4.
Described whole pixel needs the whole picture element matrix of one 13 * 13 brightness; Described whole pixel needs 5 * 5 the whole picture element matrix of colourity.
Described register array is divided into two parts, and wherein top unit is active unit all the time, is 6 * 13 matrix.
The whole pixel of described activity is one 6 * 6 a matrix.
Described low pass filter is 4 tap F
1(1,5,5 ,-1) filter is predicted 1/2 sample position of nearest pixel samples.
Described low pass filter is 4 tap F
2(1,7,7,1) filter is predicted 1/4 sample position of nearest pixel samples.
Video decoding chip fraction pixel filtering method may further comprise the steps at least:
The pixel of the whole picture element matrix of being sent by memory is moved in step 3, register array circulation, and will send into low pass filter through the pixel of the mobile movable integer pixel matrix that obtains of circulation;
Step 5, the fraction pixel position is exported.
Register array circulation in the described step 3 is moved and be may further comprise the steps:
Step 31, in beginning 6 clock cycle, each cycle is taken out delegation's totally 13 pixels from memory, move into register array in the mode of moving horizontally;
Step 32, in 7 cycles next, array will be done in the circulation and move, it is effective to remain 6 * 6 top pixels;
Step 33, move into new one-row pixels with the inverted level of putting in order, 7 pixels of back are moved to the front in the 8th cycle;
Step 34, array are done circulation and are moved down;
Step 35,7 cycles move horizontally later again;
Whether the whole pixel of step 36, judgement input has moved, and intact then end is moved, otherwise repeating step 1.
Filtering in the described step 4 specifically may further comprise the steps:
Step 411, use F
1, F
24 integral sample filtering to nearest on level or the vertical direction obtain median;
Step 412, median are through after moving to right, and if resulting value is greater than 255, and then final predicted value is 255, and less than 0, then final predicted value is 0 as if the value that obtains, otherwise final predicted value is the resulting value that moves to right.
Described filtering specifically may further comprise the steps:
Step 421, use F
1, F
2Nearest 4 integers or fractional samples on the tilted direction are carried out 1/2 or 1/4 sample filtering, obtain median;
Step 422, median are through after moving to right, and if resulting value is greater than 255, and then final predicted value is 255, and less than 0, then final predicted value is 0 as if the value that obtains, otherwise final predicted value is the resulting value that moves to right.
Filtering in the described step 4 adopts multiplication to become the method for displacement and addition, divides 2-7 clock cycle to finish.
Filtering in the described step 4 is that the clock cycle is 2 with 1 1/2 filter filtering the 1st class point.
Filtering in the described step 4 is that the clock cycle is 4 with 2 1/2 filters and 1 1/4 filter filtering the 2nd class point.
Filtering in the described step 4 is that the clock cycle is 4 or 5 with 5 1/2 filters and 1 weighted average device filtering the 3rd class point.
Filtering in the described step 4 is that the clock cycle is 6 with 7 1/2 filters and 1 1/4 filter filtering the 4th class point.
The present invention has tangible advantage and good effect, based on video encoding standard, proposed a kind of based on streamline multiplexing filtering system and filtering method, realized the motion search of fraction pixel with hardware mode, solved with software mode and carried out problems such as decoder efficiency that the fraction pixel precision search time brought is low by low pass filter, save the decode time of Video Decoder, improved the decoding efficiency of Video Decoder.Be applicable to the interpolation of video decoding chip fraction precision pixel.
Description of drawings
Fig. 1 is a luminance component image sample matrix interpolation schematic diagram;
Fig. 2 is forecast sample motion vector figure;
Fig. 3 is a chroma sample interpolation schematic diagram;
Fig. 4 is fraction pixel filtering system modular structure figure of the present invention;
Fig. 5 is a register array cyclic shift schematic diagram;
Fig. 6 is luminance filter 1/2 a filtering schematic diagram;
Fig. 7 is to the 1st class point filter logical circuitry;
Fig. 8 is to the 2nd class point filter logical circuitry;
Fig. 9 is to the 3rd class point filter logical circuitry;
Figure 10 is to the 4th class point filter logical circuitry;
Figure 11 is a chrominance filter sample interpolation schematic diagram.
Embodiment
The present invention is further detailed explanation below in conjunction with the drawings and specific embodiments.
See also Fig. 1, this figure has provided the position of reference picture luminance component integral sample, 1/2nd samples and 1/4th samples, what wherein use the capitalization mark is the integral sample position, and with the lowercase mark is 1/2nd and four/the same this position.
The predicted value of two/the same this position is by 4 tap filter F
1(1,5,5 ,-1) calculates.The predicted value of four/the same this position is by 4 tap filter F
2(1,7,7,1) calculate.
The computational process of 1/2nd samples is as follows:
/ 2nd sample b: at first use F
1To 4 nearest on horizontal direction integral sample filtering, obtain median b '=(C+5D+5E-F); Final predicted value b=Clip1 ((b '+4)＞＞3).
/ 2nd sample h: at first use F
1To 4 nearest on vertical direction integral sample filtering, obtain median h '=(A+5D+5H-K); Final predicted value h=Clip1 ((h '+4)＞＞3).
/ 2nd sample j: at first use F
1On level or vertical direction,, obtain median j '=(bb '+5h '+5m '-cc '), perhaps j '=(aa '+5b '+5s '-dd ') to nearest 4 1/2nd sample medians filtering.Aa ' wherein, dd ' and s ' they are relevant position 1/2nd sample medians, they use F
1Filtering in the horizontal direction obtains, and bb ', cc ' and m ' are relevant position 1/2nd sample medians, and they use F
1Obtain in vertical direction filtering.Final predicted value is j=Clip1 ((j '+32)＞＞6).The value that adopts horizontal direction or vertical direction filtering to obtain is identical.
Illustrate: top employed clip1 is a cutting function, and greater than 255, then output is 255 as if the number of importing, if import less than 0, then exporting is 0, equals input otherwise export.
The computational process of 1/4th samples is as follows:
/ 4th sample a: at first use F
2In the horizontal direction to ee ', D ', four value filterings of b ' and E ' obtain median a '=(ee '+7D '+7b '+E '); Final predicted value a=Clip1 ((a '+64)＞＞7).Wherein ee ' and b ' are relevant position 1/2nd sample medians, and D ' and E ' are that the relevant position integral sample is amplified 8 times value.
/ 4th sample d: at first with F2 in vertical direction to ff ', D ', four value filterings of h ' and H ' obtain median d '=(ff '+7D '+7h '+H '); Final predicted value d=Clip1 ((d '+64)＞＞7).Wherein ff ' and h ' are relevant position 1/2nd sample medians, and D ' and H ' are that the relevant position integral sample is amplified 8 times value.The interpolation process of/4th sample n is identical with the interpolation process of d.
/ 4th sample i: at first with F2 in the horizontal direction to gg ', h ", j ' and m " four value filterings, obtain median i '=(gg '+7h "+7j '+m "); Final predicted value i=Clip1 ((i '+512)＞＞10).Wherein gg ' and j ' they are relevant position 1/2nd medians, h " and m " be that relevant position 1/2nd sample medians are amplified 8 times value, the interpolation process of 1/4th sample k is identical with the interpolation process of i.
/ 4th sample f: at first with F2 in vertical direction to hh ', b ", j ' and s " four value filterings, obtain median f '=(hh '+7b "+7j '+s "); Final predicted value f=Clip1 ((f '+512)＞＞10).Wherein hh ' and j ' they are relevant position 1/2nd medians, b " and s " be that relevant position 1/2nd sample medians are amplified 8 times value, the interpolation process of 1/4th sample q is identical with the interpolation process of f.
/ 4th sample e, g, p and r:
e＝(D”+j’+64)＞＞7
g＝(E”+j’+64)＞＞7
p＝(H”+j’+64)＞＞7
r＝(I”+j’+64)＞＞7
D wherein ", E ", H " and I " be that the relevant position integral sample is amplified 64 times value, j ' is relevant position 1/2nd sample medians.
Consult Fig. 2, among this figure the whole location of pixels in the upper left corner of current luminance block E be (x, y), forecast sample matrix predMatrix[x, y] according to table 1 assignment.
Table 1 forecast sample matrix pixel table
| xFracL |
| 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 2 | 2 | 2 | 2 | 3 | 3 | 3 | 3 | |
| | 0 | 1 | 2 | 3 | 0 | 1 | 2 | 3 | 0 | 1 | 2 | 3 | 0 | 1 | 2 | 3 |
| predMatrix [x，y] | D | d | h | n | a | e | I | p | b | f | j | q | c | g | k | R |
Annotate: xFracL equals the horizontal component mvE_x﹠amp of mvE; 3, yFracL equals the vertical component mvE_y﹠amp of mvE; 3
Degree of filling in colors on a sketch sample interpolation uses and the motion vector of corresponding brightness piece is mvE, and the horizontal component of mvE is mvE_x, and vertical component is mvE_y, and corresponding motion vector is mvC.The horizontal component of mvC is mvC_x, and vertical component is mvC_y, and the base unit of mvC is 1/8 sample.
Shown in Fig. 3 chroma sample interpolation graphs, A, B, C, D are by the integral sample value around the interpolated sample, and dx and dy are respectively level and the vertical ranges of forecast sample and A, and dx equals mvC_x﹠amp; 7, dy equals mvC_y﹠amp; 7, the plain predMatrix[x of forecast sample entry of a matrix, y] calculate according to following formula:
predMatrix[x，y]＝((8-dx)×(8-dy)×A+dx×(8-dy)×B+(8dx)×dy×C+dx×dy×D+32)＞＞6
See also Fig. 4, video decoding chip fraction pixel filtering system comprises memory, with the data transmission circuit of a register array, with the low pass filter of four data selectors.Memory belongs to peripheral interface, is provided by the external world.13 integer position pixels of delegation through the filter circuit filtering of band selector, are exported the fraction pixel position through data transmission circuit output 6 * 6 integer pixel positions matrixes of band register array.The data transmission circuit in the native system and the concrete function of low pass filter are as follows:
1, data transmission circuit
Data transmission circuit looks like to be connected with external memory, and the pixel of the whole picture element matrix that will receive from the external memory control unit interface deposits memory in the form of row.From top algorithm as can be seen, insert out whole location of pixels and be (i, j), the point of all fraction pixel positions, need one 6 * 6 whole picture element matrix, the position, the upper left corner of this matrix be (i-2, j-2), position, the lower right corner is (i+3, j+3), so the brightness that will insert out one 8 * 8 divides picture element matrix, need one 13 * 13 the whole picture element matrix of brightness, insert out one 4 * 4 colourity and divide picture element matrix, need one 5 * 5 the whole picture element matrix of colourity.
As shown in Figure 5, in chip, the reference data of whole pixel will be sent by the module of upstream in the memory RAM that is put on the sheet and deposit by row, and there are 13 pixels in delegation, and this can improve the utilization rate of hardware.
This is one 6 * 13 a register array, and register array one end connects data selector, and the whole picture element matrix of being sent by memory is moved in circulation, and the other end connects low pass filter.After coming out, data will enter this array from RAM, the unit of this array is divided into two classes, 6 * 6 top unit are active units, wherein depositing current 6 * 6 required matrix pixel of interpolation that carries out, in order to make 6 * 6 top matrixes is current required data all the time, and the data in this array have three kinds of move modes, move in the circulation, circulation moves down, and moves horizontally.
In i.e. 6 bats of 6 initial clock cycle after the interpolation of one 8 * 8 of startups, 13 pixels of delegation are taken out in every bat from RAM, obtain 6 * 13 initial each pixel of row in the mode that moves horizontally, and at this moment Shang Mian 6 * 6 elements are effective.Array will be done in the circulation and move in ensuing 7 clap, and it is effective to remain 6 * 6 top elements like this.Clap to do once again the 8th and move horizontally, new one-row pixels is come to shift-in, but because the array of this moment moves owing to having done in 7 circulations, new one-row pixels puts in order when coming in must do once and is inverted, 7 pixels of back are moved to the front, and 6 pixels of front are moved to the back.6 * 6 elements above in the array are again effectively after the 8th claps like this, and last image element interpolation that only current active data is second row is needed, and array will be done circulation and move down then, move horizontally after clapping until 7 again.And then do in the circulation and move, every like this bat can both sent 6 * 6 whole pixels.
For chrominance block, can multiplexing this structure, array is also done above-mentioned three kinds of actions, and only the required data of interpolation will be positioned at 2 * 2 elements in the upper left corner.
2, based on the filter circuit of streamline
Low pass filter receives the whole picture element matrix pixel of input, and the integer pixel matrix pixel is carried out 1/2 and 1/4 filtering, obtains the fraction pixel position, and its filtering output end connects the whole picture element matrix in the memory, and the fraction pixel position is inserted in the whole picture element matrix.Filter mainly contains two kinds:
(1) luminance filter.As shown in Figure 6, in order to reduce the length of critical path, one 1/2 luminance filtering is splitted into two clap and finish, multiplication becomes displacement and addition, as a * 5=a＜＜2+a, the structure of 1/4 filtering is similar with it, but the coefficient difference, h represents 1/2 filtering, q represents 1/4 filtering.
Clap outflow one number for each, the present invention adopts the pipeline organization design, for the different pipeline organization of some employing of diverse location.
For the 1st class point, need 1 1/2 filter, drawing a number needs 2 to clap altogether, and for example b only need can draw by 1/2nd picture element interpolations of a sub-level, and i is similar with it, is finished by 1/2 filter h0.Structure as shown in Figure 6.
For the 2nd class point, need 2 1/2 filters and one 1/4 filter, drawing a number needs 4 to clap altogether, two level 1/4 pixels of a, c need to draw two 1/2 pixels by 1/2 interpolation of two sub-levels, this is by 1/2 filter h0, and h1 finishes, and 1/4th filtering that utilize these two 1/2 pixels and two whole pixels to carry out a sub-level then draw, this is finished by 1/4 filter q0, and d, n are similar with it.Structure as shown in Figure 7.
For the 3rd class point, need 5 1/2 filters and (or) a weighted average device, need 4 to clap or 5 bats altogether, 1/2 filtering that j need carry out four sub-levels earlier obtains four 1/2 pixels, this filtering is finished by 1/2 filter h0, h1, h2, h3, carry out once 1/2 vertical filtering with these four pixels again and just can obtain, promptly finished by 1/2 filter h4, e, g, four 1/4 need of p, r are weighted j on average and can get with the whole pixel of corresponding diagonal.Structure as shown in Figure 8.
For the 4th class point, for these two 1/4 pixels of f, q, need carry out 1/2 interpolation of five sub-levels earlier, finish by 1/2 filter h0, h1, h2, h3, h4, utilize these five/2nd pixels to carry out 1/2 vertical interpolation twice then, this step is finished by 1/2 filter h5, h6.Utilize the result of this twice interpolation and two whole pixels to carry out one time 1/4th interpolation again and obtain, finished by 1/4 filter q0, the producing method of i, k is similar with it, only the horizontal filtering and the direction of vertically filtering has been exchanged.Need 7 1/2 filters and one 1/4 filter, need 6 to clap altogether, structure as shown in Figure 9.
In fact, for the required filter of first three class point streamline, all can provide, therefore can finish the computing work of all types point, just need carry out different configurations to streamline according to different positions with the 4th kind of streamline by the streamline of the 4th class point.Whole logics of configuration all embody in 4 selector Muxer, and its structure as shown in figure 10.
The working method of selector is that its working method is described below according to the different flow direction of the different determination datas of dx and dy: the right-hand member of arrow is the input of selector in the following description, and left end then is output.
Selector 0:
h0_i0←A11
h0_i1←A12
h0_i2←A13
h0_i3←A14
h1_i0←A21
h1_i1←A22
h1_i2←A23
h1_i3←A24
h2_i0←A31
h2_i1←A32
h2_i2←A33
h2_i3←A34
h3_i0←A41
h3_i1←A42
h3_i2←A43
h3_i3←A44
If dx equal 1 and dy equal 1, so
A0_i←A22＜＜6
Else if dx equal 1 and dy equal 3, so
A0_i←A23＜＜6
Else if dx equal 3 and dy equal 1, so
A0_i←A323＜＜6
Else if dx equal 3 and dy equal 3, so
A0_i←A333＜＜6
If dx equal 1 and dy equal 0, so
h4_i0←A20；
h4_i1←A21；
h4_i2←A22；
h4_i3←A23；
Else if dx equal 3 and dy equal 0, so
h4_i0←A22
h4_i1←A23
h4_i2←A24
h4_i3←A25
Else if dx equal 2 and dy equal 1, so
h4_i0←A11
h4_i1←A12
h4_i2←A13
h4_i3←A14
Else if dx equal 2 and dy equal 3, so
h4_i0←A51
h4_i1←A52
h4_i2←A53
h4_i3←A54
Selector 1:
h5_i0←h0_O
h5_i1←h1_O
h5_i2←h2_O
h5_i3←h3_O
If dy equals 1, so
h5_i0←h4_O
h5_i1←h0_O
h5_i2←h1_O
h5_i3←h2_O
Otherwise
h5_i0←h1_O
h5_i1←h2_O
h5_i2←h3_O
h5_i3←h4_O
If dx equals 1, so
q0_i0←h4_O
q0_i1←A22′＜＜3
q0_i2←h1_O
q0_i3←h23′＜＜3
Otherwise
q0_i0←A22′＜＜3
q0_i1←h1_O
q0_i2←A23′＜＜3
q0_i3←h4_O
Selector 2:
If dy equals 1, so
q1_i1←h6；
q1_i2←h1′＜＜3；
q1_i3←h5；
q1_i4←h2′＜＜3；
Otherwise
q1_il←h1′＜＜3；
q1_i2←h5；
q1_i3←h2′＜＜3；
q1_i4＝h6；
Selector 3:
If this point is the integer pixel point
result←clip1((h1_O+4)＞＞3)；
If this point is the 1st a class point
result←clip1((q0_O+64)＞＞7)；
If this point is the 2nd a class point
reslut←clip1((h5_O+32)＞＞6)；
If this point is the 3rd a class point
result←clip1((A_O+64)＞＞7)；
If this point is the 4th a class point
result←clip1((q1_O+512)＞＞10)；
(2) chrominance filter.As shown in figure 11.The structure of chrominance filter is single, in order to shorten critical path, a chroma interpolation is divided into 4 bats finishes.
Above embodiment is the unrestricted technical scheme of the present invention in order to explanation only, those of ordinary skill in the art is to be understood that: can make amendment or be equal to replacement the present invention, and not breaking away from any modification or partial replacement of the spirit and scope of the present invention, it all should be encompassed in the middle of the claim scope of the present invention.
Claims (17)
1, video decoding chip fraction pixel filtering system, it is characterized in that, this system comprises memory, the data transmission circuit of band register array, the low pass filter of band data selector, low pass filter is based on the low pass filter of streamline, data transmission circuit is connected with external memory, to deposit register array in the form of going from the whole picture element matrix that the external memory control unit interface receives, the whole location of pixels of being sent by memory is moved in the register array circulation, and the whole pixel of the activity after will circulating is sent into low pass filter, low pass filter carries out 1/2 and 1/4 filtering, data selector is exported the fraction pixel position according to the type of flow of the Position Control data of fraction pixel.
2, video decoding chip fraction pixel filtering system according to claim 1 is characterized in that, described data selector is 4.
3, video decoding chip fraction pixel filtering system according to claim 1 is characterized in that, described whole picture element matrix is the whole picture element matrix of one 13 * 13 brightness.
4, video decoding chip fraction pixel filtering system according to claim 1 is characterized in that, described whole picture element matrix is 5 * 5 the whole picture element matrix of colourity.
5, video decoding chip fraction pixel filtering system according to claim 1 is characterized in that described register array is divided into two parts, and wherein top unit is active unit all the time, is 6 * 13 matrix.
6, video decoding chip fraction pixel filtering system according to claim 1 is characterized in that, the whole pixel of described activity is one 6 * 6 a matrix.
7, video decoding chip fraction pixel filtering system according to claim 1 is characterized in that, described low pass filter is 4 tap F
1(1,5,5 ,-1) filter is predicted 1/2 sample position of nearest pixel samples.
8, video decoding chip fraction pixel filtering system according to claim 1 is characterized in that, described low pass filter is 4 tap F
2(1,7,7,1) filter is predicted 1/4 sample position of nearest pixel samples.
9, video decoding chip fraction pixel filtering method is characterized in that, this method may further comprise the steps at least:
Step 1, data transmission circuit will deposit in the memory with the form of going from the whole pixel that the external memory control interface receives;
Step 2, data selector move into register array with the whole pixel in the memory with matrix form;
The pixel of the whole picture element matrix of being sent by memory is moved in step 3, register array circulation, and will send into low pass filter through the whole pixel of the activity of the mobile whole PEL (picture element) matrix that obtains of circulation;
Step 4, low pass filter carry out 1/2 and 1/4 filtering to the pixel of movable integer pixel matrix, obtain the fraction pixel position;
Step 5, the fraction pixel position is exported.
10, video decoding chip fraction pixel filtering method according to claim 9 is characterized in that, the register array circulation in the described step 3 is moved and be may further comprise the steps:
Step 31, in beginning 6 clock cycle, each cycle is taken out delegation's totally 13 pixels from memory, move into register array in the mode of moving horizontally;
Step 32, next in the 7th cycle, register array will be done in the circulation and move, 6 * 6 pixels that remain above the register array are effective;
Step 33, move into new one-row pixels with the inverted level of putting in order, 7 pixels of back are moved to the front in the 8th cycle;
Step 34, register array are done circulation and are moved down;
Step 35,7 cycles move horizontally later again;
Whether the whole pixel of step 36, judgement input has moved, and moved and then finished to move, otherwise repeating step 1.
11, video decoding chip fraction pixel filtering method according to claim 9 is characterized in that the filtering in the described step 4 specifically may further comprise the steps:
Step 411, with 4 tap F
1(1,5,5 ,-1) filter, 4 tap F
2(1,7,7,1) filter obtains median to 4 nearest on level or vertical direction integral sample filtering;
Step 421, median are through after moving to right, and if resulting value is greater than 255, and then final predicted value is 255, and less than 0, then final predicted value is 0 as if the value that obtains, otherwise final predicted value is the resulting value that moves to right.
12, video decoding chip fraction pixel filtering method according to claim 9 is characterized in that described filtering specifically may further comprise the steps:
Step 421, with 4 tap F
1(1,5,5 ,-1) filter, 4 tap F
2(1,7,7,1) filter carries out 1/2 or 1/4 sample filtering to nearest 4 integers or fractional samples on the tilted direction, obtains median;
Step 422, median are through after moving to right, and if resulting value is greater than 255, and then final predicted value is 255, and less than 0, then final predicted value is 0 as if the value that obtains, otherwise final predicted value is the resulting value that moves to right.
13, video decoding chip fraction pixel filtering method according to claim 9 is characterized in that, the filtering in the described step 4 adopts multiplication to become the method for displacement and addition, divides 2-7 clock cycle to finish.
14, video decoding chip fraction pixel filtering method according to claim 9 is characterized in that, the filtering in the described step 4 is that the clock cycle is 2 with 1 1/2 filter filtering the 1st class point.
15, video decoding chip fraction pixel filtering method according to claim 9 is characterized in that, the filtering in the described step 4 is that the clock cycle is 4 with 2 1/2 filters and 1 1/4 filter filtering the 2nd class point.
16, video decoding chip fraction pixel filtering method according to claim 9 is characterized in that, the filtering in the described step 4 is that the clock cycle is 4 or 5 with 5 1/2 filters and 1 weighted average device filtering the 3rd class point.
17, video decoding chip fraction pixel filtering method according to claim 9 is characterized in that, the filtering in the described step 4 is that the clock cycle is 6 with 7 1/2 filters and 1 1/4 filter filtering the 4th class point.
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| CN100394797C (en) * | 2006-04-13 | 2008-06-11 | 上海交通大学 | VLSI Implementation Method of Luma Interpolator Based on AVS Motion Compensation |
| CN100576918C (en) * | 2007-06-27 | 2009-12-30 | 中国科学院微电子研究所 | Standard interframe prediction pixel generation device for digital audio and video coding and decoding technology |
| CN104811739A (en) * | 2015-04-27 | 2015-07-29 | 重庆邮电大学 | H.264 rapid interpolation method based on movement compensation |
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| US6259734B1 (en) * | 1998-04-03 | 2001-07-10 | Matsushita Electric Industrial Co., Ltd. | Image processing method, image processing apparatus, and data storage media |
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