CN1301473C - Multiprocessor system and method for sharing bootstrap module thereof - Google Patents

Abstract

The present invention relates to a multiprocessor system and a method for the system to share a boot module, particularly to a multi-CPU system with a PCI controller, which belongs to the field of communication. The multiprocessor system comprises a plurality of processors, wherein each processor is provided with a control state register, a dynamic RAM, a static RAM, a serial port, etc. which are matched with the processor, and the processors are connected with each other by a PCI bus so as to share one PCI arbiter; a processor with the boot module serves as a main processor, and other processors serve as the auxiliary processors. When the power of the system is switched on, the main processor reads instructions from the boot module of the main processor, and the auxiliary processors obtain instructions from the RAMs; the main processor restores the auxiliary processors after initializing the auxiliary processors, and the system can normally operate at this time. The present invention has the advantages of simple method, capability of saving boot modules and Ethernet controllers, etc.

Description

Method for sharing boot module in multiprocessor system

technical field

The present invention relates to a kind of multiprocessor (CPU) system and the method for multi-CPU system sharing BOOT FLASH (guide module), relate in particular to the multi-CPU system and The method for multiple CPUs to share the boot module in the system.

Background technique

At present, in order to increase the processing capacity and integration of the single board in the embedded system, multiple sets of CPU systems are often designed on the same single board, and each system comes with a BOOT FLASH. CPLD (Complex Programmable Logic Device, Complex Programmable Logic Device) designs a PCI arbiter by itself, and downloads the version file from the network interface or FLASH. As shown in Figure 1 and Figure 3. Fig. 1 is the hardware block diagram of the multi-CPU system designed by prior art method in the past, two or more sets of CPU systems in the system each have a BOOT FLASH, a PCI arbiter, and at least one Ethernet port. Fig. 3 is the flow chart of power-on software of each CPU system according to the prior art method, each CPU system in the system is independent of each other, after power-on reset, all CPUs all fetch instruction from self BOOT FLASH, finish the initialisation of hardware, and Load the version file through Ethernet or FLASH to complete the system startup.

But for some CPUs (hereinafter referred to as CPUs) with PCI controllers, if according to the design method of this prior art, the cost is obviously increased, and the valuable printed circuit board PCB space has also been taken, so some new ones can be sought for this reason. Bootstrap method to complete the booting of the system. A patent application document "System of connecting multiple processors in cascade" (serial multiprocessor connection system) retrieved from the United States Trademark and Patent Office with an application number of 20020138156 relates to the startup of relevant multi-systems, which utilizes serial bootStrap ( Boot Strap) bus to complete the transmission of the startup codes of each CPU subsystem of the multi-CPU system, but this method needs to design a set of bootStrap bus on the hardware, and the processing of the RAM devices of each CPU system is also more complicated.

Contents of the invention

The purpose of the present invention is to overcome the above-mentioned shortcomings, provide a multi-CPU system solution, and provide a method for multi-CPUs to share a BOOT FLASH for booting.

A kind of multiprocessor system in the present invention comprises a plurality of processors, and each processor has supporting control state register, DRAM, SRAM, serial port etc., and a plurality of processors are connected together through PCI bus, share a PCI Arbiter, one processor with a boot module as the main processor, and other processors as slave processors; the PCI arbiter is implemented by a complex programmable logic device.

The method for multiprocessor sharing boot module among the present invention comprises the following steps: (1) initializing main processor key register; (2) main processor DRAM and SRAM, memory test; (3) code in main processor The segments and data segments are copied to the memory and jump to run there; (4) Main processor interrupt and exception handling initialization; (5) Main processor core initialization; (6) Main processor memory management initialization; (7) Main processor system clock and auxiliary clock initialization; (8) PCI controller and PCI device initialization; (9) main processor IO and file system initialization: (10) load the main processor serial port driver and Ethernet driver; (11) Load the main processor version file: (12) run the main processor version file: it is characterized in that: after the step (8), before the step (9), the following steps are also included;

1.1 Initialize the key registers of the slave processor and its DRAM and SRAM;

1.2 Test slave processor memory;

1.3 Copy the code segment and data segment to the memory of the slave processor system, and set a jump instruction at the first address of the memory;

1.4 Reset the slave processor.

To reset the slave processor in the above method, the slave processor performs the following steps:

2.1 The value of the code segment in the memory;

2.2 Interrupt and exception handling initialization;

2.3 Kernel initialization;

2.4 Memory management initialization;

2.5 System clock and auxiliary clock initialization;

2.6 PCI controller and PCI device initialization;

2.7 IO and file system initialization;

2.8 Load serial driver and/or Ethernet driver;

2.9 Load the version file;

2.10 run version files.

Compared with the prior art, the present invention has a simple method, does not need to add additional equipment on the hardware, and can save BOOT FLASH, CPLD, and perform some processing on the software. The version file can be loaded from the CPU through PCI instead of Ethernet. The bus loads version files from the main CPU, and the slave CPU system can also save the Ethernet controller. If produced in batches, the present invention will bring considerable economic benefits.

Description of drawings

Fig. 1 is a multi-CPU system functional block diagram in the prior art;

Fig. 2 is a functional block diagram of an embodiment of the multi-CPU system of the present invention;

Fig. 3 is the system guidance flowchart designed by prior art method;

Fig. 4 is a flow chart of the method in the present invention;

Fig. 5 is the guide flowchart of the present invention from CPU;

FIG. 6 is a mapping relationship diagram between CPU address and PCI address in the present invention.

Detailed ways

In the system of the present invention, the main CPU has BOOT FLASH, but the slave CPU does not have BOOT FLASH. All CPUs are connected together through the PCI bus and share a PCI arbiter. When the system is powered on, the main CPU fetches instructions from its own BOOT FLASH, and the slave CPU fetches instructions from RAM, but at this time the obtained instructions are illegal and cannot run, but after the master CPU initializes the slave CPU, it will let it Reset, at which point it operates normally.

The core of the present invention is to utilize a kind of soft reset to make the slave CPU fetch instructions from the RAM without performing other operations. Using this feature, after the system is powered on or the main CPU is reset, the main CPU configures the PCI space of the slave CPU, and the various control status registers CSR (Controll Status Registers), DRAM, SRAM, etc. inside the slave CPU system, The PCI controller is mapped to the main CPU, so that the CSR, DRAM (DRAM), and SRAM (SRAM) of the slave CPU become the open resources of the main CPU, and the main CPU can initialize the CSR of the slave CPU, especially the DRAM control register. Initialize, and then copy the code segment and data segment of the instruction to the DRAM of the slave CPU system, and reset the slave CPU after initialization through the master CPU, so that the slave CPU can fetch instructions from its own DRAM and complete the slave CPU. start up.

The present invention will be described in detail below in conjunction with the accompanying drawings.

1, the system structure among the present invention

The principle block diagram of the multiprocessor system in the present invention is shown in Figure 2 (in this embodiment, the system includes a master processor and a slave processor, only two CPUs are shown in the figure). All CPUs are connected through the PCI bus. The CPU1 system is the main CPU system, which is started by the built-in BOOT FLASH. The CPU2 system is a slave system, and some of its resources (DRAM controller, SRAM controller) are initialized by the CPU1 system. The PCI arbitrator in the figure is realized by CPLD to complete the control of the PCI bus.

2, the method among the present invention

The method in the present invention is essentially the software power-on process of the main CPU system, as shown in FIG. 4 . The flow of this method is generally similar to the flow in the prior art (shown in FIG. 3 ). After the system is powered on or reset, all CPUs fetch instructions from BOOT FLASH. Like most processors, the first instruction after the CPU is powered on is a jump instruction, pointing to the starting address of the BOOT FLASH instruction. The program first closes the cache (cache), initializes the DRAM and SRAM controllers, Then open the cache and conduct a comprehensive test on the DRAM. If the DRAM test finds an error, the initialization of the DRAM controller is incorrect, and the initialization parameters need to be adjusted. If the test is successful, copy the code segment and data segment in BOOT FLASH to DRAM and start fetching instructions from DRAM. After fetching instructions from DRAM, complete the initialization of the PCI controller, the address allocation and initialization of the PCI device, the initialization of the operating system kernel, and load the serial port driver and Ethernet driver, and load the version file through the network, FLASH or disk to complete the system. start up.

Compared with the software power-on flow of the prior art, after the initialization of the PCI controller and the PCI equipment, the main CPU will assign addresses to the CSR and the DRAM of the slave CPU, and initialize their configuration space, through the PCI bus, The CSR, DRAM, and SRAM of the slave CPU all become resources accessible to the master CPU; after that, the master CPU initializes the CSR (clock controller) of the slave CPU and conducts a comprehensive test to them. If the test fails, it will The alarm exits, and the designer is required to adjust the initialization parameters. If the test passes, the code segment and data segment in the BOOT FLASH of the main CPU system are copied to a specific location in the DRAM of the slave CPU system; Place a jump instruction at the address, which will make the slave CPU jump to the special address mentioned above to fetch instructions. This jump instruction is the first instruction obtained after the CPU reset; after completing the above work, the master The CPU just writes the above-mentioned special reset instruction to the reset register of the slave CPU, and the slave CPU just can fetch instructions from the DRAM and run normally.

3. In the present invention, the software power-on process of the CPU system

In the present invention, the software flow after the slave CPU is reset by the master CPU is shown in FIG. 5 . After the reset register of the slave CPU receives the reset command of the main CPU, it fetches the instruction from the first address of the DRAM and jumps to the special position mentioned above to fetch the instruction. Since the DRAM controller and cache of the slave CPU have been initialized by the master CPU, they will not be initialized after the slave CPU is reset. In addition, since the master CPU has allocated PCI addresses to each PCI device, the slave CPU will not reassign addresses to each PCI device, but read these addresses from the configuration registers of each PCI device. Other operations are the same as the flow chart shown in Figure 3, mainly completing the initialization of the kernel, loading of the serial port driver and the Ethernet driver. Finally, load the version file to complete the startup of the system.

Loading version files from the CPU system can be done through Ethernet, FLASH or disk, and can also be obtained from the main CPU system through the PCI bus. When obtaining the version file from the master CPU system, you only need to add a PCI communication module in the code of the master and slave CPU systems. The master and slave CPUs exchange information through this PCI communication module to complete the transfer of the version file from the master CPU system to the slave CPU system. send. Using this method saves downloading version files from the CPU system to the Ethernet controller.

4. Master-slave CPU address mapping in the present invention

FIG. 6 is a mapping relationship diagram between master and slave CPU addresses and PCI addresses in the present invention (in the figure, dual CPUs are taken as an example).

In the present invention, the PCI MEM (PCI memory) space and the PCI IO space of the main CPU, the CSR, DRAM, SRAM and Ethernet from the CPU are uniformly allocated on the PCI bus (the PCI IO space is not marked among the figures). The DRAM_BASE (DRAM base address), SRAM_BASE (SRAM base address), and CSR_BASE (CSR base address) of the main CPU are respectively mapped to PCI_DRAM_BASE1, PCI_SRAM_BASE1, and PCI_CSR_BASE1 of the PCI bus, and the DRAM_BASE, SRAM_BASE, and CSR_BASE of the slave CPU are mapped to PCI PCI_DRAM_BASE2, PCI_SRAM_BASE2, PCI_CSR_BASE2 of the bus, their size in the PCI space is determined by the actual DRAM, SRAM and CSR space size DRAM_SIZE, SRAM_SIZE, CSR_SIZE. This mapping is completed when the main CPU initializes the PCI configuration registers of each PCI device. In this way, the access to the PCI_DRAM_BASE1～PCI_DRAM_BASE2 space on the PCI bus is to access the DRAM of the main CPU system, and the access to the PCI_CSR_BASE2～PCI_CSR_BASE2+CSR_SIZE space is to access the CSR space of the slave CPU.

In the CPU, a certain section of physical address space (we call it the CPU address, and the address output by the PCI bus is called the PCI address) is used to access the PCI space, and the operation on this section of address will generate PCI operations. When the main CPU initializes, the PCI address is mapped to a space above the PCI_MEM_BASE of its own CPU address, so that the main CPU operates on a certain space above its own PCI_MEM_BASE, which will be automatically converted into a PCI operation sequence, and the slave can be operated. DRAM, SRAM, CSR of CPU system.

Claims (2)

1, a kind of method for multiprocessor system shared boot module, comprises the following steps: (1) initialization main processor key register; (2) carry out the initialization of dynamic RAM and static RAM controller, main processor dynamic RAM and static RAM Test; (3) copy the code segment and data segment into the memory in the main processor and jump to run in the memory; (4) interrupt and exception handling initialization of the main processor; (5) initialization of the main processor core; ( 6) Main processor memory management initialization; (7) Main processor system clock and auxiliary clock initialization; (8) PCI controller and PCI device initialization; (9) Main processor I/O and file system initialization; (10) Load main processor serial port driver and Ethernet drive; (11) load main processor version file; (12) run main processor version file; It is characterized in that: after described step (8), before step (9), Also includes the following steps: 1.1 Initialize the key registers of the slave processor and its dynamic RAM and static RAM; 1.2 Test slave processor memory; 1.3 Copy the code segment and data segment from the memory of the main processor to the memory of the slave processor system and set a jump instruction at the first address of the memory of the slave processor system, which will make the slave CPU jump to the copy location. address to fetch instructions; 1.4 Reset the slave processor. 2. The method for sharing a boot module in a multiprocessor system according to claim 1, wherein said step 1.4 comprises the following steps: 1.4.1 The value of the code segment in the memory; 1.4.2 Interrupt and exception handling initialization; 1.4.3 Kernel initialization; 1.4.4 Memory management initialization; 1.4.5 System clock and auxiliary clock initialization; 1.4.6 PCI controller and PCI device initialization; 1.4.7 I/O and file system initialization; 1.4.8 Load serial driver and/or Ethernet driver; 1.4.9 Load the version file; 1.4.10 Run version files.

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