CN1300949C - Parallelling receiving method by chip balancer and rake receiver - Google Patents

Abstract

The chip equalizer and rake parallel reception method is applicable to the forward link baseband chip level reception of CDMA spread spectrum communication systems (such as CDMA2000 and WCDMA systems), replacing the function of the existing forward link rake receiver. The present invention combines a chip-level equalizer with a rake receiver to form a parallel receiving method, and uses reconstructed pilot signals to train equalizer coefficients to realize chip-level equalization, and the coefficient iterative equalizer and the main equalizer work in linkage Way. The implementation of the present invention includes the following steps: using the estimation result of the channel estimator to reconstruct the pilot signal through the channel for training the coefficient iterative equalizer, the main equalizer associated with it is used to equalize the input baseband signal, and the output of the main equalizer Combined with the output of the rake receiver in proportion, it is sent to the despreading module. The invention is a CDMA system forward link baseband chip level receiver with superior performance, robust work and low computational complexity.

Description

A Parallel Receiving Method of Chip Equalizer and Rake Receiver

                      

The invention relates to a baseband chip-level signal receiving method at a mobile station side of a code division multiple access (CDMA) system, and belongs to the technical field of baseband signal processing in CDMA cellular mobile communications.

Background technique

In the CDMA system, according to the estimation results of the channel estimator, the Rake receiver uses multiple "fingers" to point to the corresponding strong paths, and combines the outputs of these "fingers" according to the principle of the maximum ratio. despread to produce each symbol. In the current actual system, the Rake receiver has become the main choice of the CDMA forward link receiver because of its simple structure and relatively robust performance.

However, when the Rake receiver extracts the component of a certain path, it regards the interference caused by other paths as white noise. This assumption makes the structure of the Rake receiver inherently deficient, which limits the Rake receiver when multipath interference becomes the main contradiction ( For example, when there are many resolvable paths or high signal-to-noise ratio environment), the performance of the receiver is further improved.

Another design idea of the receiver is to minimize the mean square error between the chip sequence sent to the despreading module and the expected sequence. This design criterion takes into account the multiple access interference caused by noise and multipath. A unit impulse response (FIR) filter is used to implement this criterion, and a (linear minimum mean square error-chip) LMMSE-chip equalizer can be obtained. Both theory and practice prove that the performance of the LMMSE-chip equalizer is better than that of the Rake receiver, especially when the multipath interference is serious and the frame error rate is low.

The implementation of the LMMSE-chip equalizer is to calculate the equalizer coefficients based on the channel estimated by the channel estimator and the joint impulse response of the transmit baseband filter and the receive baseband filter. The joint impulse response can be expressed as a channel convolution matrix h

$h=\left(\begin{array}{cccccc}{h}_0& 0& 0& \&Center\; Dot;\&Center\; Dot;\&Center\; Dot;& 0& 0\\ h_1& h_0& 0& \&Center\; Dot;\&Center\; Dot;\&CenterDot;& 0& 0\\ \&CenterDot;& \&CenterDot;& \&CenterDot;& \&CenterDot;& \&CenterDot;& \&CenterDot;\\ \&CenterDot;& \&Center\; Dot;& \&Center\; Dot;& \&Center\; Dot;& \&Center\; Dot;& \&Center\; Dot;\\ \&Center\; Dot;& \&CenterDot;& \&CenterDot;& \&Center\; Dot;& \&Center\; Dot;& \&Center\; Dot;\\ h_{L-1}& h_{L-2}& \&Center\; Dot;\&Center\; Dot;\&Center\; Dot;& h_0& 0& 0\\ 0& h_{L-1}& h_{L-2}& {\mathrm{<figure-callout\; id="1"\; label="h"\; filenames="C20041004492400141.png,C20041004492400142.png"\; state="\{\{state\}\}">h</figure-callout>}}_1& 0& 0\\ \&Center\; Dot;& \&Center\; Dot;& \&Center\; Dot;& \&Center\; Dot;& \&Center\; Dot;& \&Center\; Dot;\\ \&Center\; Dot;& \&Center\; Dot;& \&Center\; Dot;& \&Center\; Dot;& \&Center\; Dot;& \&Center\; Dot;\\ \&Center\; Dot;& \&CenterDot;& \&CenterDot;& \&CenterDot;& \&CenterDot;& \&CenterDot;\\ 0& 0& 0& 0& h_{L-1}& h_{L-2}\\ 0& 0& 0& 0& 0& h_{L-1}\end{array}\right)$ (Formula 1)

H is a (L-1+M)×M matrix (wherein L is the delay spread of the channel; M is the length of the equalizer).

The chip equalizer coefficients obtained based on the LMMSE criterion are:

$g_{\mathrm{MMSE}}={(h^{h}h+\frac{1}{\mathrm{SNR}}I)}^{-1}{h}^h{\mathrm{\&delta;}}_{\mathrm{D.}}$ (Formula 2)

where δ _D is [00…1 _D+1 0…0] ^T , D is the delay parameter, $\mathrm{SNR}=\frac{{\mathrm{\&sigma;}}_{\mathrm{the\; s}}^2}{{\mathrm{\&sigma;}}_{\mathrm{no}}^2}$ is the signal-to-noise ratio, and I is the M×M unit matrix. where (·) ^H represents Hermite transposition. The above formula can be regarded as the result of comprehensively considering the influence of multipath interference and noise on the signal. When the signal-to-noise ratio SNR>>1, the LMMSE equalizer degenerates into a zero-forcing equalizer; when the SNR<<1, the LMMSE equalizer degenerates into Rake receiver.

Since the complexity of the matrix inversion operation is difficult to realize in engineering when the matrix is large, an iterative method is generally used to rewrite the matrix inversion operation in Formula 2 as an adaptive process:

$g(\mathrm{no}+1)=g\left(\mathrm{no}\right)-\mathrm{\&mu;}[(h^{h}h+\frac{1}{\mathrm{SNR}}I)g\left(\mathrm{no}\right)-h^h{\mathrm{\&delta;}}_{\mathrm{D.}}]$ (Formula 3)

The LMMSE adaptive chip equalizer has better performance than Rake, and the amount of calculation is also much lower than that of the chip equalizer using the traditional matrix inversion algorithm. However, the following problems are still involved: the amount of multiplication between matrices and matrices and between matrices and vectors is still very large. Even if the FFT method is used to calculate matrix multiplication, the equalizer’s complex multiplication and complex addition within a unit chip time are as high as M Level ² , the receiver structure is also very complex; when M<L, the performance of the receiver will be degraded, especially when there is a path with strong power at the time delay spread greater than M, this phenomenon is more obvious; in addition, LMMSE adaptive The chip equalizer requires the channel estimator to have high precision at different vehicle speeds, which increases the design difficulty and implementation cost of the channel estimator.

Contents of the invention

Technical problem: the purpose of the present invention is to provide a method for parallel reception of a Chepp equalizer and a rake receiver, so as to solve the problem that the performance of the existing rake receiver is poor when the multipath interference is serious or the frame error rate is required to be very low. And the problem that the computational complexity of the existing LMMSE adaptive chip equalizer is still relatively high; it makes the system receiving performance more robust in the environment with large channel delay expansion.

Technical solution: a method for parallel reception of a Chip equalizer and a Rake receiver, characterized in that: the baseband input method of the mobile station side baseband reception of a code division multiple access system is formed by using a Chip equalizer and a Rake receiver in parallel. The signal is processed, that is: the output of the baseband input signal is divided into two channels, one is connected to the channel estimator, the other is connected to the input of the equalizer and the Rake receiver, and the output of the equalizer and the Rake receiver is connected to the adder. The input terminal and the output terminal of the adder are connected to the despreading module; among them, the chip equalizer is composed of two parts, the coefficient iterative equalizer and the main equalizer linked by the coefficients, and is reconstructed by using the original channel estimator estimation result of the rake receiver The channel-passed pilot sequence is used to train the coefficient iterative equalizer, the coefficients of the main equalizer are consistent with the coefficient iterative equalizer, and the main equalizer equalizes the baseband input signal.

The coefficient iterative equalizer is implemented with the LMS algorithm, and it always works in the training mode by using the reconstructed pilot signal. Determine the combination ratio of Chip equalizer and Rake according to the estimated mean square error obtained by the coefficient iterative equalizer; that is, the weighting coefficient output by Rake always takes 1, and the weighting coefficient output by Chip equalizer takes 1-mean square error Estimated value, when the 1-mean square error estimated value is less than 0, the weighting coefficient output by the chip equalizer is 0.

The method of processing the baseband input signal is as follows: the baseband input signal is divided into two channels, the first channel is sent to the channel estimator, and the channel estimator estimates the unit impulse response of the current channel for pilot regeneration; the other channel baseband input After the signal subtracts the local pilot signal reconstructed by pilot frequency regeneration, the baseband input signal after pilot interference cancellation is obtained. The signal is divided into two channels, the first channel is sent to Rake and the other channel is sent to the main equalizer The local pilot signal reconstructed by pilot frequency regeneration is sent to the coefficient iterative equalizer at the same time, and the coefficient iterative equalizer adjusts the coefficients accordingly, and sends the obtained equalizer coefficients to the main equalizer; Rake and the main equalizer The output results are combined and then despread to generate symbol-level output.

The main innovation of the present invention lies in the method of chip equalizer and Rake receiving in parallel and the method of reconstructing the chip equalizer trained by the pilot signal. In the chip equalizer and Rake parallel receiving method, the outputs of the chip equalizer and RAKE are combined and then sent to the despreading module.

The design idea of the chip equalizer part is as follows: Considering that the CDMA system isolates the pilot channel and other channels with an orthogonal Walsh function and then mixes them together for transmission, if the pilot channel can be "cleanly" extracted, then the The design of the equalizer will be greatly simplified. Based on this idea, the receiver structure shown in Figure 3 can be obtained, which is referred to as Method 1:

In this structure, the output expectation of the coefficient iterative equalizer is known, so the coefficient iterative equalizer has been working in the training state, which can be realized by a simple LMS (Least Mean Square) algorithm without matrix operation. Since there is no noise, the coefficient iterative equalizer is essentially a zero-forcing equalizer. The main equalizer is just an FIR filter whose coefficients change synchronously with the coefficient iterative equalizer. Rake receivers can share the delay line of this FIR filter with the main equalizer. The pilot signal reconstructed in the process is also used for pilot interference cancellation. The closed-loop adaptive structure of the main equalizer will also achieve better performance and stronger robustness than the open-loop structure of the LMMSE (LinearMinimum Mean Square Error) adaptive equalizer. The inventor named the receiver structure as a parallel receiving method of Chip equalizer and Rake. The receiving method greatly reduces the calculation amount of complex multiplication and complex addition within a unit chip time to an order of magnitude equivalent to the length of the equalizer, and is more concise than the LMMSE adaptive chip equalizer. In addition, the mean square error output by the coefficient iterative equalizer will also be used to control the combination ratio of the main equalizer and the Rake receiver, and the equalizer will be turned off when the channel changes too fast or some multipath distribution causes the equalizer to equalize poorly. , using only the output of the Rake receiver.

The result of the channel estimator in Fig. 3 must fully reflect the joint impulse response of the channel and the baseband filter, and it is difficult to ensure sufficient estimation accuracy in the position where there is no path in the channel due to the low signal-to-noise ratio. If the receiver structure is slightly deformed, the second chip equalizer and Rake parallel receiver structure can be obtained, which is referred to as the second method.

In the second method, the channel estimator adopts the same path selection scheme as the Rake receiver, that is, the time delay between paths must not be less than 1 chip. The pilot baseband filter is the convolution of the transmitting baseband filter and the receiving baseband filter, and is used to assist the channel estimator to reconstruct a pilot signal close to the actual situation.

Considering that the introduction of the pilot baseband filter increases the complexity of the system, if only the main lobe of the baseband filter is reserved and its side lobes are deleted, the second simplified method can be obtained. Since the maximum value of the baseband filter is set to 1, and the symmetry of the baseband filter is utilized, the number of complex multiplications of the simplified baseband filter at each sampling point is only 1 when oversampling is 2 times.

Since the above-mentioned method 1 can be obtained by canceling the pilot baseband filter and changing the channel estimator routing scheme in the method 2, only the implementation steps of the method 2 are described here, as follows:

Step 1: Use the channel estimator to estimate the unit impulse response of the current channel: the resolution of the channel estimator is 1/4 chip or 1/8 chip, and the channel estimation method using sliding window averaging or sliding window IIR filtering is used. When selecting paths, use The path selection scheme of the Rake receiver, that is, select the 3~4 paths with the strongest power under the premise that the distance between the paths is not less than 1 chip;

Step 2: Use pilot regeneration to reconstruct the pilot signal: Use the PN code offset and other information to generate the local PN sequence, use the tapped delay line model to simulate the multipath channel environment according to the strong path information obtained by the channel estimator, and repeat Construct the pilot signal through the multipath channel, and then make it pass through the pilot baseband filter to approximate the pilot part in the received signal;

Step 3: Subtract the reconstructed pilot signal from the received signal to eliminate the influence of the pilot part in the received signal on the performance of the receiver;

Step 4: Use the reconstructed pilot signal and use the LMS algorithm to train the coefficient iterative equalizer, and its output is expected to be the reconstructed local PN sequence; the error obtained by the LMS algorithm is sent to the mean square error estimate to obtain the estimate of the mean square error value, the equalizer determines the combination ratio of the main equalizer in the adder according to the estimated value;

Step 5: The main equalizer equalizes the received signal after pilot interference cancellation, the coefficient preservation of the main equalizer is linked with the coefficient iterative equalizer, and the delay line of the main equalizer is used to form a Rake receiver, and the output of the main equalizer Combined with the output of the Rake receiver proportionally.

The CDMA system forward link chip-level receiver constituted by the present invention is composed of a channel estimator, a PN sequence generation module, a tapped delay line model, a pilot baseband filter, a coefficient iterative equalizer, a main equalizer, Rake, etc. Partial composition. The specific functions of each part are described as follows:

Channel estimator: This part is basically the same as the channel estimator of the existing Rake receiver, with a minimum resolution of 1/4 chip. It is responsible for estimating the maximum power on the premise that the delay between paths is not less than 1 chip. Strong 4-path delay, amplitude and phase information for master-slave equalizer and rake receiver.

PN sequence generation module: This part serially generates local I and Q two-way PN sequences for use by subsequent modules according to the PN code offset and other information of the local area. The generated rate is synchronized with the chip rate, and the amplitude of the output data is 1.

Tapped delay line model: This part is used to reconstruct the pilot signal through the multipath channel in the form of FIR filter according to the estimation result of the channel estimator. The minimum resolution of the tapped delay line model is 1/4 chip, which is the same as that of the channel estimator.

Pilot baseband filter: This filter is formed after the convolution and truncation of the transmitting baseband filter and the receiving baseband filter, and is used to make the reconstructed pilot signal closer to the pilot part in the received signal. Since the equivalent channel composed of the transmitting baseband filter, the multipath channel and the receiving baseband filter is a linear system, switching the transmitting baseband filter and the multipath channel does not affect the unit impulse response of the equivalent channel.

Equalizer expectation adjustment: used to weight the amplitude of the local PN sequence according to the received signal amplitude estimated by the channel estimator. The weighting coefficient is larger when the amplitude of the received signal is larger, and the weighting coefficient is smaller when the amplitude of the received signal is smaller. Taking the weighted local PN sequence as the output expectation of the main equalizer is beneficial to improve the decoding performance of the channel decoder in the fading channel environment.

Coefficient iterative equalizer: The coefficient iterative equalizer adopts the complex LMS algorithm of integer or fractional intervals (the algorithm is completed by adjusting the equalizer coefficients), and selects an appropriate FIR filter length. The coefficient iterative equalizer always works in the training mode, and the output of the coefficient iterative equalizer is expected to be an amplitude-weighted local PN sequence, which is generated by the PN sequence and adjusted by the equalizer expectation. Since the training sequence has no noise, the coefficient iterative equalizer is essentially a zero-forcing equalizer working in the training mode.

Main Equalizer: The main equalizer is used to equalize the baseband signal after pilot interference cancellation. The equalizer is only an FIR filter whose coefficients are linked with the coefficient iterative equalizer, and its sampling rate is consistent with that of the coefficient iterative equalizer.

Rake: The structure of the Rake receiver is basically the same as that of the existing Rake receiver, but does not include the despreading part. The Rake receiver and the main EQ share a delay line with several "fingers".

Mean square error estimator: The equalization error can be obtained by subtracting the output expectation and the actual output of the coefficient iterative equalizer. The mean square error estimator squares the error and sends it to the low-pass filter to obtain the estimated value of the mean square error. This estimated value is used to evaluate the working status of the current equalizer, so that when the channel changes too fast or some multipath distribution causes the equalizer to equalize poorly, the equalizer can be turned off through the equalizer enable control and the multiplier. Only Rake Receiver output.

Beneficial effects: the beneficial effects of the present invention are mainly reflected in the following aspects:

1) Due to the comprehensive consideration of multipath interference and the influence of noise on the signal, compared with the existing Rake receiver, the performance is improved, especially when the multipath interference is serious or the frame error rate is required to be low.

2) Compared with the existing LMMSE adaptive chip equalizer, it is more robust, and the performance will not be significantly degraded when there is a multipath with a delay greater than the length of the equalizer or the position of the path changes.

3) Compared with the existing LMMSE adaptive chip equalizer, the computational complexity is greatly reduced. The calculation amount of complex number addition and complex number multiplication is reduced from the order of magnitude of the square of the equalizer length to the order of magnitude linearly related to the equalizer length.

Description of drawings

Fig. 1 is a signal processing flowchart of the present invention.

Fig. 2 is a schematic diagram of the parallel method of Chip equalizer and Rake.

Fig. 3 is a schematic diagram of the first chip equalizer and Rake parallel receiver (method 1).

Fig. 4 is a schematic diagram of a chip equalizer and a Rake parallel receiver implementation device.

Fig. 5 is the performance comparison of different receivers when the two-path model (L<M) is used. Among them, L is the channel delay extension, M is the length of the equalizer; in the figure, the abscissa Ior/Ioc is the ratio of the total power of the received signal to the total power of the noise, the unit is dB, and the ordinate SER is the symbol error rate, that is The proportion of wrong symbols in the output of the despreading module to the total number of symbols.

Figure 6: Performance comparison of different receivers in two-path model (L>M).

The above figure has: baseband input signal 1, channel estimator 2, chip equalizer 3, pilot regeneration 31, subtractor 32, coefficient iterative equalizer 33, main equalizer 34, PN sequence generation 35, tapped delay line Model 36, pilot baseband filter 37, multiplier 38, equalizer expectation adjustment 39, subtractor 310, equalizer coefficient adjustment 311, mean square error estimation 312, equalizer enabling control 313, multiplier 314, coefficient iterative equalization Auxiliary controller 331, rake receiver 4, adder 5, despreading module 6.

Detailed ways

Fig. 1 is a signal processing flowchart of the present invention. Wherein baseband input signal 1 is the baseband signal processed through analog/digital (A/D) conversion and receiving baseband filter; Channel estimator 2 is the CDMA mobile station side channel estimator utilizing matched filtering or sliding correlation method to realize; Despreading Module 6 is the same as the existing CDMA mobile station side despreading module, and completes the functions of descrambling and despreading, and its output is a symbol level signal.

FIG. 2 is a schematic diagram of the parallel method of the chip equalizer and the rake receiver 4 . Wherein, equalizer 3 is an integral part of the present invention, and its specific implementation method is referring to Fig. 3～Fig. Including its despreading part); adder 5 is the merging part in the equalizer and rake receiver parallel method, and this module finishes the function to the output weighting of equalizer simultaneously, and its specific implementation method is referring to Fig. 4.

Fig. 3 is the first chip equalizer and rake receiver (method 1). Wherein, pilot frequency regeneration 31, subtractor 32, coefficient iterative equalizer 33 and main equalizer 34 constitute one of the realization methods of equalizer 3 in Fig. 2 of the present invention together; Pilot frequency regeneration 31 utilizes the result regeneration that channel estimator draws Local pilot signal is used for pilot interference cancellation and training coefficient iterative equalizer; Subtractor 32 subtracts the signal of pilot frequency regeneration 31 from baseband input signal 1 as output; Coefficient iteration equalizer 33 utilizes the pilot frequency regeneration 31 output of pilot frequency Frequency signal training equalizer, utilize corresponding algorithm self-adaptive adjustment equalizer coefficient; Main equalizer 34 is used for channel equalization, its coefficient and the coefficient of coefficient iterative equalizer keep synchronous; The concrete of coefficient iterative equalizer 33 and master equalizer For the implementation method, refer to Figure 4 and the detailed description in the patent specification.

Fig. 4 is a schematic diagram of a chip equalizer and a rake receiver parallel receiver implementation diagram. Wherein, PN sequence produces 35, tapped delay line model 36 and pilot frequency baseband filter 37 jointly constitute the realization device of pilot frequency regeneration 31 parts in method two; Multiplier 38, equalizer expectation adjustment 39, subtractor 310, equalizer Coefficient adjustment 311, mean square error estimation 312, equalizer enabling control 313, and multiplier 314 together constitute coefficient iterative equalizer auxiliary control 331, which is used to control the working state of coefficient iterative equalizer and auxiliary processing of the output signal of the main equalizer .

The method for parallel reception of the chip equalizer and the rake receiver of the present invention uses the parallel connection of the chip equalizer and the rake receiver to form a code division multiple access system The method for receiving the baseband at the mobile station side processes the baseband input signal, that is: The output end of the input signal 1 is divided into two paths, one path is connected to the channel estimator 2, the other path is connected to the input end of the equalizer 3 and the rake receiver 4, and the output ends of the equalizer 3 and the rake receiver 4 are connected to the adder 5 The input terminal and the output terminal of the adder 5 are connected to the despreading module 6; wherein, the chip equalizer is composed of two parts, a coefficient iterative equalizer and a main equalizer linked by coefficients, and utilizes the original channel estimator estimation result of the rake receiver The reconstructed pilot sequence through the channel is used to train the coefficient iterative equalizer, the coefficients of the main equalizer are consistent with the coefficient iterative equalizer, and the main equalizer equalizes the baseband input signal.

The coefficient iterative equalizer is implemented with the LMS algorithm, and it always works in the training mode by using the reconstructed pilot signal. According to the estimated mean square error obtained by the coefficient iterative equalizer, determine the combination ratio of the Chip equalizer and the Rake; that is, the weight coefficient output by the Rake receiver is always 1, and the weight coefficient output by the Chip equalizer is 1- Estimated value of mean square error. When the estimated value of 1-mean square error is less than 0, the weighting coefficient output by the chip equalizer is 0. The method for processing the baseband input signal is: the baseband input signal is divided into two paths, the first path is sent to the channel estimator 2, and the unit impulse response of the current channel is estimated by the channel estimator 2 for use by the pilot regeneration 31; After subtracting the local pilot signal reconstructed by pilot regeneration 31 from one baseband input signal, the baseband input signal after pilot interference cancellation is obtained. The signal is divided into two channels, and the first channel is sent to the Rake receiver 4 The other channel is sent to the main equalizer 34; the local pilot signal reconstructed by the pilot regeneration 31 is sent to the coefficient iterative equalizer 33 at the same time, and the coefficient iterative equalizer 33 adjusts the coefficients accordingly, and the obtained equalizer The coefficients are sent to the main equalizer 34; the output results of the rake receiver 4 and the main equalizer 34 are combined and despread to generate a symbol-level output.

Taking the CDMA2000 platform as an example, the method 2 of the present invention and the performance comparison of two receivers independently using the LMMSE adaptive chip equalizer and the RAKE receiver are given below.

The signal processing process of the present invention is as follows:

Step 1: Use the channel estimator 2 to estimate the unit impulse response of the current channel. The resolution of the channel estimator is 1/4 chip, and the scheme is an adaptive sliding window IIR filter with vehicle speed estimation. When selecting the path, use the path selection scheme of the rake receiver, that is, select the 4 paths with the strongest power under the premise that the distance between the paths is not less than 1chip.

Step 2: Reconstruct the pilot signal with pilot regeneration 2. Use the PN code offset and other information to generate the local PN sequence, according to the strong path information obtained by the channel estimator, use the tapped delay line model to simulate the multipath channel environment, reconstruct the pilot signal through the multipath channel, and then make it Pass the pilot frequency baseband filter to approximate the pilot frequency part in the received signal.

Step 3: Subtract the reconstructed pilot signal from the received signal (subtractor 32), so as to eliminate the influence of the pilot part in the received signal on the performance of the receiver.

Step 4: Use the reconstructed pilot signal and use the LMS algorithm (implemented by the equalizer coefficient adjustment 311) to train the coefficient iterative equalizer 33, whose output is expected to be a local PN sequence. The error (subtractor 310) obtained by the LMS algorithm is sent to the mean square error estimation 312 to obtain the estimated value of the mean square error, and the equalizer enables the control 313 and the multiplier 314 to determine the main equalizer 34 in the adder 5 according to the estimated value. The combined ratio in .

Step 5: The main equalizer 34 equalizes the received signal after pilot interference cancellation, the main equalizer coefficient is maintained and the coefficient iterative equalizer 33 is linked, and the delay line of the main equalizer is used to form a Rake receiver 4 receiver, and the The output of the master equalizer and the output of the rake receiver are combined in appropriate proportions.

The simulation conditions are as follows:

1) Sampling rate of each chip: 4 times sampling of Rake receiver; method 2 of the present invention and LMMSE adaptive chip equalizer are single sampling. The FIR length of the equalizer is 32.

2) The data rate is 153.6kbps, and the spreading ratio is 4; the channel coding adopts a convolutional code with a code rate of 1/4.

3) The total transmission power of the base station is 0dB: among them, the pilot channel is -6dB, the synchronization channel is -9dB, the paging channel is -9dB, and the traffic channel is -7dB. Influence.

4) The multi-path channel is generated by a tapped delay line model with a resolution of 1/4 chip, the fading adopts Jake's model, and the carrier frequency is 2GHz.

5) The simulation frame number of each point in the figure is 10000 frames, or the error frame reaches 500 frames.

Since the symbol error rate performance of different receivers measured in the AWGN environment is very close, the performance curves are omitted here. Figure 5 shows the performance of two equal-intensity path models when the vehicle speed is 3km/h. The time delays of these two paths are 0chip and 2chip respectively. Increasing the delay spread between these two paths beyond the equalizer length yields the result shown in Figure 6. (The prefix PC indicates that the receiver uses pilot interference cancellation technology)

It can be seen from Fig. 5 and Fig. 6 that when the channel delay spread is smaller than the length of the equalizer, there is no obvious difference in performance between the present invention and the LMMSE equalizer, both of which are better than the traditional rake receiver. In addition, when the channel delay extension exceeds the length of the equalizer, the performance of the LMMSE equalizer is seriously degraded, but the present invention can still ensure that the performance of the receiver is not lower than that of the rake receiver.

Claims (4)

1, the method for a kind of chip balancer and Rake receiver parallel receive, it is characterized in that: the method that adopts chip balancer formation in parallel with Rake receiver code division multiple access system mobile station side base band to receive is handled base-band input signal, that is: the output of base-band input signal (1) divides two-way, one the tunnel connects channel estimator (2), another road connects the input of chip balancer (3) and Rake receiver (4), the input of the output termination adder (5) of chip balancer (3) and Rake receiver (4), the output termination despreading module (6) of adder (5); Wherein, chip balancer is made of coefficient iteration equalizing device and master equalizer two parts of coefficient interlock, utilize the original channel estimator of Rake receiver (2) estimated result reconstruct to be used to train coefficient iteration equalizing device through the pilot frequency sequence of channel, the coefficient of master equalizer and coefficient iteration equalizing device are consistent, master equalizer equalization base band input signal.

2, the method for chip balancer as claimed in claim 1 and Rake receiver parallel receive is characterized in that: coefficient iteration equalizing device is realized with the LMS algorithm, and is utilized the pilot signal of reconstruct to work in training method all the time.

3, the method for chip balancer as claimed in claim 1 and Rake receiver parallel receive is characterized in that: the mean square error estimated value that draws according to coefficient iteration equalizing device is determined the merging ratio of chip balancer and Rake receiver; That is: the weight coefficient of Rake receiver output gets 1 all the time, and the weight coefficient of chip balancer output is got 1-mean square error estimated value, when 1-mean square error estimated value less than 0 the time, the weight coefficient of chip balancer output gets 0.

4, the method for chip balancer as claimed in claim 1 and Rake receiver parallel receive, it is characterized in that: the method that base-band input signal is handled is: base-band input signal is divided into two-way, the first via is admitted to channel estimator (2), and the unit impulse response that is estimated current channel by channel estimator (2) is used for pilot tone regeneration (31); Another roadbed tape input signal deducts the base-band input signal that draws after the local pilot signal that pilot tone regeneration (31) reconstructs through pilot cancellation, this signal is divided into two-way again, and the first via is admitted to another road of Rake receiver (4) and is admitted to master equalizer (34); The local pilot signal that pilot tone regeneration (31) reconstructs is admitted to coefficient iteration equalizing device (33) simultaneously, and coefficient iteration equalizing device (33) is adjusted coefficient in view of the above, and the equalizer coefficients that draws is sent into master equalizer (34); Carry out despreading after the output result of Rake receiver (4) and master equalizer (34) merges and produce symbol level output.

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