CN1300753C - Dynamic matrix type display device - Google Patents

Abstract

The present invention provides a dynamic matrix type display device which is provided with auxiliary capacitor electrodes in pixel regions of pixel electrodes and an auxiliary capacitor, wherein the auxiliary capacitor is composed of a first auxiliary capacitor line and a second auxiliary capacitor line, and is arranged corresponding to a plurality of pixel electrodes. By exchanging that an element applies each frame period for the pixel electrodes, any voltage mode of first video voltage of which the polarity can generate reverse rotation and second video voltage of which the polarity is opposite to the first video voltage is used for displaying. In this way, the dot inversion drive caused by the auxiliary capacitance lines can be implemented, and display capability with low power consumption and high display quality can be implemented.

Description

Dynamic Matrix Display Device

technical field

The invention relates to a dynamic matrix type display device.

technical background

In a dynamic matrix display device that transmits image signals to independent pixel electrodes through switching elements such as thin film transistors (TFT: Thin Film Transistor), by means of an AC driving method that applies an alternating potential to the counter electrode and the auxiliary capacitor, While preventing liquid crystal from deteriorating, it is also possible to reduce the potential difference between the positive and negative polarity of the video signal input to the drain driver, and realize low power consumption by reducing the current and voltage of the drain driver.

However, in the horizontal inversion counter-electrode AC driving method in which the polarity of the video signal supplied to each drain line is inverted every horizontal period, the counter electrode and all auxiliary capacitor lines are The polarity of the voltage is reversed, so the capacitive load of the counter electrode and all auxiliary capacitor lines and the resulting power consumption are still very large.

Therefore, in order to achieve lower power consumption, Japanese Patent Application Laid-Open No. 12-81606 discloses a driving method (hereinafter referred to as "SC driving") in which the voltage polarity of the auxiliary capacitor is reversed. In this way, the opposite electrode voltage is set to a certain value voltage, which can further reduce power consumption, and at the same time reduce the potential difference between the positive and negative polarities of the video signal, and reduce the current and voltage of the drain driver. The following will describe the dynamic matrix liquid crystal display device driven by SC.

FIG. 11 shows an equivalent circuit diagram of a display panel of a dynamic matrix liquid crystal display device using SC driving. This circuit is provided with several drain lines 105 in the vertical direction, and several gate lines 107 in the horizontal direction, and a switching element TFT 109 is provided at their intersections. The gate of the TFT 109 is connected to the gate line 107 , and the drain thereof is connected to the drain line 105 . The source of the TFT 109 is connected to one side electrode of the liquid crystal capacitor 112 . The other electrode of the liquid crystal capacitor 112 is the counter electrode 111, which integrates the substrate on which the TFT 109 is provided and the opposite substrate sandwiching the liquid crystal.

In addition, the source of the TFT 109 is connected to a capacitor electrode on one side of the auxiliary capacitor 110 . The other electrode of the storage capacitor 110 is connected to the storage capacitor line 108 . The auxiliary capacitor line 108 is parallel to the gate line 107 and communicates with several auxiliary capacitors 110 in the row direction.

Fig. 12 shows the signal waveform diagram for driving a display panel focusing on a single pixel, in which the gate voltage V _G , pixel voltage V _P , source voltage V _S , video signal voltage V _D , auxiliary capacitor voltage V _SC and the counter electrode voltage V _COM . The gate voltage V _G has an ON period in each frame period.

When the gate is turned on, the gate voltage V _G applied to the gate line 107 becomes a high (hereinafter referred to as “High”) level. During this period, the TFT 109 is in the conduction state, and the drain and the source are in the conduction state, and the source voltage _VS will become the same as the video signal voltage _VD along with the video signal voltage VD applied to the drain line 105. _D the same level. Therefore, the source voltage V _S is applied to the capacitor electrodes on one side of the liquid crystal capacitor 112 and the auxiliary capacitor 110 . When the gate is cut off (OFF), the gate voltage V _G will become a low (hereinafter referred to as "Low") level, and the TFT 109 is in a cut-off state, thereby determining the source voltage V _S . At the same time, with As the gate voltage V _G decreases, the level decreases only by ΔV _S to become V _PL .

The counter electrode voltage V _COM is a constant value voltage, which is lower than the center level V _C of the video signal voltage V _D by reducing the source voltage V _S by about ΔV _S in advance.

After the gate voltage V _G applied to the corresponding gate line 107 drops, the storage capacitor voltage V _SC is applied to each storage capacitor line 108 to invert the level. The auxiliary capacitor voltage V _SC will be reversed at the two high and low levels of V _SCH and V _SCL . For example, when the source voltage V _S is in a period of positive polarity higher than the opposite electrode voltage V _COM , when the gate voltage V _G drops, the source voltage V _S will rise from the low level V _SCL to the high level V _SCH . Therefore, when the gate voltage V _G decreases, the pixel voltage V _P obtained by determining the source voltage V _S will be affected by the increase of the auxiliary capacitor voltage V _SC through the auxiliary capacitor 110 , and only increase by ΔV _P . The pixel voltage V _P at this time is held during the gate non-conduction (OFF) period, that is, within one frame.

In this way, charge redistribution occurs between the liquid crystal capacitor 112 and the storage capacitor 110 due to the increase of the storage capacitor voltage V _SC , and the pixel voltage V _P increases only by ΔV _P =V _PH −V _PL . On the contrary, during the negative polarity period when the source voltage V _S is lower than the counter electrode voltage V _COM , the pixel voltage V _P only drops by ΔV _P because the auxiliary capacitor voltage V _SC drops from a positive value to a negative value. As a result, the amplitude of the pixel voltage _VP becomes larger, and the voltage applied to the liquid crystal capacitor 112 can be increased.

That is, by inverting the storage capacitor voltage V _SC between two levels, even if the counter electrode voltage V _COM is a direct current voltage, the amplitude of the video signal voltage V _D can be reduced, and sufficient voltage can be applied to the liquid crystal capacitor 112. Voltage.

Generally speaking, since the auxiliary capacitor 110 is much larger than the liquid crystal capacitor 112 , the change degree ΔV _P of the pixel voltage can be controlled by the variation V(V _SCH −V _SCL ) of the auxiliary capacitor voltage in one row. Therefore, a larger voltage can be applied to the liquid crystal capacitor 112 by changing the storage capacitor voltage of the storage capacitor line 108 . That is, by changing the storage capacitor voltage, the amplitude of the video signal voltage V _D can be reduced.

However, at present, the following driving method is generally used, that is, with the increase of pixels, several drain lines 105 are turned on at the same time, and the video signal voltage V _D is simultaneously applied to several liquid crystal capacitors 112 and auxiliary capacitors 110. drive method. In this way, the time for the drain line 105 to apply the video signal voltage V _D to the liquid crystal capacitor 112 and the auxiliary capacitor 110 can be sufficiently ensured.

Especially when driving a large or high-definition display panel by the dot sequential method, dozens of drain lines 105 will be turned on at the same time, and the video signal voltage V _D will be applied to dozens of liquid crystal capacitors 112 and auxiliary capacitors 110 at the same time. Thus, when dozens of drain lines 105 become conductive at the same time, a large amount of capacitive coupling will occur at the overlapping portion of the drain lines 105 in the conductive state and the auxiliary capacitor lines 108 . That is, the voltage of the storage capacitor line 108 or the gate line 107 is finally affected by the voltage of the drain line 105 and fluctuates. Due to such a voltage change, the drain line 105 that is in the on state at the same time causes image unevenness on a unit basis.

Contents of the invention

In the present invention, voltages with different polarities can be applied to each of the adjacent single or several pixel electrodes, that is, so-called dot inversion can be performed.

The present invention has several first and second auxiliary capacitance lines corresponding to each row of pixel electrodes and extending along the row direction, corresponding to the first and second auxiliary capacitance lines, and the columns of the above-mentioned pixel electrodes are arranged alternately With the auxiliary capacitor. This makes it possible to feed signals with different polarities to the respective auxiliary capacitor lines. Therefore, by using the first and second storage capacitor lines, voltages with different polarities can be applied to adjacent pixels, that is, so-called dot inversion driving can be realized.

Furthermore, it is preferable to supply the first and second storage capacitor voltages which change in opposite phases to each other while the switching element is in the off state, to the first and second storage capacitor lines. In this way, it is possible to reduce the amplitude of the video signal voltage and apply a sufficient voltage to the pixel electrode while realizing the dot inversion driving by the above-mentioned auxiliary capacitor line.

Description of drawings

FIG. 1 is a plan view of a display panel of a dynamic matrix type display device.

2 is a plan view of a display panel according to a first embodiment of the present invention.

3 is an equivalent circuit diagram of the display panel according to the first embodiment of the present invention.

4 is a timing chart showing the relationship between signals in the display panel according to the first embodiment of the present invention.

5( a ) and FIG. 5( b ) are signal waveform diagrams showing a method of driving the display device according to the first embodiment of the present invention.

6 is a plan view of a display panel according to a second embodiment of the present invention.

7 is an equivalent circuit diagram of a display panel according to a second embodiment of the present invention.

8 is a plan view of a display panel according to a third embodiment of the present invention.

9 is an equivalent circuit diagram of a display panel according to a third embodiment of the present invention.

10(a) and 10(b) are schematic diagrams showing vertical inversion driving and dot inversion driving.

FIG. 11 is an equivalent circuit diagram of a conventional display panel.

FIG. 12 is a signal waveform diagram of a driving method of a conventional display device.

Detailed ways

The first embodiment will be described below. 1 is a plan view of a display panel of a dynamic matrix display device, FIG. 2 is a plan view of a display panel according to a first embodiment, and FIG. 3 is an equivalent circuit diagram of the display panel.

First, in FIG. 1, on the display panel 1, a drain driver (drain driver) 2 is arranged along the row direction as a row driver (row driver), and a gate driver (gate driver) is arranged along the column direction. 3 as a column driver (row driver). A display area 4 for displaying images is arranged in an area surrounded by the drain driver 2 and the gate driver 3 .

In the display area 4, as shown in Figure 2 and Figure 3, several drain lines 5 are arranged along the column direction as data lines, and several very long rectangular pixel electrodes 6 are arranged along the row direction as data lines. The gate line 7 of the selection line, and the first storage capacitor line 8a and the second storage capacitor line 8b. In a region where each pixel electrode 6 is arranged (hereinafter referred to as "pixel region"), a TFT 9 and one of the first storage capacitor line 10a or the second storage capacitor line 10b are arranged.

TFT 9 includes: a gate 9g formed by extending gate line 7, a channel (channel) region of the semiconductor layer below it, a semiconductor layer drain region 9d electrically connected to a drain line 5 and a contact, and a pixel electrode 6 The semiconductor layer source region 9s electrically connected to the contact. In the present embodiment, TFT 9 has a double gate type in which two gates 9g are provided.

The first storage capacitor 10a is composed of a storage capacitor electrode 10x formed of a semiconductor layer connected to the TFT 9, and a storage capacitor electrode 10y formed by extending the first storage capacitor line 8a. The second storage capacitor 10b is composed of the above-mentioned storage capacitor electrode 10x and a storage capacitor electrode 10z extending from the second storage capacitor line 8b.

In addition, an opposite electrode 11 is provided on the substrate on which the TFT 9 is provided and on the opposite side of the substrate sandwiching the liquid crystal, constituting a capacitor electrode on the opposite side corresponding to the pixel electrode 6 of the liquid crystal capacitor 12 .

In this embodiment, since the TFT 9 is composed of an N-channel TFT, the data line is called a drain line, and the driver is called a drain driver. However, the TFT 9 may also be composed of a P-channel TFT.

As shown in FIG. 1, a first video signal voltage Vda and a second video signal voltage VDb having mutually opposite polarities are input to the drain driver 2, and either the first video signal voltage VDa or the second video signal voltage VDb One of them is selected and applied to each drain line 5 selected in turn.

The gate lines 7 are sequentially selected to apply the gate signal GV to the gate driver 3 . The display area 4 is an area where a plurality of pixel electrodes 6 are arranged in a matrix, and a voltage is applied between these pixel electrodes 6 and the counter electrode 11 to display an image.

The drain line 5 means that after applying any voltage of the first video signal voltage VDa or the second video signal voltage VDb with opposite polarities, the video signal voltage VDa or VDb is transmitted to the TFT9 through the contact. drain wiring.

The pixel electrode 6 constitutes a pixel region as a display unit, and drives liquid crystal together with the counter electrode 11 by the video signal voltage VD transmitted from the drain line 5 through the TFT 9 .

The gate line 7 is selected by the gate driver 3, and a gate signal GV is applied, thereby turning on (ON) the connected TFT 9 .

The first storage capacitor line 8 a is formed on the same layer as the gate line 7 and is parallel to the gate line 7 . On the first storage capacitor line 8a, a plurality of storage capacitor electrodes 10y integrally formed therewith are arranged along the row direction. Therefore, the storage capacitor electrodes 10y of the first storage capacitors 10a in each row are connected to each other.

The second storage capacitor line 8b is formed on the same layer as the gate line 7 and is also parallel to the gate line 7 . On the second storage capacitor line 8b, a plurality of storage capacitor electrodes 10z integrally formed therewith are arranged along the row direction. Therefore, the storage capacitor electrodes 10z of the second storage capacitors 10b in each row are connected to each other.

In addition, a first storage capacitor voltage is sent to the first storage capacitor line 8a, and a second storage capacitor voltage having a polarity opposite to that of the first storage capacitor voltage is sent to the second storage capacitor line 8b.

TFT9 is a switching element (switching element), and only when a voltage is applied to the gate 9g, the current will flow from the source region 9s to the drain region 9d in the channel region of the semiconductor layer directly below the gate 9g. direction or the direction from the drain region 9d to the source region 9s. The first storage capacitor 10 a and the second storage capacitor 10 b hold the charge generated by the video signal voltage VD output from the drain line 5 through the TFT 9 for one frame period, so as to compensate for the charge loss of the liquid crystal capacitor 12 .

Since a certain voltage is applied to the opposite electrode 11, the driving voltage corresponding to the video signal voltage VD applied to the pixel electrode 6 will be applied to the liquid crystal between the pixel electrode 6 and the opposite electrode 11, thereby driving the liquid crystal. The liquid crystal capacitor 12 of the pixel.

What is held in the liquid crystal capacitor 12 is the charge generated by the video signal voltage VD output by the drain line 5 held by the liquid crystal through the TFT9. However, compared with the charges held by the first storage capacitor 10a or the second storage capacitor 10b, the charges held by the liquid crystal capacitor 12 are very small. Therefore, these charges will be caused by the leakage current when the TFT 9 is cut off (OFF) or from the liquid crystal. The leakage of impurities is easy to flow out. Therefore, it is necessary to supplement the charge held in the liquid crystal capacitor 12 with the charge held in the first storage capacitor 10a and the second storage capacitor 10b.

Next, the driving method will be described. FIG. 4 is a timing chart showing the relationship of signals in the display panel. It represents the vertical start signal STV and the gate signals GV1, GV2, GV3, the horizontal start signal STH and the horizontal pulse signal CKH, and the potential SCa of the first auxiliary capacitor line 8a and the potential SCb of the second auxiliary capacitor line 8b. timing of voltage changes.

First, corresponding to the fall of the vertical start signal STV pulse, the pulse of the gate signal GV1 will rise, and the gate signal GV1 will be sent to the gate line 7 of the first row, so that the TFT 9 connected to the gate line 7 will be conduction state. Then, the pulse of the horizontal start signal STH rises, and when the pulse falls, the pulse of the first horizontal pulse signal CKH in the selected period of the gate line 7 of the first row rises simultaneously.

During the period during which the gate signal GV1 is sent to the gate line 7 of the first row, the pulses of the horizontal pulse signal CKH rise sequentially. While these pulses rise, the drain lines 5 are sequentially selected, and the video signal voltage is sequentially transmitted through the TFT9. VD is applied to the pixel electrode 6 and the first storage capacitor 10a and the second storage capacitor 10b. Furthermore, the first video signal voltage VDa is applied to the pixel electrode 6 and the first storage capacitor 10a, and the second video signal voltage VDb is applied to the pixel electrode 6 and the second storage capacitor 10b.

When the video signal voltage VD is applied to all the drain lines 5, the gate signal GV1 cannot be supplied to the gate line 7 in the first row, and the TFT 9 connected to the gate line 7 is turned off. Therefore, the pulses of the gate signal GV2 and the gate signal GV3 rise sequentially, so that the gate signal GV2 is applied to the gate line 7 of the second row, and the gate signal GV3 is applied to the gate line 7 of the third row. Repeat the above actions.

When the TFT 9 connected to the gate line 7 is in an off state, that is, when the gate signal GV is not supplied to the gate line 7, the potential SCa of the first storage capacitor line 8a and the potential SCa of the second storage capacitor line 8b of the row The polarity of the potential SCb will be reversed. Here, the polarities of the storage capacitor voltages VCa and VCb on the first storage capacitor line 8a and the second storage capacitor line 8b are opposite polarities at the beginning, and are set to be the same as those applied at this time by inversion of the levels. The video signal voltage to the pixel becomes the state of the same polarity, and then maintains this state. Since the inversion of the level is performed immediately after the moment when the TFT9 is cut off, after the first or second video signal voltage is applied to either of the storage capacitors 10a or 10b, since the TFT9 is in the cut-off state, the difference between them and the source voltage Vs Although the potential difference of the counter electrode 11 decreases once, the potential difference between them and the counter electrode 11 is increased by applying the first or second storage capacitor voltage thereafter.

In this way, if the gate signal GV is supplied to all the gate lines 7, the pulse of the vertical start signal STV rises again, and the gate signal GV is applied to the gate lines 7 of the first row synchronously with the pulse, and Repeat the same action.

5 is a signal waveform diagram showing the driving method of the display device according to the first embodiment of the present invention, showing signal waveforms between one frame in adjacent pixel regions in the gate line direction. FIG. 5(a) shows a signal waveform of the first storage capacitor 10a, and FIG. 5(b) shows a signal waveform of the second storage capacitor 10b. The signal waveform shown in Figure 5(a) is approximately the same as that shown in Figure 12, however, the signal waveform shown in Figure 5(b) is just opposite to the polarity shown in Figure 12.

As shown in FIG. 1 , the first storage capacitor 10 a and the second storage capacitor 10 b are arranged on adjacent pixels in the horizontal direction. Therefore, video signal voltages VDa and VDb with opposite polarities are applied to adjacent pixels, and a storage capacitor voltage having the same polarity as the video signal voltage VDa is applied to the first storage capacitor 10a of the pixel to which the video signal voltage VDa is applied. VCa. On the other hand, to the second storage capacitor 10b of the pixel to which the video signal voltage VDb is applied, the storage capacitor voltage VCb having the same polarity as the video signal voltage VDb is applied, and the storage capacitor voltages VCa and VCb are switched while the TFT 9 is off. Polarity reversed. Therefore, the source voltage Vs of the TFT 9 will decrease by only ΔVs by turning off the TFT 9 . However, since the voltage change ΔV _P of the pixel electrode generated by the inversion of the storage capacitor voltage VC tends to increase the voltage between the electrodes of the liquid crystal capacitor 12 , the liquid crystal can be driven with sufficient voltage.

In this way, in the dynamic matrix display device of this embodiment, either storage capacitor 10a or storage capacitor 10b is arranged in each pixel region where pixel electrode 6 is formed. Then, one side of a plurality of storage capacitors 10a, 10b arranged in parallel in the row direction is connected to the source of the TFT 9 of the pixel, respectively. On the other hand, the electrodes on the other side of the storage capacitors 10a arranged every other one along the row direction are connected to the first storage capacitor line 8a. Furthermore, the electrodes on the other side of the storage capacitors 10b arranged every other one along the row direction are connected to the second storage capacitor line 8b.

And, the video signal voltage whose polarity is reversed is supplied to the drain lines 5 in each frame period. The video signal voltage has a first video signal voltage and a second video signal voltage with opposite polarities, and the first video signal voltage and the second video signal voltage are applied to adjacent drain lines 5 , respectively.

Then, by using the first video signal voltage to turn on the TFT 9, when charging the first storage capacitor 10a, the polarity of the first storage capacitor voltage VCa applied to the first storage capacitor line 8a of the pixel can be reversed, and Make it the same polarity as the first video signal voltage. Moreover, when the TFT 9 is turned on by the second video signal voltage, when the second storage capacitor 10b is charged, the polarity of the second storage capacitor voltage VCb applied to the second storage capacitor line 8b of the pixel can be reversed, and Make it the same polarity as the voltage of the second video signal.

In this way, so-called dot inversion driving can be realized by using the auxiliary capacitor lines 8a, 8b.

Then, in this dynamic matrix display device, when the TFT9 is turned on, the first video signal voltage is delivered to the first auxiliary capacitor 10a connected to the first auxiliary capacitor line 8a, and the second auxiliary capacitor is connected to the first auxiliary capacitor 10a. The second storage capacitor of the line supplies the second video signal voltage. Then, when the TFT9 is turned off, at the same time, the source voltage Vs of the TFT9 drops, and the voltage of the auxiliary capacitors 10a and 10b connected thereto decreases.

However, according to the present embodiment, when the TFT 9 is in the cut-off state, the first storage capacitor voltage VCa can be sent to the first storage capacitor line 8a to change the level to the voltage polarity held by the first storage capacitor (at this time The source voltage Vs of the pixel or the polarity of the pixel electrode voltage V _P ), and the second storage capacitor voltage VCb having the opposite polarity to the first storage capacitor voltage VCa is supplied to the second storage capacitor line 8b to change the level To the voltage polarity held by the first storage capacitor (the polarity of the source voltage Vs of the pixel or the pixel electrode voltage _VP at this time). Therefore, the voltages held by the first and second storage capacitors that have fluctuated can be compensated for by the cut-off operation of the TFT 9, and the voltages held by the first and second storage capacitors can be increased.

In the present embodiment, by performing dot inversion driving, it is possible to eliminate the influence of adjacent video signal voltages and prevent image unevenness due to capacitive coupling. Furthermore, while the switching element ( TFT9 ) is in the OFF state, the first and second storage capacitor voltages of opposite polarities are respectively applied while inverting the first and second storage capacitor lines. In this way, even if the amplitude of the video signal voltage is narrowed, a sufficient voltage can be applied to the liquid crystal, and power consumption can be reduced.

In this embodiment, in order to minimize image unevenness and flickering, the first and second storage capacitor lines 8a, 8b are configured to have storage capacitor electrodes alternately in the row direction in units of one pixel. However, the present invention is not limited thereto, and a configuration in which the first and second storage capacitors 10 a and 10 b are alternately arranged in units of several columns of continuous pixels in the row direction may be used.

For example, it is also preferable to arrange three pixels displaying RGB primary colors as a unit, and arrange each unit as storage capacitors 10a, 10b connected to either of the first or second storage capacitor lines 8a, 8b.

Next, a second embodiment will be described.

In the first embodiment, as shown in FIG. 2 , the first storage capacitor line 8a and the second storage capacitor line 8b have a structure overlapping all the storage capacitor electrodes 10x. In this way, only in the pixel area where the second storage capacitor line 8b and the storage capacitor electrode 10z of the second storage capacitor 10b are present, there is a semiconductor superimposed on the connection between the first storage capacitor line 8a and the storage capacitor electrode 10z. Overlap 13 on layers. Therefore, a derived capacitance C _PAR will be generated at the overlapping portion 13 .

The problem to be solved in the second embodiment is that the derivative capacitor C _PAR can only be formed on the second auxiliary capacitor 10b. 6 is a plan view of a display panel according to a second embodiment of the present invention, and FIG. 7 is an equivalent circuit diagram thereof. The same reference numerals are assigned to the same structures as those of the first embodiment, and explanations thereof will be omitted.

This embodiment differs from the first embodiment in that in the pixel area having the storage capacitor electrode 10y, a dummy line extending from the storage capacitor electrode 10y and overlapping the second storage capacitor electrode 8b is provided. 14. The dummy line 14 forms a derived capacitance C _PAR of a portion 13 overlapping the storage capacitor electrode 10z and the first storage capacitor line 8a by forming a portion 13' overlapping the second storage capacitor line 8b where no storage capacitor is formed. equal derived capacitance C _PAR' .

In the first embodiment, since the derivative capacitance C _PAR is generated only at the overlapping portion 13 of the storage capacitor electrode 10z and the first storage capacitor line 8a, only the potential of the second storage capacitor 10b having the storage capacitor electrode 10z decreases. . Therefore, between the pixel region having the storage capacitor electrode 10y and the pixel region having the storage capacitor electrode 10z, there will be a difference in the magnitude of the counter electrode voltage that best matches the pixel electrode 6 in each pixel region, so comparison is likely to occur ( contrast) shift or flicker phenomenon.

However, in the present embodiment, by forming the dummy wiring 14 at the first storage capacitor electrode 10x, the first storage capacitor voltage 10x is formed to be the same as the second storage capacitor line 8b and the dummy wiring 14 where no storage capacitor is formed. The overlapping overlapping portion 13', thereby producing a derived capacitance C _PAR' .

As a result, by achieving a polarity balance between the first storage capacitor 10a and the second storage capacitor 10b, the difference in the magnitude of the counter electrode voltage that best matches the pixel electrode 6 in each pixel area can be eliminated, thereby eliminating Contrast shift or flickering caused by this difference.

Next, a third embodiment will be described. FIG. 8 is a plan view of a display panel according to a third embodiment of the present invention, and FIG. 9 is an equivalent circuit diagram thereof. The same reference numerals are assigned to the same configurations as those of the first embodiment, and description thereof will be omitted. In this embodiment, the arrangement of the drain lines 5 and the pixel electrodes 6 is the same as that in the first or second embodiment.

This embodiment differs from the first and second embodiments in that the gate line 7 is disposed at the center of the pixel electrode and sandwiched between the first storage capacitor line 8a and the second storage capacitor line 8b. Furthermore, in each pixel region, a gate electrode 10x is formed integrally with the gate line 7 and constitutes the TFT 9 with the gate line 7 as a boundary, and the storage capacitor electrode 10x is formed.

In the second embodiment, dummy wirings are arranged in addition to the storage capacitor electrodes which are originally required, so the pattern becomes complicated and the aperture ratio decreases.

However, in this embodiment, by disposing the gate line 7 between the first storage capacitor line 8a and the second storage capacitor 8b, since all the storage capacitor electrodes 10x are connected only to the first storage capacitor line 8a constituting the storage capacitor Or any one of the second auxiliary capacitance lines 8b overlaps, so the overlapping portion 13 and the overlapping portion 13' are unnecessary, and the derivative capacitance C _PAR generated in the overlapping portion can be eliminated.

Furthermore, in this embodiment, the distance between the second storage capacitor line 8b and the TFT 9 can be shortened, thereby reducing the wiring resistance. In this way, since the area of the semiconductor layer required for forming the storage capacitor electrode 10z in the first embodiment or the dummy wiring 14 in the second embodiment can be reduced, the aperture ratio can be increased.

In addition, in each of the embodiments, a double-gate TFT is used as an example, but the present invention is not limited thereto, and may be composed of one gate or three or more gates. Furthermore, although the storage capacitor line and the gate line are formed on the same layer in each embodiment, the storage capacitor line may be formed on a different layer from the gate line.

In addition, in each embodiment, although a dynamic matrix type liquid crystal display device is taken as an example, the present invention is not limited thereto, and it can also be applied to a dynamic matrix electroluminescence (EL) display device.

As described above, in this embodiment, there are a plurality of first and second storage capacitor lines corresponding to each row of pixel electrodes and extending along the row direction, and the first and second storage capacitor lines are alternately arranged in each column of the pixel electrodes. 1 and the auxiliary capacitor corresponding to the second auxiliary capacitor line. In this way, signals with different polarities can be supplied to the auxiliary capacitor lines. Therefore, by applying voltages of different polarities to adjacent pixels through the first and second storage capacitor lines, so-called dot inversion driving can be realized.

In addition, it is preferable to apply any one of a first video signal voltage whose polarity is reversed every frame period or a second video signal voltage whose polarity is opposite to the first video signal voltage to the pixel electrode. In addition, the voltages of the first and second storage capacitors, which change in opposite phases to each other during the OFF period of the switching element, are supplied to the first and second storage capacitor lines. In particular, the first video signal voltage and the first storage capacitor voltage have the same polarity, and the second video signal voltage and the second storage capacitor voltage have the same polarity. Thus, dot inversion driving by the above-mentioned auxiliary capacitor line can be realized, and the amplitude of the video signal voltage can be reduced.

In addition, the first and second storage capacitor lines preferably have storage capacitor electrodes alternately in units of several columns of continuous pixel electrodes. For example, the pixel electrodes of the three primary colors RGB among the display colors are grouped, and voltages having opposite polarities may be applied to adjacent groups. In this way, reverse drive in units of groups can be realized.

Furthermore, it is preferable that the first and second storage capacitor lines overlap all storage capacitor electrodes arranged corresponding to the rows forming the pixel electrodes. In this way, the effect of balancing the polarity between the storage capacitor line where no storage capacitor is formed and the derived capacitance generated in the overlapping region of the storage capacitor electrode can be achieved, thereby preventing image unevenness.

In addition, the storage capacitor electrode preferably has a dummy wiring superimposed on one of the first and second storage capacitor lines on which no storage capacitor is formed. In this way, since the first and second storage capacitor lines are similarly formed to overlap with all storage capacitor electrodes, it is possible to achieve a balance between the storage capacitor lines that do not form storage capacitors and the derivative capacitance generated in the overlapping area of the storage capacitor electrodes. The effect of polarity, which in turn can prevent image unevenness.

In addition, in the pixel region where the pixel electrode is formed, the gate line is preferably arranged between the first and second storage capacitor lines. In this way, the overlapping region of the storage capacitor line and the storage capacitor electrode where no storage capacitor is formed, and the derived capacitance generated in this region can be eliminated, and image unevenness can be prevented.

In addition, in the pixel region, as for the gate line, it is preferable that a gate constituted by a switching element is formed in a region where the storage capacitor electrode is provided with the gate line as a boundary. In this way, the overlapping region of the storage capacitor line and the storage capacitor electrode where no storage capacitor is formed, and the derived capacitance generated in this region can be eliminated, and image unevenness can be prevented.

In addition, in this dynamic matrix display device, a common electrode (counter electrode 11) is arranged on the second substrate, and a constant voltage is applied to the common electrode. In this way, the voltage of the common electrode with a large area can be avoided from changing, and the dynamic matrix display device can be driven with lower voltage and power consumption.

In addition, during the cut-off period of the switching element (TFT9), the voltage levels of the first and second storage capacitors are reversed immediately after the switching element is turned off, making it less susceptible to the influence caused by the switching element's cut-off operation. , when the voltages held by the first and second storage capacitors fluctuate less, the charges of the storage capacitors that have changed are replenished, so that more charges can be used to increase the voltage held by the first and second storage capacitors.

Therefore, according to the present embodiment, it is possible to provide a dynamic matrix display device with high display quality.

Here, voltages of the same polarity may be applied to pixel electrodes adjacent in the direction of the drain line. At this time, a vertical inversion drive as shown in FIG. 10( a ) will be formed.

However, in consideration of characteristics, it is preferable to employ dot inversion driving in which opposite polarities are applied to all pixels adjacent up, down, left, and right as shown in FIG. 10( b ). As shown, in either driving method, a voltage of the opposite polarity to the previous frame is applied to each frame.

By performing dot inversion driving, not only can liquid crystal be prevented from deteriorating, but also capacitive coupling can be effectively prevented.

Claims (13)

1. A dynamic matrix type display device is characterized in that: it configures some pixels in a matrix, and controls the display of each pixel; this device has, a plurality of gate lines extending along the row direction for transmitting gate voltage; A plurality of data lines extending along the column direction for transmitting video signal voltage; a switching element arranged corresponding to the intersection of the gate line and the data line; a pixel electrode connected to the data line through the switching element; and, Corresponding to each row of the above-mentioned pixel electrodes, a plurality of first and second auxiliary capacitor lines extending along the row direction; On each pixel, an auxiliary capacitor electrode superimposed on any one of the first or second auxiliary capacitor lines is also arranged; the first and second auxiliary capacitor lines are respectively supplied with opposite signals during the cut-off period of the switching element. Phase-to-phase change of the 1st and 2nd storage capacitor voltages. 2. The dynamic matrix type display device as claimed in claim 1, wherein a certain voltage is applied to the opposite electrode formed on the opposite substrate, the opposite substrate is opposite to the direction of the substrate on which the above-mentioned pixel electrode is formed, The voltages of the first and second storage capacitors, which change in opposite phases to each other during the off period of the switching element, are supplied to the first and second storage capacitor lines, respectively. 3. The dynamic matrix type display device as claimed in claim 1, wherein the auxiliary capacitor electrodes of each pixel are alternately connected to the first or second auxiliary capacitor electrodes in each column of the pixels. Either line overlaps. 4. The dynamic matrix type display device as claimed in claim 1, wherein the auxiliary capacitor electrodes of each pixel are connected to the first or second auxiliary capacitor lines alternately in units of several columns of the continuous pixels. Any of the lines overlap. 5. The dynamic matrix type display device according to claim 1, wherein all of the above-mentioned storage capacitor electrodes arranged corresponding to the first and second storage capacitor lines and the respective rows of pixels forming these storage capacitor lines overlap . 6. The dynamic matrix display device according to claim 5, wherein the auxiliary capacitor electrode has a part of the first or second auxiliary capacitor line that forms an auxiliary capacitor, while the other part overlaps the auxiliary capacitor that is not formed. Virtual wiring on the auxiliary capacitor line of the capacitor. 7. The dynamic matrix display device according to claim 1, wherein in the pixel region where the pixel electrode is formed, the gate line is arranged between the first and second storage capacitor lines. 8. The dynamic matrix type display device as claimed in claim 7, characterized in that: in the above-mentioned pixel area, on the above-mentioned gate line, with the above-mentioned gate line as the boundary line, in the area equipped with the above-mentioned auxiliary capacitor electrode , forming a gate having the above switching element structure. 9. A dynamic matrix type display device is characterized in that: it configures several pixels in a matrix, and controls the display of each pixel; it has, a plurality of pixel electrodes arranged in rows and columns on the first substrate; switching elements respectively connected to the pixel electrodes; Auxiliary capacitor electrodes respectively arranged in the pixel regions where the above-mentioned pixel electrodes are arranged; first and second storage capacitor lines arranged corresponding to the above-mentioned pixel electrodes of each row; and, The first and second storage capacitors formed in the direction opposite to any one of the first or second storage capacitor lines and the electrodes of the storage capacitor; wherein, By applying any one of the following voltages to the above-mentioned pixel electrode and the above-mentioned storage capacitor electrode, that is, the first video signal voltage whose polarity is inverted every frame period; or the second video signal voltage which is the same as the above-mentioned first video signal voltage The voltage polarity is reversed, while the display is performed in a manner that The first and second storage capacitor voltages whose levels change while the switching element is in an OFF state are supplied to the first and second storage capacitor lines, respectively. 10. The dynamic matrix type display device according to claim 9, wherein the first video signal voltage is supplied to the first auxiliary capacitor electrode while the switching element is in a conducting state, and the second auxiliary capacitor electrode is supplied to the second auxiliary capacitor electrode. The capacitor electrode transmits the above-mentioned 2nd video signal voltage, While the switching element is in the OFF state, the level of the first storage capacitor voltage supplied to the first storage capacitor line changes to a level having the same polarity as the first video signal voltage, The level of the second storage capacitor voltage sent to the second storage capacitor line changes to a level having the same polarity as the second video signal voltage. 11. The dynamic matrix display device according to claim 9, wherein the first video signal voltage is supplied to the first storage capacitor electrode while the switching element is on, and the first auxiliary capacitor electrode is supplied to the first auxiliary capacitor electrode. The capacitor line supplies the first storage capacitor voltage opposite in polarity to the first video signal voltage, supplies the second video signal voltage to the second storage capacitor electrode, and supplies the second video signal voltage to the second storage capacitor line. The voltage of the second auxiliary capacitor with opposite polarity; While the switching element is in the OFF state, the voltage level of the first storage capacitor changes to the same polarity level as the first video signal voltage, and the voltage level of the second storage capacitor changes to the same polarity as the polarity of the first video signal voltage. The voltage polarity of the second video signal is the same level. 12. The dynamic matrix display device according to claim 9, wherein a common electrode is arranged on the second substrate, and a constant voltage is applied to the common electrode. 13. The dynamic matrix type display device as claimed in claim 9, characterized in that: during the period when the switching element is in the cut-off state, after the switching element is cut off, the voltage levels of the first and second auxiliary capacitors change immediately .

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