CN1300098A - Deep turf mask capable of intensifying performance and reliability of buried channel P field effect transistor - Google Patents
Deep turf mask capable of intensifying performance and reliability of buried channel P field effect transistor Download PDFInfo
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- CN1300098A CN1300098A CN 99120592 CN99120592A CN1300098A CN 1300098 A CN1300098 A CN 1300098A CN 99120592 CN99120592 CN 99120592 CN 99120592 A CN99120592 A CN 99120592A CN 1300098 A CN1300098 A CN 1300098A
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- 230000005669 field effect Effects 0.000 title claims description 27
- 239000004020 conductor Substances 0.000 claims abstract description 52
- 239000012212 insulator Substances 0.000 claims abstract description 31
- 239000004065 semiconductor Substances 0.000 claims abstract description 30
- 238000000034 method Methods 0.000 claims description 36
- 230000015572 biosynthetic process Effects 0.000 claims description 29
- 150000004767 nitrides Chemical class 0.000 claims description 25
- 238000002955 isolation Methods 0.000 claims description 15
- 229910052710 silicon Inorganic materials 0.000 claims description 12
- 239000010703 silicon Substances 0.000 claims description 12
- 229910044991 metal oxide Inorganic materials 0.000 claims description 9
- 150000004706 metal oxides Chemical class 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 9
- 239000012535 impurity Substances 0.000 claims description 8
- TVEXGJYMHHTVKP-UHFFFAOYSA-N 6-oxabicyclo[3.2.1]oct-3-en-7-one Chemical compound C1C2C(=O)OC1C=CC2 TVEXGJYMHHTVKP-UHFFFAOYSA-N 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 239000000203 mixture Substances 0.000 description 9
- 229920002120 photoresistant polymer Polymers 0.000 description 9
- 230000007797 corrosion Effects 0.000 description 6
- 238000005260 corrosion Methods 0.000 description 6
- 239000002784 hot electron Substances 0.000 description 6
- 230000003071 parasitic effect Effects 0.000 description 5
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 4
- 230000001105 regulatory effect Effects 0.000 description 4
- 230000007850 degeneration Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 230000000873 masking effect Effects 0.000 description 3
- 238000006396 nitration reaction Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 240000001439 Opuntia Species 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 230000001276 controlling effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000003447 ipsilateral effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
一种半导体结构包括环绕埋置沟道P型金属氧化物半导体场效应晶体管的N阱的第一栅导体,和不环绕表面沟道N型金属氧化物半导体场效应晶体管的P阱的第二栅导体,制造该半导体结构的方法包括邻接每个N阱和P阱形成绝缘体,用构图掩模保护N阱,在邻接N阱的绝缘体区域中形成第一草皮,在邻接P阱的绝缘体区域中形成第二草皮,其中第一草皮的深度大于第二草皮。
A semiconductor structure comprising a first gate conductor surrounding an N-well of a buried-channel PMOSFET and a second gate conductor not surrounding the P-well of a surface-channel NMOSFET The method of fabricating the semiconductor structure includes forming an insulator adjacent to each of the N-well and the P-well, protecting the N-well with a patterned mask, forming a first divot in the insulator region adjacent to the N-well, forming a first divot in the insulator region adjacent to the P-well The second turf, wherein the depth of the first turf is greater than that of the second turf.
Description
The present invention relates generally to that the grating ring of control mos field effect transistor is around amount by regulating the degree of depth of turf (divot) in the shallow channel isolation area of grid.
Have recognized that, in abutting connection with the shallow trench isolation of transistor well in (STI) district, the turf that causes because of the sacrificial oxide layer that removes surface channel N type metal oxide semiconductor field-effect transistor (NFET) be cause the grid conductor " around " reason in the silicon bight of NFET, caused very poor NFET threshold voltage controllability.This turf 12,13 has been shown in abutting connection with buried channel PFET device among Fig. 1.Because this very poor threshold voltage controllability,, improve under the grid conductor doping content in the P trap in order to satisfy target cut-off current (for example field-effect transistor end leakage one source electric current " Ioff ").
Yet, because (for example, surface concentration is greater than 5 * 10 because of P trap surface concentration improves
17Cm
-3), observing the array junctions electric leakage significantly increases, and has a problem so improve this conventional solution of doping content.Owing to the problem of this array NFET that causes because of the STI turf, people are very interested for the problem of the degree of depth minimum that makes turf.
The present invention can make the turf degree of depth minimum of NFET device, can avoid simultaneously causing being manufactured on the same wafer other device for example buried channel PFET device have problems.
Therefore, the purpose of this invention is to provide a kind of on Semiconductor substrate, formation around the first grid conductor of the N trap of buried channel P-type mos field-effect transistor with not around the second grid conductor of the P trap of buried channel N type MOS (metal-oxide-semiconductor) memory.Method of the present invention may further comprise the steps: all form insulator in abutting connection with N trap and P trap; Mask protection P trap with composition; In the insulator region of adjacency N trap, form first turf; Form second turf in the insulator region of adjacency P trap, wherein first turf has the degree of depth greater than second turf.
The technology that forms first turf comprises that the technology that forms second turf is retained in insulator on the P trap side from N trap part side etch insulator.
This method also is included in and forms the grid conductor on N trap and the P trap, thereby a part of grid conductor covers the upper surface of P trap, and other grid conductors cover the upper surface and the side surface of N trap.In addition, the N trap has depletion region in surperficial P type layer, and first turf forms the degree of depth of the degree of depth greater than depletion region.
In another embodiment, this method may further comprise the steps: all form insulator in abutting connection with N trap and P trap; Mask protection N trap with composition exposes the P trap; In the P trap, inject first impurity; Remove first patterned mask; With second patterned mask protection P trap, and the N trap is exposed; In the N trap, inject the second and the 3rd impurity; In the insulator region of adjacency N trap, form first turf; Remove the mask of second composition; In the insulator region of adjacency P trap, form second turf, wherein first turf in the degree of depth greater than second turf.
The present invention also comprises the semiconductor structure with buried channel P-type mos field-effect transistor and surface channel N type metal oxide semiconductor field-effect transistor, buried channel P-type mos field-effect transistor has the N trap and covers the top of N trap and the first grid conductor of part side, and surface channel N type metal oxide semiconductor field-effect transistor has the P trap and covers the second grid conductor on the top of P trap.
Structure of the present invention comprises also that in abutting connection with N trap and first shallow trench isolation with first turf from (STI) district with in abutting connection with the P trap and have second shallow channel isolation area (STI) of second turf, wherein the degree of depth of first turf is greater than second turf.In addition, the N trap comprises the p type island region that exhausts in abutting connection with first grid conductor, and first grid conductor covers the side of N trap, and overburden depth is greater than the degree of depth that exhausts p type island region.In addition, N trap and P trap are positioned on the independent substrate.
The present invention is by regulating the degree of depth of turf in the shallow channel isolation area of grid, in the controlling filed effect transistor grating ring around amount.The present invention is a kind of single technology, on same substrate, in buried channel PFET device, form dark turf, in surface channel NFET device, form the shallow turf degree of depth, by doing like this, provide the subthreshold value swing, cut-off current, parasitic edge conduction, the hot electron that reduce to degenerate and reached the sensitiveness of the electric charge that the adjacent device sidewall is existed.
From following detailed introduction to each preferred embodiment of the present invention in conjunction with the accompanying drawings, can understand above-mentioned better and other purpose, scheme and advantage.
Fig. 1 is the constructed profile of P type buried channel field-effect transistor;
Fig. 2 is the curve chart that concerns between the electric current of not ipsilateral of expression structure shown in Figure 1 and voltage;
Fig. 3 A-3D is the constructed profile that represents the field-effect transistor of the embodiment of the invention;
Fig. 4 A-4D is the constructed profile that represents the field-effect transistor of the embodiment of the invention;
Fig. 5 A-5B is a flow chart of showing the preferred embodiment of the present invention.
As mentioned above, in abutting connection with the shallow trench isolation of transistor well region in (STI) district, the turf that causes because of the sacrificial oxide layer that removes mos field effect transistor be cause the grid conductor " around " reason at silicon edge, caused very poor array NFET threshold voltage (Vt) controllability.Therefore, people are very interested for the problem of the degree of depth minimum that makes turf.In fact, needing among the surface channel N type NFET in abutting connection with the degree of depth of the turf of transistor well region is zero.
The inventor finds that the shallow STI turf degree of depth of necessity is unfavorable for the work of (after this being called PMOSFET or PFET) of buried channel P-type mos field-effect transistor for the bight conductibility of control surface raceway groove NFET.The shallow STI turf degree of depth has caused very poor Ioff grid-control system in the edge of buried channel PFET, makes the PFET device be subject to the influence that sidewall parasitic conduction, very poor sub-threshold slope (subthresholdslope) and hot electron are degenerated.
Fig. 1 is that its left side has the generalized section that dark turf 13 right sides have the buried channel PFET device of shallow turf 12.In addition, Fig. 1 has showed in this example for exhausting P layer 15 on the grid conductor 14 of N+ polysilicon gate conductor and the nitration case 16 cingens N traps 11.Gate oxide 18 has been isolated grid conductor 14 and depletion region 15.Nitration case 16 adjoins shallow trench isolation from (STI) district 10.
With opposite to surface channel NFET effect, shallow turf 12 has caused the parasitic edge conduction in buried channel PFET.The loss of grid-control reduces sub-threshold slope, cut-off current and hot electron reliability.
In order to ensure the acceptable cut-off current of buried channel PFET, grid 14 must enough be controlled the current potential of whole surperficial P layer 15 strong, thereby the main charge carrier (hole) of P layer 15 effectively exhausts.Grating ring is around the control of Electric potentials that has in fact strengthened whole P laminar surface.
Under the situation that has dark STI turf 13, the grating ring in bight is all depleted around the sidewall hole that allows P layer 15.Yet, because shallow turf 12, a little less than the control of grid 14 oppose side walls.This has caused the sub-threshold slope of high cut-off current and degeneration.
Fig. 2 has showed the voltage/current slope (for example at the main carrier depletion of sidewall) of the shallow turf 12 that line 22 is represented and the voltage/current slope of the dark turf 13 that line 21 is represented.As shown in Figure 2, the slope of the line 22 that is produced by shallow turf 12 is compared serious degradation with 21 the better slope that is produced lines by dark turf 13.In addition, the cut-off current 20 of dark turf 13 is far below the cut-off current 23 of the undesirable rising relevant with shallow turf 12.
In addition, because the top of the nitride liner 16 sidewall P layer 17 on the right side, so near any electronics of capturing P layer/nitride interface all can cause sidewall leakage.The electronics of being captured may be that technology induces, and maybe may be that the hot electron degeneration of normal work period device causes.
On the other hand, the nitride liner 16 on the device left side wall is recessed under P layer/N trap junction depth basically.Nitride liner 16 should dark depression have caused greatly reducing of trapped electron density in the zone that is subject to the parasitic conduction influence.Nitride liner 16 has greatly reduced the speed that hot electron is degenerated when not existing basically.
Each method for optimizing of the present invention of introducing below allows dark turf to be manufactured on the PFET, and shallow turf is manufactured on the NFET.The turf degree of depth that can be independent of NFET is suitably determined the STI turf degree of depth of PFET.So the present invention is by regulating the degree of depth of turf in the shallow channel isolation area of grid, the grating ring that can control MOSFET is around amount.
Say that more specifically Fig. 3 A has showed the cross section of the semiconductor transistor that partly forms, this transistor comprise with become NFET the P trap silicon area 300 and will become the silicon area 301 of the N trap of PFET.Fig. 3 A also shows shallow trench isolation from (STI) district 302 and be present in nitride pad 303 and 304 on NFET silicon area 300 and the PFET silicon area 301.In addition, Fig. 3 A shows nitride liner 305.
Utilize known deposit and patterning process to form structure shown in Fig. 3 A.The flow process of Fig. 5 A has gone out this part of the present invention in frame 501.Utilize these structures of conventional method complanation such as for example chemico-mechanical polishing, this structure is smooth to pad nitride 303,304 tops downwards.
Shown in Fig. 3 B, the deposit photoresist layer (or other similar masking material, as the oxide hard masking layer), and composition, WN mask (N trap mask) 310 formed.This step is exposed PFET district 304,301, and NFET district 303,300 is protected by photoresist 310.Fig. 5 A has illustrated this part of the present invention in frame 502.
Utilize common remover, for example Si
3N
4Reactive ion etching or hot H
3PO
4, remove the pad nitration case 304 that exposes, shown in Fig. 3 C.Corrosion depth in nitride liner 305 is determined by the time span of hot phosphoric acid corrosion.Generally speaking, for smooth nitride surface, H
3PO
4To equal 4.5nm/ minute speed corrosion.Utilize the experience of this information and etching condition to regulate, determine to make nitride liner to be recessed to the etching time that its needed degree of depth needs.
Be oxide etch (for example buffered HF) behind the nitride etch, remove general thin nitride pad 304 below and (that is, 6nm) fill up oxide.In most cases, because the controlled excessive erosion time, nitride etch has also removed thin pad oxide fully.This corrosion produces so-called turf 320 in the STI 302 that can fill grid conductor polysilicon (GC poly) easily.Fig. 5 A has illustrated this part of the present invention in frame 503.
The degree of depth of turf should be greater than the degree of depth of raceway groove depletion layer, to obtain good PFET performance.On the other hand, because the reason of above-mentioned discussion, the concentration of turf should minimize among the NFET.The turf degree of depth of NFET better is zero (not having turf).Yet actual situation is, the turf degree of depth of NFET is less than 1/3rd of the depletion region depth of P trap, thus the grid conductor can be not in a large number around the silicon edge of P trap.
The PFET raceway groove depletion layer degree of depth is determined by impurity (for example boron) injection technology.For example, the degree of depth of depletion layer is generally about 600 dusts, and in this case, the turf degree of depth should be about 1000 dusts, to guarantee good PFET performance.
Then, remove dark turf masking photoresist 310, shown in Fig. 3 D.Fig. 5 A has illustrated this part of the present invention in frame 504.Then, remove and stay the pad nitride 303 of district on 300 (reusable heat H for example
3PO
4).This has also removed the pad oxide under the pad nitride 303.Owing to adopt practical pad etching condition usually, the depression of nitride liner 305 keeps minimum in non-PFET (the being NFET) district 300.
Utilize already known processes to finish the formation of semiconductor transistor, comprise the formation of sacrificial oxide layer, the formation that trap injects, formation, the deposit of grid conductor and composition and known other step of one of ordinary skill in the art of gate oxide.Fig. 5 A has illustrated this part of the present invention in frame 505.
Therefore, the present invention optionally is controlled at the dissimilar transistorized turf degree of depth that is formed in the unitary system fabrication technique on the same substrate (for example wafer).
The present invention is useful especially for the technology that adopts buried channel and surface channel MOSFET.Among the application, make example with buried channel PMOSFET and surface channel NMOSFET.As discussed herein, buried channel and surface channel MOSFET have the requirement of the conflicting turf degree of depth.
The above embodiment of the present invention has added additional mask and has formed and removed step in the common process of making NMOSFET and PMOSFET.The second embodiment of the present invention of discussing is below optionally controlled the turf degree of depth of different crystal tube device, and the mask that does not but need to add forms or remove step.
Realize that second preferred embodiment of the present invention is shown among Fig. 4 A-4D and Fig. 5 B.Fig. 4 A and 3A are similar, have showed the silicon area that will be used for NFET 400, the silicon area that will be used for PFET 401, shallow channel isolation area 402, nitride liner 405 and have grown in sacrificial oxide layer 406 on the silicon face 400,401 that exposes.Fig. 5 B has illustrated this part of the present invention in frame 510.
Shown in Fig. 4 B, deposit and composition one deck photoresist form WP mask (P trap mask) 412.This step is exposed NFET district 400,406, and PFET district 401,406 is protected by photoresist 412.Utilize one of ordinary skill in the art's known method, inject p type impurity (for example boron), in the P of NFET trap 400, mix.Flow process among Fig. 5 B has illustrated this part of the present invention in frame 511.
Referring to Fig. 4 C, remove P trap (WP) photoresist 412, deposit another layer photoetching glue and composition are as WN (N trap) mask 421.This figure is protected P trap (NFET) 400 when subsequently PFET401 being handled.Adopt one of ordinary skill in the art's known method again, inject N trap 401, for embedding superficial layer P type dopant with N type dopant (for example phosphorus and arsenic).Fig. 5 B has illustrated this part of the present invention in frame 512.
Yet, shown in Fig. 4 D, before removing WN photoresist 421, carry out oxide etch (for example buffered HF), to remove any sacrifical oxide that covers the end of nitride liner 405 in the PFET district 401.Then, adopt nitride etch (to use for example hot H again
3PO
4), make the nitride liner of exposing 405 be recessed to the needed degree of depth 430.As first embodiment, the corrosion depth in nitride liner 405 is determined by the time span of hot phosphoric acid corrosion.Fig. 5 B is in this part of the present invention shown in the frame 513.
In case left suture by removing nitride liner 405, then adopt the suture 430 in the oxide etch expansion PFET district, NFET is still protected by photoresist 421 simultaneously.This helps using subsequently for example dark turf 430 of grid conductor polysilicon (GC poly) filling.Then, remove N trap photoresist 421, then, remove sacrificial oxide layer 406.
The same with previous embodiment, adopt processes well known to finish the formation of semiconductor transistor, comprise formation, the deposit of grid conductor and composition and known other step of one of ordinary skill in the art of gate oxide.Fig. 5 B has illustrated this part of the present invention in frame 514.
More than having introduced increases the low cost process that does not influence NFET in abutting connection with the turf degree of depth of the STI of buried channel PFET and changes shape.The present invention is by regulating the degree of depth of turf in the shallow channel isolation area of grid, thereby grating ring is around amount in the control MOSFET.Present invention resides on the same substrate, in buried channel PFET device, form dark turf, in surface channel NFET device, form shallow turf.By doing like this, the invention provides the sensitiveness that the subthreshold value swing, cut-off current, parasitic edge conduction, the hot electron degeneration that reduce reach the electric charge that the adjacent device sidewall is existed.
As mentioned above, the present invention relates to adopt the technology of buried channel and surface channel MOSFET.For buried channel PFET, cut-off current and subthreshold value swing reduce, and have caused lower standby power.In addition, the grating ring of increase has caused higher conducting electric current and improved performance around having increased effective channel width.
For surface channel NFET, reduced the turf degree of depth.Because standard Vt can set lowlyer, but is no more than the cut-off current target under the worst case, so have better Vt control and improved performance.
Although introduced the present invention in conjunction with the preferred embodiments, the those skilled in the art it should be understood that the present invention can realize with the shape that changes in the spirit and scope of appended claims.
Claims (29)
1 one kinds of methods of making semiconductor transistor comprise:
A plurality of transistor well regions that formation is isolated by insulator;
In the said insulator region of second well region of said transistor well region, forming first turf; And
Forming second turf in the said insulator region of said first well region, the degree of depth of wherein said first turf is greater than said second turf.
2 methods according to claim 1, wherein said formation transistor well region comprises said first well region of formation, P trap as surface channel N type metal oxide semiconductor field-effect transistor, form said second well region, as the N trap of buried channel P-type mos field-effect transistor.
3 according to the silicon well region that the process of claim 1 wherein that said formation transistor well region comprises that formation is surrounded by nitride and separated from (STI) by shallow trench isolation.
4 according to the process of claim 1 wherein that said first turf of said formation comprises the said insulator of part side etch from said second well region, and said second turf of said formation remaines in said insulator on the side of said first well region.
5 methods according to claim 1 also are included in and form the grid conductor on the said transistor well region, make some said grid conductors cover the upper surface of said first well region, and other said grid conductors cover the upper surface and the side of said second well region.
6 according to the process of claim 1 wherein that said formation transistor well region comprises said second well region of formation, makes it to have depletion region, and said first turf forms the degree of depth of its degree of depth greater than said depletion region.
7 one kinds of methods that on Semiconductor substrate, form the first grid conductor and the second grid conductor, wherein first grid conductor loops is around the bight of the N trap of buried channel P-type mos field-effect transistor, around the P trap of surface channel N type metal oxide semiconductor field-effect transistor, said method does not comprise the second grid conductor:
Form insulator in abutting connection with each said N trap and said P trap;
In the said insulator region of said N trap, forming first turf; And
Form second turf in the said insulator region of adjacency P trap, the degree of depth of wherein said first turf is greater than the degree of depth of said second turf.
8 methods according to claim 7, wherein said first turf of said formation comprises the said insulator of part side etch from said N well region, said second turf of said formation remaines in said insulator on the side of said P well region.
9 methods according to claim 7 also are included in and form the grid conductor on said N trap and the said P trap, make some said grid conductors cover the upper surface of said P trap, and other said grid conductors cover the upper surface and the side of said N trap.
10 methods according to claim 7, wherein said N trap has depletion region, and said first turf forms the degree of depth of its degree of depth greater than said depletion region.
11 1 kinds of methods of making semiconductor transistor comprise:
A plurality of transistor well regions that formation is isolated by insulator;
Protect first well region of said transistor well region with first patterned mask, second well region of said transistor well region is exposed;
In said second well region, inject first impurity;
Remove said first patterned mask;
Protect said second well region with second patterned mask, and said first well region is exposed;
In said first well region, inject the second and the 3rd impurity;
In the said insulator region of said first well region, forming first turf;
Remove said second patterned mask; And
Forming second turf in the said insulator region of said second well region, the degree of depth of wherein said first turf is greater than said second turf.
12 methods according to claim 11, wherein said formation transistor well region comprises said second well region of formation, P trap as surface channel N type metal oxide semiconductor field-effect transistor, form said first well region, as the N trap of buried channel P-type mos field-effect transistor.
The silicon well region that 13 methods according to claim 11, wherein said formation transistor well region comprise that formation is surrounded by nitride and separated from (STI) by shallow trench isolation.
14 methods according to claim 11, wherein said first turf of said formation comprises the said insulator of part side etch from said first well region, said second turf of said formation remaines in said insulator on the side of said second well region.
15 methods according to claim 11 also are included in and form the grid conductor on the said transistor well region, make some said grid conductors cover the upper surface of said second well region, and other said grid conductors cover the upper surface and the side of said first well region.
16 methods according to claim 11, wherein said formation transistor well region comprise said first well region of formation, make it to have depletion region, and said first turf forms the degree of depth of its degree of depth greater than said depletion region.
17 1 kinds of methods that on Semiconductor substrate, form the first grid conductor and the second grid conductor, wherein first grid conductor loops is around the bight of the N trap of buried channel P-type mos field-effect transistor, around the bight of the P trap of buried channel N type metal oxide semiconductor field-effect transistor, said method does not comprise the second grid conductor:
Form insulator in abutting connection with each said N trap and said P trap;
Protect said N trap with patterned mask, said P trap is exposed;
In said P trap, inject first impurity;
Remove said first patterned mask;
Protect said P trap with second patterned mask, said N trap is exposed;
In said N trap, inject the second and the 3rd impurity;
In the said insulator region of said N trap, forming first turf;
Remove said second patterned mask;
Forming second turf in the said insulator region of said P trap, the degree of depth of wherein said first turf is greater than said second turf;
Form said first grid conductor on said N trap and in said first turf;
Form the said second grid conductor on said P trap and in said second turf.
18 methods according to claim 17, wherein said first turf of said formation comprises the said insulator of part side etch from said N trap, said second turf of said formation remaines in said insulator on the side of said P trap.
19 methods according to claim 17 also are included in and form the grid conductor on said N trap and the said P trap, make some said grid conductors cover the upper surface of said P trap, and other said grid conductors cover the upper surface and the side of said N trap.
20 methods according to claim 17, wherein said N trap has depletion region, and said first turf forms the degree of depth of its degree of depth greater than said depletion region.
21 1 kinds of semiconductor structures comprise:
A plurality of the first transistors have first well region and cover the top of said first well region and the first grid conductor of part side; And
A plurality of transistor secondses have second well region and the second grid conductor that covers the said second well region top.
22 semiconductor structures according to claim 21 also comprise:
Said first well region of adjacency also has first isolated area of first turf; And
Said second well region of adjacency also has second isolated area of second turf,
The degree of depth of wherein said first turf is greater than said second turf.
23 semiconductor structures according to claim 21, wherein said first well region comprise the depletion region in abutting connection with said first grid conductor, and said first grid conductor covers the side of said first well region, and overburden depth is greater than the degree of depth of said depletion region.
24 semiconductor structures according to claim 21, wherein said first well region comprises the N trap of buried channel P-type mos field-effect transistor, said second well region comprises the P trap of surface channel N type metal oxide semiconductor field-effect transistor.
25 semiconductor structures according to claim 21, wherein said first well region and said second well region are positioned on the independent substrate.
26 1 kinds of semiconductor structures comprise:
A plurality of buried channel P-type mos field-effect transistors have the N trap and cover the top of said N trap and the first grid conductor of part side; And
A plurality of surface channel N type metal oxide semiconductor field-effect transistors have the P trap and cover the second grid conductor on the top of said P trap.
27 semiconductor structures according to claim 26 also comprise:
Distinguish from (STI) in abutting connection with the said N trap and first shallow trench isolation with first turf; And
In abutting connection with said P trap and second shallow trench isolation with second turf from (STI) district,
The degree of depth of wherein said first turf is greater than said second turf.
28 semiconductor structures according to claim 26, wherein said N trap comprise the p type island region that exhausts in abutting connection with said first grid conductor, and said first grid conductor covers the said side of said N trap, and the degree of depth of covering is greater than the said degree of depth that exhausts p type island region.
29 semiconductor structures according to claim 26, wherein said N trap and said P trap are positioned on the independent substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB991205928A CN1159752C (en) | 1999-10-09 | 1999-10-09 | Deep pit mask for enhanced performance and reliability of buried channel p field effect transistors |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB991205928A CN1159752C (en) | 1999-10-09 | 1999-10-09 | Deep pit mask for enhanced performance and reliability of buried channel p field effect transistors |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1300098A true CN1300098A (en) | 2001-06-20 |
| CN1159752C CN1159752C (en) | 2004-07-28 |
Family
ID=5281570
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB991205928A Expired - Fee Related CN1159752C (en) | 1999-10-09 | 1999-10-09 | Deep pit mask for enhanced performance and reliability of buried channel p field effect transistors |
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| Country | Link |
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| CN (1) | CN1159752C (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103050500A (en) * | 2011-10-13 | 2013-04-17 | 全视科技有限公司 | Partial buried channel transfer device for image sensors |
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1999
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103050500A (en) * | 2011-10-13 | 2013-04-17 | 全视科技有限公司 | Partial buried channel transfer device for image sensors |
| US9698185B2 (en) | 2011-10-13 | 2017-07-04 | Omnivision Technologies, Inc. | Partial buried channel transfer device for image sensors |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1159752C (en) | 2004-07-28 |
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