CN1399348A - Surface (transverse) voltage-proof structure with high-dielectric constant film - Google Patents

Abstract

The present invention proposes a method or an auxiliary method to cover the surface of a semiconductor with a high dielectric constant thin film as the best lateral flux. This high dielectric constant film can introduce electric flux on the semiconductor surface, and can also take out electric flux on the semiconductor surface, or take out electric flux in one part and introduce electric flux in another part. Using the best lateral flux can produce lateral high-voltage devices, and can be used as a junction edge technology for vertical high-voltage devices, and can prevent the generation of strong electric fields on the boundaries covering the dislocation compensation impurity layer. It can also be used as a method to achieve the best lateral flux to fabricate devices when the electric flux entering the substrate only accounts for a very small part of the total flux.

Description

Surface (lateral) pressure-resistant structure with high dielectric constant film

technical field

The invention relates to a semiconductor device, in particular to a surface withstand voltage region of a lateral high voltage device and a junction edge region of a vertical high voltage device.

Background technique

As we all know, the withstand voltage region of surface (lateral) high-voltage devices generally adopts RESURF technology. From the literature [X.B.Chen, et al., "Optimization of the drift region of powerMOSFET's with lateral structure and deep junctions", IEEE Trans.E.D.Vol.ED-34, No.11, pp.2344-2350 (1987)] known Generally, the breakdown voltage of the surface device made by RESURF technology can only reach 70% of the breakdown voltage of the drift region (actually the above-mentioned withstand voltage region) of the single-side mutation parallel planar junction under the same substrate doping concentration, and by The on-resistance of the horizontal MOST made in this way is also very large. The inventor's patents U.S.Patent 5,726,469 and U.S.Patent 6,310,365 B1 proposed a method of using the best surface lateral doping to make the surface withstand voltage region. Using this method, the surface breakdown voltage can be placed at the same substrate doping concentration. 90% or more of the breakdown voltage of the parallel plane junction, and the on-resistance of the drift region of the lateral MOST can also be very small. This kind of withstand voltage region can also use the dislocation of the p-type region and the n-type region Impurity compensation is achieved, so it is possible to be fully compatible with CMOS or BiCMOS processes.

In [XBChen, et al., "Theory of optimal design of reverse-biased pn junction using resistive field plates and variation lateral doping", Solid-State Electronics, Vol.35, No.8, pp.1365-1370(1992)] The optimal doping density of the surface withstand voltage region (set as n ^{-type below) which is inverse to the doping of the substrate (set as p-} type below) is published. Figure 1(a) shows a structural diagram of a diode using this voltage-resistant layer as an interdigitated bar pattern. In the figure, 1 represents the p ^- type substrate region, 2 represents the n ⁺ type contact region, and 3 represents the p ⁺ -type contact region, 4 represents the n-type region of the surface withstand voltage layer, A represents the anode, K represents the cathode, and the withstand voltage region is a section of coordinates from x=0 to x=L. The solid line in Fig. 1(b) indicates the optimal surface impurity charge density D required to obtain the highest breakdown voltage at a certain distance L, where D ₀ =qN _B W _pp , q represents the electronic charge, and W _pp represents the same Thickness of the depletion layer of the one-sided mutation parallel plane junction (n ⁺ -p ^- junction) under the substrate (p ^- ) concentration, N _B is the acceptor concentration of the substrate, and D ₀ represents the depletion of the n ⁺ region at this time layer charge density. The figure shows the situation of L = 2W _pp , and the resulting surface withstand voltage region can withstand 95% of the breakdown voltage of the parallel plane junction with the single-side mutation of the substrate. The dotted lines 5, 6, and 7 in this figure represent the best case where three segments of uniform surface impurity charges are used instead of the solid line. The breakdown voltage obtained by this three-stage approximation is only slightly lower than that obtained by the solid line. Figure 1(c) and Figure 1(d) respectively show the distribution of the lateral electric field _Ex and surface potential V on the surface under the condition of optimal surface variable doping. E _crit and V _Bpp in the figure respectively represent the maximum electric field and breakdown voltage of the single-side abrupt parallel plane junction at the time of breakdown under the same contrast doping concentration. Figure 1(e) schematically depicts a method for implementing a three-stage uniform surface impurity charge. Here, the surface withstand voltage region has an n-type region 4 with a uniform donor density, and its charge density exceeds the maximum charge density of segment 5 in the dotted line in Figure 1(b). On the top of the n-type region 4 there is a thin p-type region 8 whose acceptor density is also uniform, but it does not completely cover the n-type region 4 . In this figure, the p-type region 8 covers the least part (that is, the part containing points A and A' in the figure), and the average charge density generated by the combined action of the donor charge in the n-region 4 and the acceptor charge in the p-region 8 is equal to 1(b) is approximated by the dashed line segment 5. In the middle part of the figure, a large part of the p-type region 8 covers the n-type region 4, so that the average charge density generated by the joint action of the donor charge and the acceptor charge in this part is equal to three times in Fig. 1(b) Segment approximated by dashed line segment 6. In the right part of the figure, the p-type region 8 completely covers the n-type region 4, so that the average charge density of this part is equal to the three approximate dashed line segments 7 in FIG. 1(b). This method is the above-mentioned method using the compensation effect of heterotopic impurities.

Obviously, the more the approximate number of segments is, the closer the obtained breakdown voltage is to the effect achieved by the solid line in Figure 1(b).

However, the above-mentioned dislocation impurity compensation method may not be available in a suitable dose of the p-type region 8 or a suitable dose of the n-type region 4 in the CMOS or BiCMOS process. In addition, under the condition of the deep submicron process, the n-type drift region 4 itself is very thin, so the donor concentration in this region is very high, resulting in a small mobility. Therefore, the specific on-resistance of the lateral n-MOST made with this technology is very large. The fact that the mobility becomes smaller can be explained from the following rough numerical calculation example. For high-voltage devices, the donor density (the number of donors per unit area) of the n-type region 4 should generally be about 2·10 ¹² cm ^-2 . When the depth of n-type region 4 changes from 2 μm to 0.1 μm, the corresponding donor concentration changes from 1·10 ¹⁶ cm ^-3 to 2·10 ¹⁷ cm ^-3 , so the electron mobility changes from 1400 cm ² /V·s to 650cm ² /V·s. Furthermore, if the n-type region 4 is covered by the p-type region 8, the corresponding n-type region 4 has a smaller thickness and a larger specific on-resistance. Furthermore, as described in [XBChen, "Lateral high-voltage devices using an optimized variational lateral doping", Int.J.Electronics.Vol.83, No.3, pp.449-459(1996)], using Fig. In the compensation method shown in 1(e), on the boundary of the p-type region 8, for example, points A and A' in the figure, an electric field parallel to the semiconductor surface and perpendicular to the direction of the p-type strip 8 will be generated , the electric field will also slightly decrease the breakdown voltage.

Contents of the invention

The purpose of the present invention is to avoid the above-mentioned disadvantages, and cover the semiconductor surface with a thin film of high permittivity (high permittivity dielectric) material (hereinafter referred to as HK film), which can guide the electric flux line from a certain area to a place where a certain electric flux needs to be introduced. Flux lines somewhere on the semiconductor surface, or vice versa. The high permittivity material mentioned here refers to its permittivity ε _K = Kε ₀ which is much larger than the permittivity of semiconductors ε _S = Sε ₀ , where ε ₀ is the vacuum permittivity, and K and S represent high permittivity Relative permittivity of electrical coefficient materials and semiconductor materials.

In fact, the optimal surface withstand voltage region means that the electric flux D to the substrate in the surface withstand voltage region meets the requirements of Figure 1(b). Because as long as this requirement is met, the upper part of the depletion region of the semiconductor region under the withstand voltage region has the same boundary condition when the voltage V is applied, so there is the same answer, and this electric flux does not necessarily use electricity It cannot be produced without impurities.

Accordingly, the present invention provides a surface withstand voltage region for a semiconductor device comprising a semiconductor substrate of a first conductivity type and a heavily doped semiconductor substrate of a second conductivity type in contact with the substrate. The maximum potential region of the region or metal region, and the minimum potential region of a heavily doped first conductivity type semiconductor region or metal region connected to the substrate;

The surface withstand voltage region is located on the top of the substrate from the maximum potential region to the minimum potential region, and is characterized in that:

The surface withstand voltage region includes at least a section of high dielectric constant dielectric film covering the surface of the semiconductor;

The high-permittivity dielectric film covering the surface of the semiconductor can also have one or more sections with a conductor on its top, and the conductor can be floating or connected to a potential terminal outside the withstand voltage region;

The surface withstand voltage region may also include one or more segments of semiconductor surface thin layers whose net doping is the second conductivity type and/or the first conductivity type, and the impurity concentration and/or type of the surface thin layers are different from those of the substrate. ;

When the surface withstand voltage region has a reverse breakdown voltage close to the maximum potential and the minimum potential, the withstand voltage region sends out a net electric flux of the first symbol to the substrate everywhere, and the electric flux line The average flux density decreases gradually or stepwise from approximately qN _B W _pp , where q represents the electron charge, N _B represents the impurity concentration of the substrate, and W _pp represents the single-sided abrupt parallel plane junction formed by the substrate at its strike The thickness of the depletion layer under the breakdown voltage, the flux density refers to the value obtained by dividing the effective total flux in an area whose lateral dimension of the surface is much smaller than W _pp but greater than the thickness of the surface withstand voltage region; The thickness of the surface withstand voltage region at this place refers to the thickness of the dielectric film with high dielectric constant at this place plus the thickness of the surface thin layer with different doping to the substrate at this place;

The sign of the net electric flux line of the first sign means that the sign of this electric flux line is consistent with the sign of the flux line produced by the ionized impurities of the semiconductor of the second conductivity type;

The net average electric flux density of the first symbol refers to the value of the average electric flux density of the first symbol minus the average electric flux density of the second symbol opposite to the first symbol;

Under the action of the average electric flux density of the above-mentioned net first symbol in the surface withstand voltage region, the electric field along the surface (lateral direction) points from the maximum potential region to the minimum potential region, and its value gradually changes from close to zero to or stepwise increase;

The electric flux density mentioned includes the electric flux density generated by the ionized impurity charge of the thin layer of semiconductor surface which is net-doped as the second conductivity type or the first conductivity type in the surface withstand voltage region, and also includes the electric flux density caused by the high dielectric The electric flux density induced by the electric coefficient film;

The electric flux density caused by the high dielectric constant film refers to the electric flux density caused by no conductor on the top of the high dielectric constant film and/or the electric flux caused by the conductor on the top of the high dielectric constant film Quantity density;

The electric flux density caused by the high dielectric constant film without conductor on the top refers to the electric field along the surface (transverse direction) multiplied by this side at a small distance from the surface, on the side closest to the maximum potential region The value obtained by subtracting the electric field along the surface (horizontal direction) of the side farthest from the maximum potential region from the square capacitance multiplied by the square capacitance on this side;

The square capacitance refers to the amount obtained by dividing the electric flux component parallel to the surface in the dielectric film by the electric field component parallel to the surface;

The electric flux density caused by the high-permittivity film with a conductor on the top refers to the value obtained by subtracting the potential of the top of the film from the potential of the semiconductor surface by the specific capacitance of the high-permittivity film ;

The specific capacitance refers to the value obtained by dividing the potential difference between the top of the high dielectric constant film and the semiconductor surface below it by the electric flux density caused by the potential difference.

In addition, the present invention also provides a thin withstand voltage region for a semiconductor device, the semiconductor device contains a heavily doped first conductivity type semiconductor region or the minimum potential region of the metal region and a heavily doped first conductivity type semiconductor region or the minimum potential region of the metal region and a heavily doped first The maximum potential region of the semiconductor region or metal region of two conductivity types;

The thin withstand voltage region of the semiconductor device is located between the maximum potential region and the minimum potential region, and is characterized in that:

The surface withstand voltage region includes at least a section of high dielectric constant dielectric film covering the surface of the semiconductor;

The high-permittivity dielectric film covering the surface of the semiconductor can also have one or more sections with a conductor on its top, and the conductor can be floating or connected to a potential terminal outside the withstand voltage region;

The thin withstand voltage region of the semiconductor device may include one or more thin layers net-doped with the first conductivity type and/or the second conductivity type;

When the thin withstand voltage region of the semiconductor device has a reverse breakdown voltage close to the maximum potential and the minimum potential, each place in the thin withstand voltage region emits a net doping to the dielectric film with a high dielectric coefficient. Electric flux lines with the same electric flux density produced by the dose;

The electric flux lines sent to the high-permittivity dielectric film are absorbed by the conductor covering the top of the high-permittivity dielectric film and/or pass through the high-permittivity dielectric film and are finally heavily doped. absorbed by a semiconductor or metal region of one conductivity type and/or absorbed by a heavily doped semiconductor or metal region of a second conductivity type;

After the electric flux line generated by the thin withstand voltage region is absorbed by the high dielectric constant film, the electric field component from the maximum potential region to the minimum potential region is close to constant.

The concrete content of the present invention can be expressed with five examples.

The first example is shown as the diode in Figure 2, which is composed of p ^- type substrate 1, n ⁺ type contact region 2, p+ type contact region 3, and HK film layer 9, where A is the anode and K is the cathode. In the surface withstand voltage region (from x=0 to x=L), there is no ionized donor at all, and its electric flux depends on the electric flux emitted from the cathode K, and gradually dissipates to the semiconductor surface through the HK film 9. The lines with arrows in the figure represent the electric flux lines. Here, at the HK film 9 not covered by electrodes, the thickness of the HK film 9 gradually becomes thinner with the distance away from K, which makes the electric flux entering the semiconductor gradually decrease.

The second example is shown in Figure 4, which is composed of p ^- type substrate 1, n ⁺ type contact area 2, p ⁺ type contact area 3, n type drift area 4 and HK film layer 9, where A is the anode , K is the cathode. Here, there is already a layer of n-type region 4 on the surface of the semiconductor, but the flux density it produces during ionization is greater than the maximum value of D required in Figure 1(b). The role of the HK film 9 from 0 to L is to absorb x>0 The electric flux of the n region 4 at the place can be finally absorbed by the top of the p ⁺ region 3 connected to the anode A. Here the thickness of the HK film 9 gradually increases with the distance away from x=0, so that more and more electric fluxes are allowed to flow in the HK film 9, and as a result, n in the distance from x=0 to x=L Below region 4 there is an electric flux density to the substrate that meets the requirements of Fig. 1(b).

The third example is shown in Figure 5. It is composed of p ^- type substrate 1, n ⁺ type contact area 2, p ⁺ type contact area 3, n type area 4 and HK film 9, where A is the anode and K is the cathode. Here, there is a layer of n-type region 4 under the surface of a section from x=0 to x=d ₀ , but the flux density generated by its ionization is greater than the maximum value of D required in Fig. 1(b), and after this section to A section of x=L has no ionized donors available at all, the effect of the HK film 9 from x=0 to x=d ₀ is to absorb the flux of the n-type region 4 at x≥0, these fluxes are in the absence of n-type region 4 where x ≥ d ₀ is gradually released to the substrate. As a result, within the distance from x=0 to x=L, the electric flux density meeting the requirements of Fig. 1(b) is generated under the withstand voltage region.

The fourth example, as shown in Figure 13, is covered by striped HK film 9 in the area including point A and point A' in Figure 1(e), so that the covered semiconductor top n-region 4 has electric flux The outflow semiconductor enters the HK layer 9 , then flows through the HK film 9 to the p-region 8 on top of the semiconductor and then enters the p-region 8 . The effect is equivalent to the reduction of the effective donor density of the covered n-region 4, and the increase of the effective donor density of the covered p-region 8, and the directions of points A and A' are parallel to the semiconductor surface and perpendicular to the p-type strip 8 The electric field can be greatly reduced.

The fifth example is shown in FIG. 17 in an n ^{+ np+ diode} composed of n+-type contact region 2, n-type region 4 and p ⁺ -type contact region 3. The upper part of the n-type region 4 in the entire withstand voltage region is covered by the HK film 9 , and the top of the HK film 9 is connected with the anode A by conductors. The lines of electric flux emitted by the donors of the n-region 4 all or almost all pass through the HK film 9 and terminate in the conductor above it. When the cathode K applies a positive voltage to the anode A, the distribution of the electric field in the n region 4 is close to the electric field distribution in the i region of the n ⁺ -ip ⁺ diode, that is, the transverse electric field is close to a constant constant, so that the n region 4 can be Withstand the highest voltage within the shortest lateral distance.

Description of drawings

Figure 1 shows a case of an optimal surface withstand voltage region with a p ^- type semiconductor as the contrast

(a) A schematic diagram of the cell of a diode with interdigitated bar pattern (the withstand voltage area in the figure is the area within the distance from 0 to L on the abscissa x, K represents the cathode, and A represents the anode)

(b) Schematic diagram of the variation of the electric flux D between the cathode K and the anode A that can withstand the surface donor density of 0.95V _Bpp as a function of the surface distance when the distance of a surface withstand voltage region is L=2W _pp . (V _Bpp is the breakdown voltage of the unilateral abrupt parallel planar junction under the same substrate impurity concentration _NB , and W _pp is the reverse voltage of the unilateral abrupt parallel planar junction under the same substrate impurity concentration _NB as V _Bpp The thickness of the depletion layer. D ₀ represents the donor number per unit area of the depletion region of the n ⁺ region under the reverse voltage V _Bpp parallel to the substrate multiplied by the electron charge q, D ₀ =qN _B W _pp , N _B is the acceptor concentration of the substrate)

(c) A schematic diagram of the variation of the lateral electric field E _x on the surface with the distance from the surface under the doping condition along the semiconductor surface in Fig. 1(b). (E _crit represents the breakdown critical electric field of the parallel plane junction with unilateral mutation made on the same substrate)

(d) Potential V of the surface under the doping condition along the surface in Fig. 1(b). (V _Bpp is the breakdown voltage of a single-sided abrupt parallel planar junction at the same substrate impurity concentration _NB )

(e) represents an implementation method for realizing the compensation method of heterotopic impurities.

Figure 2 shows a method for covering the surface withstand voltage region with an HK film to achieve a surface electric flux density close to the D required in Figure 1(b) (the curve with the arrow in the figure represents the electric flux in the HK film Wire)

Figure 3 shows another method to cover the surface pressure-resistant region with HK film to achieve a surface flux density close to D required in Figure 1(b)

Figure 4 shows that the effective electric flux density of the surface pointing to the substrate gradually decreases with the increase of x (the number of donors per unit area in the n region in the figure exceeds the proper maximum value)

Figure 5 shows the situation where the donor density in one section of the surface exceeds the proper maximum value and the other section is completely absent. Covering the substrate with an HK film can generate an electric flux density that meets the requirements of the optimum withstand voltage region.

The electric flux density of the donor in the n-region of the surface in Fig. 6 reaches the maximum value in Fig. 1(b), and the electric flux density (negative value) partially covering the p-region above it is greater than the maximum value in Fig. 1(b) The following example using HK film

Figure 7 The electric flux entering the semiconductor from x ₁ to x _{2 is} the flux flowing from x ₁ to the right in the HK film minus the flux flowing from x ₂ to the right in the HK film)

Figure 8: There is a conductor on a piece of HK film, and the conductor is connected to a certain potential

Figure 9 HK film thickness is not constant, and there is a conductor on the top connected to a certain potential V ₀

Figure 10 The change of the coverage of the HK film is used to replace the change of the thickness

Figure 11 The case where the HK film is connected to the semiconductor through a LK (low dielectric constant) film

Figure 12 Three sections of materials with different dielectric coefficients (HK ₁ , HK ₂ , HK ₃ ), their dielectric coefficients increase sequentially

Figure 13 is covered with an HK film on a section of the semiconductor surface in Figure 1(e) to reduce the electric field at points A and A' parallel to the semiconductor surface and perpendicular to the p-type strip in the figure

Figure 14 VLF as the edge technology of n-VDMOST (from x=0 to x=L is the surface withstand voltage region)

Figure 15 is an example of fabricating a lateral n-MOST using the withstand voltage region as shown in Figure 4

Figure 16 Example of using floating electrodes on top of the HK film to achieve the required VLF

Figure 17 An example of a diode with a HK film with a conductor connected to the anode A on the top

Figure 18 In the diode shown in Figure 17, the ideal transverse electric field E _x and voltage V(x) vary with distance x

(a) Variation of the lateral electric field E _x of the n-type semiconductor with the distance x in Figure 17

(b) In Figure 17, when the cathode K has a voltage V _K to the anode, the internal potential V of the n region varies with the distance x

Figure 19: An example of making a diode on SIS with a HK film with all conductors on the top connected to the anode

Figure 20 is an example of fabricating a lateral MOST using the structure of Figure 19

Figure 21 An example of lateral MOST fabricated with a HK film with all conductors on the top connected to the drain

specific implementation

According to the above, the role of the surface withstand voltage region can be considered to be that it produces an electric flux density on the substrate that changes with the distance from the high potential end, that is, the variation lateral flux (VariationLateral Flux, referred to as VLF). Using the best surface lateral doping layer (Variation Lateral Doping, referred to as VLD) is just one way to achieve the best VLF. According to the aforementioned reasons, we can also use other methods to produce an optimal VLF for the substrate.

FIG. 2 shows a method to achieve optimum VLF by having a high dielectric constant (abbreviated as HK) film 9 of varying thickness on the semiconductor surface. The figure shows a cell of a high voltage diode in an interdigitated bar pattern. In the figure, there is no surface n-type region 4 at all from the n ⁺ type contact region 2 of the cathode K to the p ⁺ type contact region 3 of the anode A. The thick line in the figure represents the electrode contact, and the shaded area represents the HK film 9 . The permittivity ε _K of this HK film 9 is much larger than the permittivity ε _S of the semiconductor. The thickness of the dielectric film 9 starts at x=0 on the cathode side and increases gradually until x=d ₁ , and the top of the HK film 9 at 0≤x≤d ₀ (≤d ₁ ) has a conductor and a cathode K connect. The curves with arrows in the figure schematically represent the electric flux lines of 9 in the HK membrane. In the region with the conductor on top, there is a larger electric flux density flowing into the semiconductor. After this region, because the distance that the electric flux line travels is getting larger and larger, and the thickness of the HK film 9 is getting smaller and smaller, so the flux density entering the semiconductor through the HK film 9 is also getting smaller and smaller.

Appropriate design and fabrication of this distance-varying HK film 9 can make the electric flux density D(x) entering the semiconductor meet the requirements of the curve in Figure 1(b).

Fig. 3 shows another method of using HK film 9 to meet the requirements of the curve in Fig. 1(b). The HK film here is thicker than the n ⁺ type heavily doped region 2 at the cathode K. Electric flux lines enter the HK film 9 from the heavily doped region 2, and then gradually flow into the semiconductor surface. Therefore, this HK film 9 can play the same role as the HK film 9 of FIG. 2 .

The above two examples are the cases where the p ^- substrate 1 has no n-type withstand voltage region 4 at all, and the dielectric layer provides the required (positive) flux into the substrate everywhere on the semiconductor surface. In fact, (if desired), the dielectric layer can also provide the necessary negative flux, ie the flux out of the substrate. Figure 4 shows an example of such a situation. Here, the semiconductor surface from the n ⁺ region 2 connected to the cathode K to the p ⁺ region 3 connected to the anode A itself has an n-type thin layer 4 whose donor dose is greater than the maximum dose shown in Figure 1(b). In order to achieve the electric flux density along the x direction under the thin semiconductor layer as shown in Fig. 1(b), which decreases gradually with the increase of x, the HK Membrane 9 is covered, and its end is connected with anode A.

Starting from x=0, part of the electric flux flows out from the semiconductor surface to the HK film 9, at x= _d1 , more flux flows out due to the thickening of the HK film 9, and so on. The effect of the flux flowing out is the same as that of p-type doping on the semiconductor surface in Fig. 1(e). As a result, the flux penetrating into the p ^- substrate 1 under the n region 4 gradually decreases with distance.

The above examples all have one end connected to an electrode or a heavily doped region connected to an electrode.

In fact, the HK film plays the role of absorbing electric flux from the semiconductor surface and/or emitting electric flux to the semiconductor surface. FIG. 5 schematically shows another example of using the HK film. Here the n-type region 4 is uniformly doped, ^and its dose is greater than the maximum value of D divided by q shown in Fig. A distance to x = d ₀ . The remaining section cannot provide positive electric flux to the substrate at all. After having the upper layer of HK film, starting from the HK film 10 of the first stage, the semiconductor surface has a positive flux flowing into the HK film, which makes the positive flux density from the n region 4 to the substrate in this section conform to Figure 1(b ) of the maximum paragraph 5 requirement. The electric flux flowing into the first section of the HK film flows into the second section 11 along the x-coordinate direction, and part of it flows back into the semiconductor surface from the second section 11, causing positive flux to flow in there, and part of it flows into the third section 12. In the third section 12, part of the electric flux flows into the semiconductor surface again. The rest of the electrical flux flows into the semiconductor surface in the fourth segment 13 . Appropriately designing the physical parameters and geometric parameters of each section can make the electric flux density entering the substrate approximately meet the requirements of Figure 1(b).

Fig. 6 shows another example of applying the HK film. In this figure, the donor density in the first region 14 of the n-type region is exactly equal to the stage 5 where the electric flux density of the three stage changes in Fig. 1(b) is the largest. The electric flux density generated by the donor density in the second region 15 of the N-type region is higher than that in the middle stage 6 of the electric flux density of the three stages of step change in FIG. 1( b ). And the electric flux density obtained by subtracting the acceptor density of the p ⁺ type region 3 at the top of the region from the donor density of the n-type region 16 in the third region 16 is better than the electric flux density of the three-stage step change in Fig. 1(b) The lowest section 7 is still lower. There is a layer of HK film 9 on the semiconductor surface of the 15th and 16th regions. It absorbs part of the electric flux in the 15th region and releases it to the semiconductor surface in the 16th region. As a result, x=0 to x In the region of =L, the electric flux density of p ^- substrate 1 conforms to the stepwise change of Fig. 1(b).

是电通量密度矢量)。因此，进入某段HK膜的电通量等于流出的电通量；2)两端电位差与路径无关(即

是电场强度矢量)。因此，在HK膜与半导体的界面两边，平行于界面的电场分量相等。Regarding the design of the HK membrane, standard numerical calculation software, such as TMA/MEDICI, TMA/DAVINCI, etc., can be used for simulation. Rough calculation methods are introduced below, which can at least be used as initial values for simulation calculations. The theoretical basis of the calculation is two points: 1) In the region without space charge, the electric flux is conserved, (ie

is the electric flux density vector). Therefore, the electric flux entering a section of HK membrane is equal to the electric flux flowing out; 2) The potential difference between the two ends has nothing to do with the path (ie

is the electric field intensity vector). Therefore, on both sides of the interface between the HK film and the semiconductor, the electric field components parallel to the interface are equal.

Let the thickness of the HK film 9 change from coordinates x ₁ to x ₂ in Fig. 7 from t ₁ to t ₂ , and suppose the thickness of the HK film 9 in this short section (x ₁ to x ₂ ) is much smaller than that of the junction parallel to the substrate The depletion layer thickness _WPP at the breakdown voltage is multiplied by _εK / _εS . The value of the flux entering HK membrane 9 from the left side of x=x ₁ is t ₁ D _x (x ₁ )=t ₁ ε _K E _x (x ₁ ) within a unit distance perpendicular to the paper surface, and from x ₂ this The flux passing through one section is t ₂ D _x (x ₂ )=t ₂ ε _K E _x (x ₂ ), where D _x and E _x represent the components of D and E in the x direction. The subtraction of the two is the flux D _y (x ₁ −x ₂ ) into the semiconductor 17 . therefore

D _y (x ₁ -x ₂ )＝ε _K (t ₁ E _x (x ₁ )-t ₂ E _x (x ₂ ))

According to this formula, the thickness of high dielectric constant can be calculated for a given E _x (x) (can be found from Figure 1(c)) and the required D _y (can be found from Figure 1(b)) .

In this patent, the amount obtained by dividing the transverse component of the electric flux in the dielectric film by the transverse component of the electric field is called the square capacitance, represented by _C. For the above-mentioned case where there is only one HK film, it is obvious that C _ou is the dielectric coefficient ε _K of the HK film multiplied by the thickness t of the film, that is, C _ou = ε _K t. It can be seen that when x ₁ is close to x ₂ in the above formula, the flux density D _y introduced into the semiconductor by the HK film can be expressed in differential form as:

D _y ＝-d(C _port E _x )/dx (1)

For x=0 to x=L of Fig. 3 and in the distance of x=d ₀ to x=L of Fig. 2 and Fig. 5, D _y should press the requirement of D value shown in Fig. 1 (b), and E _x Should be in accordance with Figure 1 (c) requirements. In this way, the change of _port C with distance can be obtained. In fact, the decrease of _C with the increase of distance x is enough to exceed the influence of the increase of E _x with the increase of distance x, which can ensure that D _y has a sufficient positive value.

For the situations of x=0 to x=L in Fig. 4 and x=0 to x=d ₀ in Fig. 5, the electric flux density _Dn produced by the n-type region 4 on the semiconductor surface is already greater than that shown in Fig. 1(b) The maximum flux density (the latter is about 1.1D ₀ ) is obtained, so the D _y provided by the HK membrane 9 is required to be negative. The value of D _y is equal to D _n minus the value of D shown in Fig. 1(b). A moderate increase of _C with distance x can provide D _y with a suitable negative value.

The above discussion is the case where there is no conductor connected to a certain potential on the upper part of the HK membrane. The following discusses the situation where there is a conductor connected to a certain potential V ₀ on a section of HK film, but there is no high-permittivity material connected at both ends of this section of high-permittivity material. As shown in Figure 8, suppose the ideal potential of the semiconductor surface at x is V(x) (can be found from Figure 1(d)), and the flux density that should enter is D _y (x), then at x The thickness t of the high dielectric constant material can be approximated as ε _K (V ₀ -V(x))/t=D _y (x), that is, t=ε _K (V ₀ -V(x))/D _y ( x).

In this patent, there is an electrode on the top of the HK film, and the flux density entering the semiconductor surface caused by the potential difference between it and the semiconductor surface below is divided by the potential difference, which is called the specific capacitance (capacitance per unit area) C _v . For the above case where there is only one uniform HK film, it is clear that C _v is equal to the dielectric coefficient of the HK film divided by its thickness t, that is, C _v =ε _K /t. Using the definition of C _v , the above formula can be written as:

D _y (x)＝C _v (V ₀ -V(x)) (2)

As shown in Figure 9, the top of the HK film 9 has a conductor connected to a potential V ₀ , assuming that the thickness of the HK film 9 is not uniform, the theoretical design of this situation is relatively complicated, and the thickness at x ₁ is t ₁ , At _x2 the thickness is _t2 . A rough method of determining t ₁ and t ₂ is as follows.

The electric flux from _x1 to _x2 into the semiconductor surface has two sources. One source is the electrical flux generated by the top conductor of the HK membrane 9 . Another source is the electrical flux flowing in from the left at _x1 of the HK membrane 9 minus the electrical flux flowing out from the right at _x2 .

The electric flux emitted from the top of the HK film 9 perpendicular to the semiconductor surface can be determined by the electric field perpendicular to the surface. The value E′ _y of this vertical electric field at points x ₁ and x ₂ can be approximated as E′ _y (x ₁ )=(V ₀ -V(x ₁ ))/t ₁ and E′ _y (x ₂ ) respectively ＝(V ₀ -V(x ₂ ))/t ₂ , so the electric flux densities are ε _K E′ _y (x ₁ ) and ε _K E′ _y (x ₂ ) respectively, and the sections from x ₁ to x ₂ are composed of The average value of electric flux generated at the top of the HK film 9 can be approximately taken as [ε _K E′ _y (x ₁ )+ε _K E′ _y (x ₂ )]/2.

Actually, the above-mentioned electric field E' _y perpendicular to the semiconductor surface is a component of the electric field at the top of the HK film 9 . The electric field itself is a conductor perpendicular to the top of the HK film 9 . There is an angle θ ₀ between the plane of the conductor and the plane of the semiconductor surface, which can be determined by tanθ ₀ =(t ₂ -t ₁ )/(x ₂ -x ₁ ). Suppose the electric field at the top is E', then E' _y =E'cosθ ₀ . The electric field at the top also has a component in the x direction, which is E′ _x =E′sinθ ₀ . It can be known from the above that E′ _x =E′ _y tanθ ₀ .

The parallel electric field _Ex on the semiconductor surface can be determined by Fig. 1(c). Then, the electric field parallel to the surface in HK film 9 at point _x1 changes from E _x at the semiconductor surface to E' _x at the top. Its average value is (E _x +E′ _x )/2, which has different values at two points x ₁ and x ₂ [E _x (x ₁ )+E′ _x (x ₁ )]/2 and [E _x (x ₂ )+E′ _x (x ₂ )]/2. Therefore, the electric flux entering the HK film 9 from the left side of x ₁ is ε _K t ₁ [E _x (x ₁ )+E′ _x (x ₁ )]/2, and the electric flux going out from the right side of x ₂ is ε _K t ₂ [E _x (x ₂ )+E′ _x (x ₂ )]/2, the two electric fluxes are subtracted and then divided by (x ₂ -x ₁ ), that is, by parallel to the semiconductor surface The flux density of the electric field introduced into the semiconductor.

In the above-described example, the thickness of the high-permittivity film is changed to achieve the required electric flux density entering the semiconductor surface. In fact, as pointed out in US Patent 5,726,469 and US Patent 6,310,365 B1, the required The electric flux density is only an average value in a region that is much smaller than the depletion region thickness W _PP of the parallel plane junction with the same substrate single-side mutation at the breakdown voltage. Therefore, it is obvious that some places have high dielectric coefficient dielectric films, while some places do not have this method to replace dielectric films of different thicknesses. FIG. 10 shows an alternative to FIG. 4 . This figure is the arrangement of a HK film 9 (shaded area in the figure) seen from the top, if the thickness of the HK film 9 is t, then the far right is equivalent to a dielectric layer with a uniform thickness of t, and the middle section is equivalent to For a dielectric layer with a thickness smaller than t, the equivalent thickness of the left segment is smaller than that of the middle segment. The equivalent thickness of the dielectric layer is equal to the coverage of the dielectric layer in the z direction (that is, the ratio of the length of the area with the dielectric in the unit length to the unit length) multiplied by its thickness t.

Now look at the discussion in the previous paragraph from the perspective of square capacitance. In fact, the square _capacitance C of the HK film 9 in Fig. 4 increases with the increase of x. However, the area of the HK film in Figure 10 is constantly expanding, which means that the equivalent (or average) square _capacitance C increases with the increase of x. So the two HK membranes in Figure 4 and Figure 10 have the same effect on the electric flux.

For the case where a conductor is connected to the top of the HK film and connected to a certain potential, the equivalent calculation of the thickness of the HK film is different from the above. The average value of the flux lines emitted from the top of the area with low coverage is also reduced, which is equivalent to the increase of the thickness of the HK film there. From the perspective of specific capacitance, the number of specific capacitances connected in parallel in the area with low coverage decreases, so the average specific capacitance also decreases. This corresponds to an increase in the thickness of the HK film when there are all HK films.

In summary, the flux into the semiconductor can be varied by changing the pattern of the dielectric layer.

The dielectric film with high dielectric constant is certainly not limited to one kind of material, it can be a combination of several kinds of materials. Even, the surface of the semiconductor can be covered with a layer of low dielectric constant material (such as SiO ₂ on Si) and then covered with a layer (or multiple layers) of high dielectric constant material. As long as the thickness of this layer of low-permittivity material is much smaller than the thickness of the upper layer of high-permittivity material, then this layer of low-permittivity material is essential for the electric flux from the semiconductor surface into the high-permittivity material film, and from The penetration of high-k material films into the semiconductor surface has no serious effect. FIG. 11 shows a situation where a thin layer of low-permittivity material 18 is attached to the surface of semiconductor 17, on which is the above-mentioned high-permittivity material 19.

When there are n layers of HK film, and the thickness of each layer is t ₁ ,...t _n , then when there is no conductor connection on the top, _{the port} C in formula (1) can be written as:

in

C _□i = ε _Ki t _i

When there is a conductor connection at the top, ε _Ki is the permittivity of the i-th layer. Then C _v of formula (2) can be written as: $\frac{1}{C_v}=\mathrm{\Σ}\frac{1}{C_{\mathrm{vi}}}$

where C _vi =ε _Ki /t _i

The high dielectric constant material itself can also be a variety of materials. Figure 12 shows that three high dielectric constant materials are used to replace the situation in Figure 4. The three high dielectric constant materials are HK ₁ film 20 and HK ₂ film 21 respectively. And HK ₃ film 22, wherein K ₃ >K ₂ >K ₁ , when the materials and widths of K ₁ , K ₂ , and K ₃ are properly selected, they may maintain the same thickness.

The use of the HK film can also eliminate the peak of the electric field. Figure 13 shows a method for reducing the electric field at points A and A' of Figure 1(e) parallel to the semiconductor surface but perpendicular to the p-type strip 5. Arrange a HK film 9 (shaded area in the figure) on the semiconductor surface in the z direction. The HK film 9 absorbs the positive electric flux of some donors at the top of the n-region 4 and covers the top of the p-region 5. Release the positive electric flux. The effect is that there is part of the p region 5 at the top of the n region 4, and the dose at the top of the p region 5 is reduced, so that the electric field in the z direction is greatly weakened.

The above discussions are all for the case of p-type substrates. It is not difficult for those skilled in the art to know that the above discussion can easily be deduced to the case where the substrate is n-type.

The above-mentioned surface withstand voltage region can naturally be used in various devices. Obviously, for vertical devices, it can be used as a junction edge technology outside the active area. Fig. 14 shows an example of using this kind of withstand voltage region as the edge technology of n-VDMOST, which consists of n ⁺ type drain region 23, n type region 4, p source material substrate region 24, n ⁺ type source contact region 25 , n ⁺ -type drain contact region 26 and HK film 9 with varying thickness, wherein G is the gate electrode, D is the drain electrode, and S is the source electrode. This is the method using Figure 3, the difference is that the p-type and n-type are just the opposite of Figure 3.

For lateral (surface) devices, only the diode example was given above. Figure 15 shows an example of using the surface withstand voltage region of Figure 4 to manufacture a lateral n-MOST. This structure consists of a p ^- type substrate 1, an n-type region 4, a p-source substrate region 24, and an n ^+-type source region 25 , n ⁺ type drain contact region 26 and HK film 9 with variable thickness, wherein G is the gate electrode, D is the drain electrode, S is the source electrode, and the shaded area with X between the gate and the semiconductor is the gate insulating layer. Wherein x=0 to L is the surface withstand voltage region, the top of the last segment of the HK film 9 has a conductor connected to the source, and the source is also connected to the substrate.

Figure 16 shows an example where there are floating electrodes on the HK film to achieve the desired VLF. Here, the semiconductor under the HK film is the same as in Figure 5. When there is a floating electrode on the top of the HK film, assuming that the potential of the floating electrode is V _fl , then from x=0 to d ₀ , the electric current generated by the semiconductor The amount is absorbed by the top electrode through the HK film, and at x≥d ₀ , the top electrode sends out electric flux lines, which enter the semiconductor surface through the HK film. An example of approximate calculation of geometric parameters and physical parameters of HK membrane is as follows. The average value of the semiconductor surface potential from x=0 to this section of x=d ₀ is V ₀ as required, and the average value of the semiconductor surface potential from x=d ₀ to this section of x=d ₁ is V ₁ as required. From x= The average value of the semiconductor surface potential of this section from d ₁ to x=d ₂ is V ₂ as required, and the average value of the semiconductor surface potential of this section from x=d ₂ to x=d ₃ (=L) is V ₃ as required; and Let the specific capacitance of the HK film on the above-mentioned sections be C _v0 , C _v1 , C _v2 , and C _v3 in sequence; then set the average value of the electric flux density of each section entering the semiconductor surface as D ₀ , D ₁ , D ₂ , D ₃ (the value of D ₀ is actually negative), the relationship between these quantities is

(V _fl -V _i )C _vi = D _i , where i = 0, 1, 2, 3 (3)

The total flux emitted by the floating electrode should be zero, i.e. $\underset{i=0}{\overset{3}{\mathrm{\Σ}}}{\mathrm{D.}}_i(d_i-d_{i-1})=0$ , where d _-1 ＝0 (4)

Actually, from the required values of D _i and V _i and the given values of d _i , V _fl and C _vi can be obtained from equations (3) and (4).

The optimum surface flux mentioned above is that the surface withstand voltage region exhibits the electric flux density D as shown in Fig. 1(b) to the substrate. In fact, the principle of the present invention can also be used in other situations. Figure 17 shows an example of an n ⁺ np ⁺ diode without a substrate underneath. In the n ⁺ region 2 connected to the cathode K and the p There is an n-region thin layer 4 not very lightly doped between the ⁺ regions 3 . If we want the n-region thin layer 4 to withstand a high voltage, it is best that the electric flux lines of the donors in it are all absorbed by the HK thin layer 9 covering it. After the cathode K applies a positive voltage V _K to the anode A, the electric field along the x direction in the n region 4 is shown in Figure 18(a), which does not change with the distance, which is very similar to an n ⁺ -ip ⁺ diode . The potential distribution in the n region is shown in Fig. 18(b).

If the electric flux density of the ionized donor in the unit area of the n-region thin layer 4 is _Dn , these electric fluxes will all be absorbed by the conductor connected to the electrode K on the HK film 9, then at any coordinate x point should have

D _n =ε _K V _x /t _x

Here V _x represents the potential at point x in the n region, and t _x represents the thickness of the film having a dielectric constant ε _K of the layer above this point.

Since the required V _x can be written as V _K (1-x/L), where L represents the length of the n-region 4, for the case where the donor density of the n-region 4 is uniform, the above formula obviously requires t _x =t _M ( 1-x/L), where t _M represents the maximum thickness of the HK layer.

In the above calculation, it is assumed that the electric flux line of the n-type layer 4 at the bottom can be absorbed by the upper electrode through the HK layer as well as the top. In fact, from the bottom of the n-type layer 4 to the electrode, it can be considered that there are two capacitors in series, one is ε _K /t _x , the other is ε _S /d, and d is the thickness of the n layer. As long as ε _S /d>>ε _K /t _x , then the assumption of the above formula is reasonable. Otherwise, only a certain modification to the calculation of t _x is required.

The example in FIG. 17 is a situation where the electric flux emitted by the donor in the n-type region is not emitted downward through the bottom surface. A practical situation is the semiconductor thin layer on top of an insulator (I) layer, which in turn is on top of the semiconductor substrate (S layer), the so-called SIS situation, as shown in FIG. 19, for the S layer 27 is In the case of Si, the I layer is often a thicker SiO ₂ layer 28 . Since the dielectric constant of the _SiO2 layer 28 is three times smaller than that of Si, the electrical flux lines of the donors in the n layer emit fewer flux lines through the bottom surface to the substrate. The above theoretical calculation can be used as an approximation.

Fig. 20 shows the example that utilizes Fig. 19 to make lateral MOST, it is made of S layer 27, I layer 28, n-type region 4, n ⁺ type source region 25, p-type source substrate region 24, n ⁺ The drain region 26 is composed of a HK film 9 with a variable thickness, wherein G represents the gate, and there is a thin insulating layer below it, and there is a HK layer on the n-layer 4 of the drift region, and the conductor on the top and the source electrode Except S connection, others are the same as the usual horizontal MOST composed of SIS.

The above principle can of course also be used in the case where the conductor on top of the HK film is connected to K in FIG. 17 or D in FIG. 20 . At this time, the thickness of the HK film increases continuously with the distance from K or D. Fig. 21 shows a situation of making lateral MOST with this connection, and this MOST is made of S layer 27, I layer 28, n-type region 4, n ⁺ type source region 25, p-type source substrate region 24, n ⁺ drain Region 26 and a HK film 9 of varying thickness. Among them, G represents the gate, S represents the source, and D represents the drain.

Using the structure shown in FIG. 20 or FIG. 21 , a lateral MOST with a very short drift region, heavy doping and high withstand voltage can be produced. Its on-resistance can be made very small.

The example shown in FIG. 17 is a case where the withstand voltage region of a semiconductor device is covered with a high dielectric constant film on one side. In fact, the withstand voltage region of the semiconductor device can also be covered with a high dielectric constant film on the other side. When there is a conductor on the top of the high-permittivity film on the other side, and when the conductor is connected with the n ⁺ region 2, the specific capacitance of the high-permittivity film gradually decreases with the distance away from the n ⁺ region 2. When there is a conductor on the top of the high-permittivity film on the other side, and when the conductor is connected with the p ⁺ region 3, the specific capacitance of the high-permittivity film gradually increases with the distance from the n ⁺ region 2.

Because the MOST of deep submicron Si requires high dielectric constant materials to replace the traditional gate oxide (SiO ₂ ) layer, and also because it is hoped to use a smaller area to manufacture capacitive elements in integrated circuits. At present, many HK film materials have been developed for application.

Although the above implementation example has been described in combination with two devices and one edge technology, for those of ordinary skill in the art, without violating the basic connotation of the present invention, the technology of the present invention can be modified and widely applied to various semiconductor devices.

Claims (19)

1. A surface withstand voltage region for a semiconductor device comprising a semiconductor substrate of the first conductivity type and a heavily doped semiconductor region of the second conductivity type or metal in contact with the substrate The maximum potential region of the region, and the minimum potential region of a heavily doped first conductivity type semiconductor region or metal region connected to the substrate; The surface withstand voltage region is located on the top of the substrate from the maximum potential region to the minimum potential region, and is characterized in that: The surface withstand voltage region includes at least a section of high dielectric constant dielectric film covering the surface of the semiconductor; The high-permittivity dielectric film covering the surface of the semiconductor can also have one or more sections with a conductor on its top, and the conductor can be floating or connected to a potential terminal outside the withstand voltage region; The surface withstand voltage region may also include one or more segments of semiconductor surface thin layers whose net doping is the second conductivity type and/or the first conductivity type, and the impurity concentration and/or type of the surface thin layers are different from those of the substrate. ; When the surface withstand voltage region is close to the reverse breakdown voltage between the maximum potential and the minimum potential, the withstand voltage region sends a net electric flux of the first symbol to the substrate everywhere, and the electric flux line The average flux density of , decreases gradually or stepwise from approximately qN _B W _pp , where q represents the electron charge, N _B represents the impurity concentration of the substrate, and W _pp represents the single-sided mutation-parallel plane junction formed by the substrate at its The thickness of the depletion layer under the breakdown voltage, the flux density refers to the value obtained by dividing the effective total flux in an area whose lateral dimension of the surface is much smaller than W _pp but greater than the thickness of the surface withstand voltage region ; The thickness of the surface withstand voltage region at this place refers to the thickness of the dielectric film with high dielectric constant at this place plus the thickness of the thin surface layer with different doping on the substrate at this place; The sign of the net electric flux line of the first sign means that the sign of this electric flux line is consistent with the sign of the flux line produced by the ionized impurities of the semiconductor of the second conductivity type; The net average electric flux density of the first symbol refers to the value of the average electric flux density of the first symbol minus the average electric flux density of the second symbol opposite to the first symbol; Under the action of the average electric flux density of the above-mentioned net first symbol in the surface withstand voltage region, the electric field along the surface (lateral direction) points from the maximum potential region to the minimum potential region, and its value gradually changes from close to zero to or stepwise increase; The electric flux density mentioned includes the electric flux density generated by the ionized impurity charge of the thin layer of semiconductor surface which is net-doped as the second conductivity type or the first conductivity type in the surface withstand voltage region, and also includes the electric flux density caused by the high dielectric The electric flux density induced by the electric coefficient film; The electric flux density caused by the high dielectric constant film refers to the electric flux density caused by no conductor on the top of the high dielectric constant film and/or the electric flux caused by the conductor on the top of the high dielectric constant film Quantity density; The electric flux density caused by the high dielectric constant film without conductor on the top refers to the electric field along the surface (transverse direction) multiplied by this side at a small distance from the surface, on the side closest to the maximum potential region The value obtained by subtracting the electric field along the surface (horizontal direction) of the side farthest from the maximum potential region from the square capacitance multiplied by the square capacitance on this side; The square capacitance refers to the amount obtained by dividing the electric flux component parallel to the surface in the dielectric film by the electric field component parallel to the surface; The electric flux density caused by the high-permittivity film with a conductor on the top refers to the value obtained by subtracting the potential of the top of the film from the potential of the semiconductor surface by the specific capacitance of the high-permittivity film ; The specific capacitance refers to the value obtained by dividing the potential difference between the top of the high dielectric constant film and the semiconductor surface below it by the electric flux density caused by the potential difference. 2. The surface withstand voltage region of a semiconductor device according to claim 1, wherein the semiconductor substrate of the first conductivity type is a p-type semiconductor, the semiconductor of the second conductivity type is an n-type semiconductor, and the semiconductor substrate of the first conductivity type is an n-type semiconductor. The sign of the electric flux line of the sign is consistent with the sign of the flux line generated by the positive charge, the maximum potential has the highest potential, the minimum potential has the lowest potential, and the withstand voltage region emits positive electric flux to the substrate everywhere. 3. The surface withstand voltage region of a semiconductor device according to claim 1, wherein the semiconductor substrate of the first conductivity type is an n-type semiconductor, the semiconductor of the second conductivity type is a p-type semiconductor, and the semiconductor substrate of the first conductivity type is a p-type semiconductor. The sign of the electric flux line of the sign is consistent with the sign of the flux line produced by the negative charge, the maximum potential has the lowest potential, the minimum potential has the highest potential, and the withstand voltage region absorbs positive electric flux from the substrate everywhere, That is, a negative electric flux is emitted to the substrate everywhere. 4. The surface withstand voltage region of a semiconductor device according to claim 1, the surface withstand voltage region has no impurity concentration and type of thin layer inconsistent with the substrate, and the top of the high dielectric constant dielectric film is completely Without a conductor, the square capacitance of the high-permittivity dielectric film decreases continuously or stepwise from the maximum potential away from the surface to the minimum surface potential. 5. The surface withstand voltage region of a semiconductor device according to claim 1, said surface withstand voltage layer region has a doped region of the second conductivity type near the maximum potential, and the number of impurities per unit area exceeds N _B W _pp ; there is no conductor at the top of the dielectric film with high dielectric coefficient, and the square capacitance of the dielectric film with high dielectric coefficient begins to decrease continuously or stepwise from the maximum potential of the surface until the surface minimum potential. 6. The surface withstand voltage region of a semiconductor device according to claim 1, wherein the surface withstand voltage region has a doped region of the second conductivity type from the maximum potential to the minimum potential, and the number of impurities per unit area exceeds N _B W _pp ; The square capacitance of the dielectric film with high dielectric coefficient increases continuously or stepwise away from the maximum potential on the surface, and the dielectric film also covers the connected area at the minimum potential. 7. The surface withstand voltage region of a semiconductor device according to claim 1, said surface withstand voltage region has a doped region of the second conductivity type near the maximum potential, and the number of impurities per unit area exceeds N _B W _pp , there is a doped region with a net dose of the first conductivity type near the minimum potential, and the square capacitance of the dielectric film with high dielectric constant increases continuously or stepwise from the maximum potential away from the surface, However, the net dose near the minimum potential is continuously reduced in the doped region of the first conductivity type. 8. The surface withstand voltage region of a semiconductor device according to claim 1, the surface withstand voltage region has no impurity concentration and type of thin layer inconsistent with the substrate, and the top of the high dielectric constant dielectric film is completely There is no conductor, and the top of the dielectric film with high dielectric constant has a conductor to connect with the maximum potential in a section adjacent to the maximum potential of the surface, and the specific capacitance in this section increases with the distance away from the maximum potential. It decreases continuously or stepwise, and the surface withstand voltage area outside this section also has a dielectric film with high dielectric coefficient but there is no conductor on the top. The square capacitance formed by this dielectric film increases continuously or stepwise as it approaches the minimum potential. reduced in a manner. 9. The surface withstand voltage region of a semiconductor device according to claim 1, wherein the surface withstand voltage region has a doped region of the second conductivity type from the maximum potential to the minimum potential, and the number of impurities per unit area exceeds N _B W _pp ; The dielectric film with high dielectric coefficient is divided into two regions. There is no conductor at the top of the region adjacent to the maximum potential. In this region, the square capacitance increases continuously or stepwise with the distance from the maximum potential on the surface. to increase; The dielectric film with high permittivity has a conductor on its top connected to the minimum potential in the area adjacent to the minimum potential, and the specific capacitance in this area decreases continuously or stepwise with the distance close to the minimum potential. Increase. 10. The surface withstand voltage region of a semiconductor device according to claim 1, wherein the thickness of the high dielectric constant film changes continuously or stepwise with the distance from the maximum potential. 11. The surface withstand voltage region of a semiconductor device according to claim 1, wherein the coverage ratio of the high dielectric constant film on the semiconductor surface changes continuously or stepwise with the distance from the maximum potential. 12. The semiconductor surface withstand voltage region according to claim 1, at least one section of said high dielectric constant film is formed by the close combination of thin layers of multiple dielectric constant materials. 13. The semiconductor surface withstand voltage region according to claim 1, which contains a semiconductor thin layer whose net doping is the second conductivity type or the first conductivity type, and the surface within a certain distance from the maximum potential has a high A dielectric film covers the upper part. 14. A semiconductor device made of the surface withstand voltage region of the semiconductor device according to claim 1. 15. The edge outside the active region of the semiconductor device formed by the surface withstand voltage region of the semiconductor device according to claim 1. 16. A thin withstand voltage region for a semiconductor device containing a heavily doped first conductivity type semiconductor region or a minimum potential region of a metal region and a heavily doped second conductivity type The maximum potential area of the semiconductor region or metal region; The thin withstand voltage region of the semiconductor device is located between the maximum potential region and the minimum potential region, and is characterized in that: The surface withstand voltage region includes at least a section of high dielectric constant dielectric film covering the surface of the semiconductor; The high-permittivity dielectric film covering the surface of the semiconductor can also have one or more sections with a conductor on its top, and the conductor can be floating or connected to a potential terminal outside the withstand voltage region; The thin withstand voltage region of the semiconductor device may include one or more thin layers net-doped with the first conductivity type and/or the second conductivity type; When the thin withstand voltage region of the semiconductor device is applied with a reverse breakdown voltage close to the maximum potential and the minimum potential, each thin withstand voltage region sends out a net doping with the dielectric film of high dielectric coefficient. Electric flux lines with the same electric flux density generated by impurity dose; The electric flux lines sent to the high-permittivity dielectric film are absorbed by the conductor covering the top of the high-permittivity dielectric film and/or pass through the high-permittivity dielectric film and are finally heavily doped. absorbed by a semiconductor or metal region of one conductivity type and/or absorbed by a heavily doped semiconductor or metal region of a second conductivity type; After the electric flux line generated by the thin withstand voltage region is absorbed by the high dielectric constant film, the electric field component from the maximum potential region to the minimum potential region is close to constant. 17. A semiconductor device made of the surface withstand voltage region of the semiconductor device according to claim 16. 18. The semiconductor device according to claim 17, one side of the thin withstand voltage region is covered by the high dielectric constant film, and the other side is in contact with a low dielectric constant film, the low dielectric constant film The membrane is in turn joined to a semi-insulating or insulating thick semiconductor layer. 19. The semiconductor device according to claim 17, both sides of the thin voltage-resistant region are covered by said high dielectric constant film.

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