CN1395155A - DDR and QDR conversion device and adapter card, motherboard and memory module interface using it - Google Patents

Abstract

The invention relates to a DDR and QDR conversion device, and an adapter card, a mainboard and a memory module interface using the same. The DDR and QDR conversion device comprises a QDR interface element, a DDR interface element and a conversion core element. The QDR interface device is used for exchanging signals with the QDR device, and the DDR interface device is used for exchanging signals with the DDR device. The conversion core element converts the instruction and data form of QDR into the instruction and data form of DDR, and converts the instruction and data form of DDR into the instruction and data form of QDR.

Description

DDR and QDR conversion device and adapter card, motherboard and memory module interface using it

The present invention relates to a memory conversion device and a device using it, and in particular to a DDR-QDR conversion device and an adapter card, a motherboard, a memory module and a portable computer motherboard using the same.

Due to the improvement of computer technology, process and packaging technology, not only the processing speed of the central processing unit (CPU, Central Processing Unit) has increased by leaps and bounds, but also many changes have been made in the memory. With the improvement of memory access speed requirements, the commonly used memory has also changed from the initial dynamic random access memory (DRAM), extended data output random access memory (EDO RAM), etc., to the most common synchronous dynamic random access memory (DRAM) today. Access memory (Synchronous Data Rate RAM, hereinafter referred to as SDR random access memory) and double data rate random access memory (Double Data Rate RAM, hereinafter referred to as DDR random access memory). With the improvement of memory access speed, the cost of making various random access memories is relatively high.

Therefore, the present invention proposes a method and structure with a faster access speed than the current memory, which can significantly improve the efficiency of DDR random access memory without consuming too much production cost. This brand-new structure is called quadruple data rate random access memory (Quadruple DataRate RAM, hereinafter referred to as QDR random access memory). However, the present invention includes the formulation of the QDR signal system and the conversion method between DDR and QDR signal systems. The DDR-QDR conversion structure and method proposed by the present invention can be used in all electronic devices that need to use random access memory, such as adapter cards, motherboards, and portable computer motherboards.

The invention proposes a DDR-QDR conversion device, which has a QDR interface element, a DDR interface element, a clock controller, an instruction controller, a state register set and a data conversion device. Wherein, the QDR interface element is used for exchanging signals with the QDR element, and the DDR interface element is used for exchanging signals with the DDR element. The clock controller converts the clock signal sent by the QDR element into the clock used by the conversion device and the DDR element. After obtaining the QDR command signal of the QDR element, the command controller processes the QDR command signal into a corresponding DDR command signal and outputs it to the DDR element. The state register set is used to store the data in the module register set (Mode Register Set, MRS) and the extended module register set (Extended Mode Register Set, EMRS) used by the QDR interface, and provide conversion information to the command controller Appropriate command and data conversion. The data conversion device is used to convert the data type of the QDR into a data type suitable for the DDR, and convert the data type of the DDR into a data type suitable for the QDR.

However, in an embodiment of the present invention, the data conversion device includes a data masking and detection controller, a QDR-to-DDR data converter, and a DDR-to-QDR data converter. Among them, the data shielding and detection controller is used to obtain the QM signal and DQS signal of the QDR component, convert the QM signal into a DDR QM signal and output the DDR QM signal to the DDR component, and convert the DQS signal into a QDR component to extract data from the DDR component data extraction signal. The QDR-to-DDR data converter converts the serial signal of the QDR element into a parallel signal, and transmits the converted parallel signal to two DDR elements separately according to the command of the instruction controller. The DDR-to-QDR data converter converts the data signals of the two DDR elements into serial signals used by the QDR elements, and transmits the converted serial signals to the QDR elements according to the command of the instruction controller.

In summary, the present invention establishes a conversion channel between QDR and DDR, so that DDR can operate normally in a system or device supporting QDR without converting the system or device supporting QDR into a system or device supporting DDR. device, so DDR and QDR can be operated normally at the same time.

Users do not need to purchase new QDR memory modules, and use the device of the present invention in conjunction with existing DDR memory modules to improve the original DDR efficiency to a memory module with QDR efficiency.

For producers, when making printed circuit boards such as adapter cards and main boards, DDR chips with lower cost can be selected. Cooperating with the device of the present invention, the product can also have the data processing efficiency of QDR, so that the produced product It has the same quality and efficacy as existing products in the market, but its production cost can be greatly reduced.

In order to make the above and other objects, features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings as follows:

A brief description of the accompanying drawings:

FIG. 1A is a block diagram of a conversion device according to a first embodiment of the present invention;

FIG. 1B is an embodiment of an operating circuit according to the conversion device of FIG. 1A;

2A is a block diagram of a conversion device according to a second embodiment of the present invention;

Fig. 2B is an embodiment of the operating circuit according to the conversion device of Fig. 2A;

3A is a block diagram of a conversion device according to a third embodiment of the present invention;

Fig. 3B is a first embodiment of the operating circuit according to Fig. 2A conversion device;

Fig. 3C is a second embodiment of the operating circuit according to Fig. 3A conversion device;

FIG. 3D is a third embodiment of the operating circuit of the switching device according to FIG. 2A;

Fig. 4 is the block diagram according to the conversion device of the 4th embodiment of the present invention;

5 is a block diagram according to a fifth embodiment of the present invention;

Fig. 6 is a block diagram according to the sixth embodiment of the present invention;

Fig. 7 is a block diagram according to the seventh embodiment of the present invention;

8 is a block diagram according to an eighth embodiment of the present invention; and

Fig. 9 is a block diagram according to a ninth embodiment of the present invention. Explanation of reference numerals: 10, 20, 30, 52, 62, 70, 80, 92, 1002, 1102, 1202, 1302, 1402: DDR and QDR conversion devices 12, 22, 32, 42: conversion core components 14, 24, 34, 40: QDR interface components 18, 28, 38, 44, 46, 48, 410: DDR interface components 512: adapter card 54, 56: DDR module matrix 612: motherboard 64, 66: DDR DIMM712: memory module 72, 74, 76: DDR memory chipset matrix 812: memory module interface 82, 84: DDR DIMM912: motherboard of portable computer 94, 96: SO-DIMM slot 1000, 1100, 1200, 1300, 1400: QDR components 1004, 1104, 1204, 1304, 1404: SQDR 1006, 1106, 1306: phase locked loop (referred to as PLL) 120, 220, 320: clock controller 122, 222, 322: command controller 124, 224, 324: status register Group 126, 226, 326: Data Converter 50, 60, 90: Chipset 1260, 2260, 3260: Data Masking and Detection Controller 1262, 2262, 3262: DDR to QDR Data Converter 1264, 2264, 3264: QDR to DDR data converter

Example

Please refer to FIG. 1A, which is a block diagram of a conversion device according to a first embodiment of the present invention. The conversion device 10 for DDR and QDR includes a QDR interface component 14 , a DDR interface component 18 and a conversion core component 12 , and the conversion device 10 is named “DQDR” here.

The QDR interface component 14 is between the QDR memory module and the switching core component 12 for exchanging signals. The DDR interface component 18 is interposed between the DDR memory module and the conversion core component 12 for exchanging signals. In Fig. 1A, a block diagram of the conversion core element 12 according to an embodiment of the present invention is also depicted in more detail. In this embodiment, the conversion core component 12 includes a clock controller 120 , an instruction controller 122 , a state register set 124 , and a data conversion device 126 . Wherein, the clock controller 120 converts the clock signals (CKn, CKn#) sent by the QDR memory module into the clock (MCKn) used inside the conversion device 10 and used by the DDR memory module.

The instruction controller 122 is used to receive the QDR instruction (such as including CSn, RAS, CAS, Ban, Can, WE, etc.) transmitted by the QDR memory module, and process the QDR instruction signal into a corresponding DDR instruction (such as a corresponding MCSn, MRAS, MCAS, MBAn, Man, MWE, etc.), and then output to the DDR memory module. And when the command of QDR has access to data, for example, when the QDR command needs to use the read or write command of data, the data conversion device 126 will activate the function control system, these systems include data shielding and detection system, QDR to DDR data conversion system and DDR to QDR data conversion system. In these systems, the data conversion device 126 has the function of converting the data type of QDR into a data type suitable for DDR, and converting the data type of DDR into a data type suitable for QDR. The state register set 124 is used to store data in the Mode Register Set (MRS) and the Extended Mode Register Set (EMRS) used by the QDR interface.

In order to describe the present invention in more detail, in FIG. 1A , a block diagram of the internal circuit of the data conversion device 126 according to an embodiment of the present invention is drawn in more detail. In this embodiment, the data conversion device 126 includes a data masking and detection controller 1260 , a DDR to QDR data converter 1262 and a QDR to DDR data converter 1264 .

When the function control system is activated, that is, when there is a command to read or write data, the data shielding and detection controller 1260 will obtain the QM signal and DQS signal of the QDR memory module, and convert the QM signal into a DDR QM signal It is then input to the DDR memory module, and the DQS signal is converted into a data extraction signal used by the QDR to extract data from the DDR component. When the QDR command signal is a data read command, the QDR-to-DDR data converter 1264 converts the serial signal of the QDR element into a parallel signal, and transmits the converted parallel signal separately to two DDR components. When the QDR command signal is a data write command, the DDR-to-QDR data converter 1262 will convert the data signals of the two DDR elements into serial signals used by the QDR element, and convert the obtained serial signals according to the command of the instruction controller 122. The serial signal is transmitted to the QDR element.

Because QDR sends four bits (bit) in one cycle (cycle), and DDR can only send two bits in one cycle, so QDR is all superior to DDR in processing speed and efficiency, in the above-mentioned embodiment, is The DDR-QDR conversion device is designed in such a way that one QDR element corresponds to two DDR elements. But those who are familiar with this technology should know that the conversion device can also be designed in the way that one QDR element corresponds to one DDR element, but obviously its efficiency will be reduced. To maintain the same efficiency, the frequency of DDR must be increased to It is about twice that of QDR, so that DDR can output the same bit as QDR, but it is also difficult to increase the frequency of DDR, so the required cost will be relatively increased, so the present invention is still applied to using two groups of DDR modules to Efficiency in generating QDRs.

Please refer to FIG. 1B , which is a practical circuit diagram of the conversion device 10 according to the embodiment of the present invention shown in FIG. 1A . The conversion device 10 in FIG. 1A can be used in FIG. 1B , wherein when writing, the DQS signal is input from the QDR element 1400 to the DDR and QDR conversion device 1402 . When reading, the QDR element 1400 will input the DQS signal to the conversion device 1402 of DDR and QDR, and then after being processed by the DQDR 1404 of the conversion device 1402 of DDR and QDR, it will finally be input to the QDR element 1400. Among them, those who are familiar with this technology It can be seen that the conversion device 10 does not need to use an external phase-locked loop and double the clock signal, and the DQS signal is directly transmitted.

For example: when the QDR element 1400 wants to access data to the DDR, first the QDR element 1400 will send an access command, then via the QDR interface element 14 shown in Figure 1A to the command controller 122 of the conversion device 10, at this time After the command controller 122 receives the access command of the QDR element 1400, it processes it into a corresponding DDR command, and then the command status data register 124 transfers the data in the module register group and the extended module register group used by the QDR interface 14 to store and activate the function control system. After the function control system is activated, the data shielding and detection controller 1260 will read the DM signal and the DQS signal of the QDR element 1400, and the data shielding and detection controller 1260 will convert the DM signal of the QDR element 1400 into a DDR DM signal, and The DQS signal of the QDR element 1400 is converted into a data extraction signal used by the QDR to extract data from the DDR element.

When the access command of the QDR element 1400 is a data write command, the serial signal of the QDR element 1400 will be converted into a parallel signal via the QDR-to-DDR data converter 1264 shown in FIG. command to send the converted parallel signal to two DDR components separately. When the access command of the QDR element 1400 is a data read command, the DDR-to-QDR data converter 1262 will convert the data signal of the two DDR elements into a serial signal used by the QDR element, and according to the command of the instruction controller 122 The converted serial signal is transmitted to the QDR element 1400 .

Please refer to FIG. 2A , which is a block diagram of a conversion device according to a second embodiment of the present invention. The functions of all devices are the same as those of the device in Fig. 1A, the only difference is that when the data shielding and detection controller 2260 obtains the QM and DQS signals of the QDR element, the QM signal is converted into a DDR QM signal and output to the DDR element, and the DQS The signal is converted into the data extraction signal used by the QDR element to extract data from the DDR element, and when the DQS signal must be returned to the QDR element, the returned DQS signal is generated based on the double clock signal.

Please refer to FIG. 2B, which is an embodiment of the operating circuit of the conversion device according to FIG. 2A. The conversion device 20 of the present invention can be used in FIG. 2B. In this figure, the direction from the QDR element 1200 to the DDR and QDR conversion device 1202 is writing, and the direction from the DDR and QDR conversion device 1202 to the QDR element 1200 is reading. If the returned DQS signal is generated by twice the clock signal, the DQS signal is input from the QDR element 1200 to the conversion device 1204 for DDR and QDR during writing. When reading, the DQDR 1204 of the DDR and QDR conversion device 1202 converts the double clock signal provided by the QDR element 1200 into a DQS signal, and then outputs it to the QDR element 1200.

Please refer to FIG. 3A , which is a block diagram of a conversion device according to a third embodiment of the present invention. The functions of all devices are the same as those of the conversion device in FIG. 1A , the only difference is a phase-locked loop (PhaseLock Loop, referred to as PLL hereinafter) 321 and a data shielding and detection controller 3260 . After receiving the clock signal, the phase-locked loop 321 can generate an output clock signal whose frequency is a multiple of the frequency of the input clock signal, for example, a clock signal twice that of the present embodiment. When the data shielding and detection controller 3260 obtains the QM and DQS signals of the QDR element, it converts the QM signal into a DDR QM signal and outputs it to the DDR element, and converts the DQS signal into a data extraction signal used by the QDR element to extract data from the DDR element. , and when it is necessary to return the DQS signal to the QDR element, the returned DQS signal is generated according to the clock signal output by the phase-locked loop 321 .

Please refer to FIG. 3B and FIG. 3D , which are practical implementation circuit embodiments of the converting device 20 in FIG. 2A according to an embodiment of the present invention. The conversion device 20 of the present invention can be used in FIG. 3B. In this figure, the direction from the QDR device 1000 to the DDR and QDR converting device 1202 is writing, and the direction from the DDR and QDR converting device 1202 to the QDR device 1000 is reading. 3B and 3D mainly illustrate that the PLL 321 in the conversion device 20 of FIG. 2A can be built in the DDR and QDR conversion device 1002, or built in the DQDR 1004, or provided externally.

In one embodiment, if the phase-locked loop 1006 is inside the conversion device 1002 of DDR and QDR, and generates an output clock signal with twice the clock signal to the data conversion device, when writing, the QDR The component 1000 outputs the DQS signal to the conversion device 1002 of DDR and QDR. When reading, the DQDR 1004 of the DDR and QDR conversion device 1002 converts the return clock signal provided by the phase-locked loop 1006 into a DQS signal, and then outputs it to the QDR element 1000.

In another embodiment, if the phase-locked loop 1106 is inside the DQDR 1104, please refer to FIG. 3C , which is an actual implementation circuit embodiment of the conversion device 30 in FIG. 3A according to an embodiment of the present invention. The clock signal generated by the phase-locked loop 1106 is output to the data conversion device. When writing, the DQS signal is input from the QDR element 1100 to the conversion device 1102 of DDR and QDR. When reading, the DQDR 1104 of the DDR and QDR conversion device 1102 converts the return clock signal provided by the phase-locked loop 1106 into a DQS signal, and then outputs it to the QDR element.

In another embodiment, if the phase-locked loop 1306 is provided by an external circuit, please refer to FIG. 3D , which is a practical circuit embodiment of the conversion device 20 in FIG. 2A according to an embodiment of the present invention. The clock signal generated by the PLL 1306 is input to the conversion device 1302 for DDR and QDR. When writing, the DQS signal is input from the QDR element 1300 to the conversion device 1302 of DDR and QDR. When reading, the DQDR 1304 of the DDR and QDR conversion device 1302 converts the return clock signal provided by the phase-locked loop 1306 into a DQS signal, and then outputs it to the QDR element.

Please refer to FIG. 4 , which is a block diagram of an embodiment of the present invention. Among them, the conversion core component is used to convert the command and data form of QDR into the command and data form of DDR, input to the DDR component through DDR interface components 44, 46, and convert the command and data form of DDR into the command and data form of QDR , transmitted to the QDR element through the QDR interface element 40 .

Next, please refer to FIG. 5 , which is an embodiment of applying the memory conversion device of the present invention to an adapter card, that is, the fifth embodiment of the present invention. The adapter card 512 includes a chipset 50 supporting the use of QDR modules, a conversion device 52 and two DDR module matrices 54 , 56 . Wherein, in order to make the block diagram obvious and easy to understand, the QDR interface components and DDR interface components of the conversion device 52 are only represented by connecting lines connected to the chipset 50 and the DDR module matrix 54 , 56 respectively. With this device connection, the DDR module matrix can be used on the adapter card 512 that supports QDR modules.

Next, please refer to FIG. 6 , which is an embodiment of applying the memory conversion device of the present invention to a motherboard, that is, the sixth embodiment of the present invention. The motherboard 612 includes a chipset 60 supporting QDR modules, a conversion device 62 and two DDR DIMMs 64, 66. Wherein, in order to make the block diagram clearer, the QDR interface components and DDR interface components of the conversion device 62 are only represented by the connection lines connected to the chipset 60 and the DDR DIMMs 64 and 66 respectively. With this device connection, DDR DIMMs can be used on the motherboard 612 that supports QDR DIMMs.

Next please refer to FIG. 7 , which is an embodiment of applying the memory conversion device of the present invention to a memory module (Memory Module), which is the seventh embodiment of the present invention. In the memory module 712, a conversion device 70 and a plurality of DDR memory chipset matrixes 72-76 are included. Wherein, in order to make the block diagram clearer, the QDR interface element and the DDR interface element of the conversion device 70 are respectively represented by the connection lines connecting the external device and a plurality of DDR memory chipset matrixes 72-76. With such a device connection mode, the DDR memory chipset matrix can be used on the memory module 712 supporting the QDR memory chipset matrix.

Next please refer to FIG. 8 , which is a block diagram according to an eighth embodiment of the present invention. In the memory module interface 812, a conversion device 80 and two DDR DIMMs 82, 84 are included. Wherein, in order to make the block diagram clearer, the QDR interface element and the DDR interface element of the conversion device 80 are respectively represented by the connection lines connecting the external device and the two DDR DIMMs 82 and 84. With this device connection, DDR DIMMs can be used on the memory module interface 812 that supports QDR DIMMs.

Please refer to FIG. 9, which is a block diagram of a ninth embodiment of the present invention. In the motherboard 912 of the portable computer, a chipset 90 supporting QDR modules, a conversion device 92 and two DDR DIMM slots 94, 96 are included. Wherein, in order to make the block diagram clearer, the QDR interface components and DDR interface components of the conversion device 92 are only represented by the connection lines connected to the chipset 90 and the DDR DIMM slots 94, 96 respectively. With the connection mode of this device, just can use DDR DIMM slot on the motherboard 912 of the portable computer that supports QDR DIMM slot.

In summary, the present invention establishes a conversion channel between QDR and DDR, which not only enables DDR and QDR to operate normally at the same time, but also maintains the data processing efficiency of QDR when only DDR memory is used.

Users do not need to purchase a new QDR memory module. Using the device of the present invention in combination with an existing DDR memory module, the original DDR efficiency can be improved to a memory module with QDR efficiency, and the existing DDR memory module can also be used. The DDR memory module, the device of the present invention and the QDR memory module are used simultaneously to further improve the efficiency of the system.

For producers, when making memory modules and adapter cards, they can choose DDR chips with lower cost. Cooperating with the device of the present invention, the products can also have the data processing efficiency of QDR. Some QDR products have the same quality and efficacy, but their production cost can be greatly reduced. And when making main board, use device of the present invention can provide user no matter under the situation of simultaneously using DDR and QDR module, or can reach the efficiency of QDR under the situation of only using DDR module, therefore can improve the competitiveness of product .

Although the present invention has been described as above with the embodiments, it is not intended to limit the present invention. Anyone familiar with this technology can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be determined by the claims.

Claims (14)

1. the conversion equipment of DDR and QDR is characterized by: comprising:

One QDR interface element is used for carrying out signal exchange with the QDR element;

One ddr interface element is used for carrying out signal exchange with the DDR element;

One clock controller is used for the clock conversion of signals that the QDR element is delivered to is become this conversion equipment and the employed operation clock signal of DDR element;

One status register group is used for storing the QDR element state;

One DTU (Data Transfer unit) is used for the data kenel of QDR is converted to the data kenel that is applicable to DDR, and the data kenel of DDR is converted to the data kenel that is applicable to QDR; And

One instruction control unit after obtaining a QDR command signal of QDR element, is processed into a corresponding DDR command signal with this QDR command signal, and exports the DDR element to.

2. the conversion equipment of DDR as claimed in claim 1 and QDR is characterized by: this DTU (Data Transfer unit) comprises:

One data mask and detection controller, be used for obtaining the QM signal and the DQS signal of QDR element, the QM signal is changed into DDR QM signal and DDR QM signal is inputed to the DDR element, and transfer the DQS signal to the QDR element extracts data to the DDR element a data extract signal;

One QDR to DDR data converter converts the serial signal of QDR element to parallel signal, and according to the order of this instruction control unit, and the parallel signal of conversion gained separately is transferred to two DDR elements; And

One DDR to QDR data converter changes into the employed serial signal of QDR element with the data-signal of two DDR elements, and transfers to the QDR element according to the serial signal that the order of this instruction control unit will be changed gained.

3. the conversion equipment of DDR as claimed in claim 1 and QDR is characterized by: this DTU (Data Transfer unit) comprises:

One data mask and detection controller, obtain QM signal and DQS signal that the QDR element is transmitted, the QM signal is changed into DDR QM signal and exports the DDR element to, transfer the DQS signal to the QDR element extracts data to the DDR element a data extract signal, and in the time must returning the DQS signal, produce the DQS signal of passback according to these clock signals of two times to the QDR element;

One QDR to DDR data converter converts the serial signal of QDR element to parallel signal, and according to the order of this instruction control unit, and the parallel signal of conversion gained separately is transferred to two DDR elements; And

One DDR to QDR data converter changes into the employed serial signal of QDR element with the data-signal of two DDR elements, and transfers to the QDR element according to the serial signal that the order of this instruction control unit will be changed gained.

4. the conversion equipment of DDR as claimed in claim 1 and QDR is characterized by: this DTU (Data Transfer unit) comprises:

One phase-locked loop is used for receiving this clock signal, and the generation frequency is a built-in function clock signal of this clock signal frequency twice;

One data mask and detection controller, be used for obtaining a QM signal and the DQS signal of this QDR, this QM signal is changed into a DDR QM signal and inputs to this DDR element, transfer this DQS signal to this QDR element extracts data to this DDR element a data extract signal, and in the time must returning this DQS signal, produce the DQS signal of passback according to this built-in function clock signal to this QDR element;

One QDR to DDR data converter becomes a parallel signal with a serial conversion of signals of this QDR element, and according to the order of this instruction control unit, and this parallel signal of conversion gained separately is transferred to two these DDR elements; And

One DDR to QDR data converter changes into employed this serial signal of this QDR element with the data-signal of two these DDR elements, and transfers to this QDR element according to this serial signal that the order of this instruction control unit will be changed gained.

5. the conversion equipment of DDR and QDR, be applicable between a QDR interface element and the ddr interface element, it is characterized by: this QDR interface element is used for carrying out signal exchange with a QDR element, and this ddr interface element is used for carrying out signal exchange with a DDR element, and this conversion equipment comprises:

One clock controller is used for receiving the clock signal that this QDR element is exported, and converts the employed clock signal of this conversion equipment to;

One instruction control unit after being used for obtaining a QDR command signal of this QDR element, is processed into a corresponding DDR command signal with this QDR command signal, and exports this DDR element to; And

One DTU (Data Transfer unit), be couple to this QDR interface element, this ddr interface element and this instruction control unit, a control signal of exporting according to this instruction control unit, the data kenel that is applicable to this QDR element is converted to the data kenel that is applicable to this DDR element, and will be applicable to that the data kenel of this DDR element is converted to the data kenel that is applicable to this QDR.

6. the conversion equipment of DDR as claimed in claim 5 and QDR is characterized by: this DTU (Data Transfer unit) comprises:

One data mask and detection controller, be used for obtaining a QM signal and a DQS signal of this QDR element, this QM signal is changed into a DDR QM signal that is applicable to this DDR element and exports this DDR element to, and transfer the DQS signal to this QDR element extracts data to this DDR element a data extract signal;

One QDR to DDR data converter will be become a parallel signal by the serial conversion of signals that this QDR element is exported, and according to the order of this instruction control unit, and this parallel signal of conversion gained is transferred to those DDR elements; And

One DDR to QDR data converter changes into employed this serial signal of this QDR element with the data-signal of those DDR elements, and transfers to this QDR element according to this serial signal that the order of this instruction control unit will be changed gained.

7. the conversion equipment of DDR as claimed in claim 5 and QDR is characterized by: this DTU (Data Transfer unit) comprises:

One data mask and detection controller, be used for obtaining a QM signal and the DQS signal that this QDR element is transmitted, this QM signal is changed into a DDRQM signal that is applicable to this DDR element and exports this DDR element to, transfer this DQS signal to this QDR element extracts data to this DDR element a data extract signal, and in the time must returning this DQS signal, produce this DQS signal of passback according to these clock signals of two times to the QDR element;

One QDR to DDR data converter, the serial conversion of signals that this QDR element is exported become a parallel signal, and according to the order of this instruction control unit, and the parallel signal of conversion gained separately is transferred to those DDR elements; And

One DDR to QDR data converter changes into employed this serial signal of this QDR element with the data-signal of those DDR elements, and transfers to this QDR element according to this serial signal that the order of this instruction control unit will be changed gained.

8. the conversion equipment of DDR as claimed in claim 5 and QDR is characterized by: this DTU (Data Transfer unit) comprises:

One phase-locked loop receives this clock signal, and produces the passback clock signal that frequency is this clock signal frequency twice;

One data mask and detection controller, be used for obtaining QM signal and the DQS signal of this QDR, the QM signal is changed into DDR QM signal and inputs to the DDR element, transfer the DQS signal to the QDR element extracts data to the DDR element a data extract signal, and in the time must returning the DQS signal, produce the DQS signal of passback according to this passback clock signal to the QDR element;

One QDR to DDR data converter converts the serial signal of QDR element to parallel signal, and according to the order of this instruction control unit, and the parallel signal of conversion gained separately is transferred to two DDR elements; And

One DDR to QDR data converter changes into the employed serial signal of QDR element with the data-signal of two DDR elements, and transfers to the QDR element according to the serial signal that the order of this instruction control unit will be changed gained.

9. the conversion equipment of DDR and QDR is characterized by: comprising:

One QDR interface element is used for carrying out signal exchange with the QDR element;

One ddr interface element is used for carrying out signal exchange with the DDR element; And

One conversion core parts, the instruction and the data mode that convert instruction and the data mode of QDR to DDR, reach the DDR element by this ddr interface element, and, reach the QDR element by this QDR interface element with instruction and data mode that instruction and the data mode of DDR converts QDR to.

10. an adapter that uses the conversion equipment of DDR and QDR is applicable on the circuit board of supporting the QDR module, it is characterized by: have a chipset of supporting QDR on this circuit board at least, this adapter comprises at least:

At least one DDR modular matrix; And

The conversion equipment of one DDR and QDR comprises:

One QDR interface element is used for carrying out signal exchange with this chipset;

One ddr interface element is used for carrying out signal exchange with this DDR modular matrix;

One conversion core parts, instruction and data mode with instruction and the data mode of QDR converts DDR to are sent to this DDR modular matrix by this ddr interface element,

And the instruction and the data mode that convert instruction and the data mode of DDR to QDR,

Be sent to this chipset of supporting QDR by this QDR interface element.

11. a mainboard that uses the conversion equipment of DDR and QDR is characterized by: comprising:

Chipset supports to use the QDR module; And

The conversion equipment of one DDR and QDR comprises:

At least one DDR DIMM;

The conversion equipment of one DDR and QDR comprises a QDR interface element, is used for carrying out signal exchange with this chipset; One ddr interface element is used for carrying out signal exchange with this DDR DIMM; Reach conversion core parts, the instruction and the data mode that convert instruction and the data mode of QDR to DDR, be sent to this DDR DIMM by this ddr interface element, and, be sent to this chipset by this QDR interface element with instruction and data mode that instruction and the data mode of DDR converts QDR to.

12. a memory modules that uses the conversion equipment of DDR and QDR is applicable to that it is characterized by: this memory modules comprises on the internal memory of supporting the QDR memory modules:

At least one DDR memory chip group matrix; And

The conversion equipment of one DDR and QDR comprises a QDR interface element, carries out signal exchange with this internal memory; One ddr interface element carries out signal exchange with this DDR memory chip group matrix; Reach conversion core parts, the instruction and the data mode that convert instruction and the data mode of QDR to DDR, be sent to this DDR memory chip group matrix by this ddr interface element, and, be sent to this internal memory by this QDR interface element with instruction and data mode that instruction and the data mode of DDR converts QDR to.

13. a memory module interface that uses the conversion equipment of DDR and QDR is characterized by: comprising:

At least one DDR DIMM; And

The conversion equipment of one DDR and QDR comprises a QDR interface element, carries out signal exchange with this memory module interfaces; One ddr interface element carries out signal exchange with this DDR DIMM; Reach conversion core parts, the instruction and the data mode that convert instruction and the data mode of QDR to DDR, be sent to this DDR DIMM by this ddr interface element, and, be sent to this memory module interfaces by this QDR interface element with instruction and data mode that instruction and the data mode of DDR converts QDR to.

14. a portable computer mainboard that uses the conversion equipment of DDR and QDR is characterized by: comprising:

One chipset supports to use the QDR module; And

The conversion equipment of one DDR and QDR comprises a QDR interface element, is used for carrying out signal exchange with this chipset; One ddr interface element provides at least one SO-DIMM slot; One conversion core parts, the instruction and the data mode that convert instruction and the data mode of QDR to DDR, be sent to this SO-DIMM slot by this ddr interface element, and, be sent to this chipset by this QDR interface element with instruction and data mode that instruction and the data mode of DDR converts QDR to.

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