CN1387306A - Tree-level switching transformer - Google Patents

Abstract

A three-level, frequency-stabilized, soft-switching isolated converter provides zero voltage switching (ZVS) conditions for all primary switches to conduct over a wide range of input voltages and output loads. These converters achieve ZVS with minimal duty cycle loss and circulating current. The ZVS of the primary switch is achieved by the energy stored in an inductor on the primary of the isolation transformer. The inductor and transformer are arranged so that a change in the phase shift between the outer and inner switch pairs of the four switches in series changes the volt-second product on the transformer winding and the inductor winding in opposite directions. In some embodiments, the primary side inductor is coupled to an inductor having two windings, while in other embodiments the inductor has only one winding.

Description

Three-Stage Soft-Switching Converter

Cross References to Related Applications

This application is a patent application filed on August 31, 2000, with serial number 09/652869, entitled "Soft-switching full-bridge converter", and a patent application with serial number -______, filed on February 5, 2001, named Continuation of Patent Application for "Soft-Switching Full-Bridge Converter".

technical field

The invention relates to a power converter, in particular to a high-voltage power converter.

Background technique

Typically, high voltage power conversion applications require switching elements with high voltage ratings because the voltage rating of a switch is determined by the input and/or output voltage of the converter. For example, in a conventional isolated buck converter, ie in a transformer isolated converter with an output voltage higher than the input voltage, the voltage stress on the primary switching element is determined by the input voltage and the layout of the converter. Primary switches in bridge layouts, such as half-bridge and full-bridge converters, experience a minimum voltage stress equal to the input voltage. However, the voltage stress of a single-ended layout, such as that on a single-switch forward and flyback converter, is significantly higher than the input voltage.

Achieving high efficiency for high voltage applications is a major design challenge, requiring optimization of conduction and switching losses through careful selection of converter layout and switching element characteristics. That is, semiconductor switches with higher rated voltages, such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), IGBTs (Insulated Gate Bipolar Transistors) and BJTs (Bipolar Junction Transistors) with their lower rated Compared with their voltage counterparts, they exhibit larger conduction losses. In addition, switching losses also increase in high voltage applications. In general, switching losses can be reduced or even eliminated by employing various resonant or soft-switching topologies. However, options for reducing conduction losses are very limited. In fact, once the layout and switches with the lowest conduction losses for the desired voltage rating are selected, the only way to further reduce conduction losses is to use a circuit with a lower voltage rating and therefore a higher layout of switches with low conduction losses. In a class of circuits known as multilevel converters, multilevel converters are a natural choice for high-voltage applications because the primary switches operate with much lower voltage stress than the input voltage. To date, a large number of multilevel DC/AC and DC/DC converters have been disclosed in the literature.

As an example, Figure 1 shows a three-level, zero-voltage switching (ZVS) DC/DC converter that has been used in "DC/DC converters for high input voltages: with a peak value of V _IN /2 Four switches of voltage, capacitive forced disconnection, and zero voltage switch-on" were introduced in the article by Barbi et al. and published in IEEE Power Electronics Specialists' Conf. Rec, pp.1-7, 1998. The converter in Figure 1 provides ZVS conduction of all four primary switches and frequency stabilization with pulse width modulation (PWM) operation with voltage stress on the primary switches limited to V _IN /2. However, since the circuit in Figure 1 relies on the energy stored in the leakage inductance of the transformer TR to establish the ZVS condition for switches _Q2 and _Q4 , switches _Q2 and Q4 can only be achieved within a very limited load range of full load. A ZVS of ₄ , unless the leakage inductance is significantly increased, or a sizable external inductance in series with the transformer primary is added. It should be noted that in Figure 1, the inductance of the inductor L represents the sum of the leakage inductance of the transformer and the external additional inductance (if any). The addition of inductance in series with the primary winding has a detrimental effect on circuit performance as it reduces the effective secondary duty factor and produces severe parasitic ringing due to the interaction of the inductance with the junction capacitance of the non-conducting secondary rectifier ring. In general, the reduction in secondary duty cycle needs to be compensated by reducing the turns ratio of the transformer, which in turn increases the primary conduction losses because the reflected load current into the primary of the transformer is also increased. In order to attenuate the spurious ringing, a heavy secondary muffler circuit is required, further deteriorating the conversion efficiency.

As another example, Figure 2 shows the three-level, soft-switching DC/DC converter described in "A Zero-Voltage Switching Three-Level DC/DC Converter" by Canales et al. Disclosed in Proceedings of IEEE International Telecommunications Energy Conference (INIELEC), pp.512-517, 2000. The three-level converter in Figure 2 is also characterized by ZVS conduction of all switches Q1 to Q4. Furthermore, frequency stabilized operation with phase shift control is also featured by the use of a "crossover capacitance" C _B . The circuit of Figure 2 uses energy stored in the output filter inductor to achieve ZVS for the outer switches Q1 and Q4, and uses energy stored in the leakage inductance of the transformer to achieve ZVS for the inner switches Q2 and Q3. Therefore, the ZVS of the outer switch can be achieved over a wide load range, while the ZVS range of the inner switch is very limited unless the leakage inductance is significantly increased, and/or a large external inductance in series with the primary winding is added. As mentioned above, increased leakage inductance and/or additional external inductors have detrimental effects on circuit performance.

Recently, a soft-switching full-bridge technique was disclosed in a patent application filed by Jang and Jovanovic, which achieves ZVS of the primary switch over the entire load and linear range with practically no secondary duty cycle loss and with minimal cycle energy , the patent application was filed on August 31, 2000, and its serial number is 09/652869. Figure 3 shows one implementation of this technique. The circuit in Figure 3 utilizes the energy stored in the magnetizing inductance of the coupled inductor _LC to discharge the capacitance across the switch to be turned on, thus achieving ZVS. By properly choosing the value of the magnetizing inductance of the coupled inductor, the primary switch in the converter of Figure 3 can achieve ZVS even when there is no load. Since in the circuit of Figure 3, the energy required to establish the ZVS condition at light load does not need to be stored in the leakage inductance, the transformer leakage inductance can be minimized. As a result, secondary duty cycle losses are minimized, which maximizes the transformer turns ratio, thereby minimizing primary conduction losses. In addition, the minimized leakage inductance of the transformer significantly reduces secondary ringing caused by resonance between the leakage inductance and the junction capacitance of the rectifier, thereby greatly reducing the power of the noise-cancelling circuits normally used to attenuate the ringing consume.

In the present invention, the concept used to realize the ZVS of the primary switch in the converter shown in Fig. 3 is extended to a three-level converter.

Contents of the invention

In the present invention, a plurality of three-level, frequency-stabilized, soft-switching isolated converters are disclosed that can achieve substantially zero-voltage turn-on of the primary switch over a wide range of load currents and input voltages. Typically, these converters use an inductor on the primary of the isolation transformer to establish the ZVS condition of the primary switch. In some embodiments, the primary inductor couples an inductor with two windings; while in other embodiments, the inductor has only one winding. The inductor and transformer are arranged in a circuit such that a change in phase shift between the outer and inner pair of switches in series of four switches changes the volt-second product on the transformer winding and the inductor winding in opposite directions. Specifically, if the phase shift between the inner and outer switch pairs is changed such that the volt-second product on the transformer winding decreases, the volt-second product on the inductor winding increases, and vice versa.

In the circuit of the present invention, since the energy stored in the inductor available for ZVS increases as the load current increases and/or the input voltage increases, the circuit of the present invention can operate at both input voltage and load current, including very Achieving ZVS over a wide range.

Furthermore, since the energy used to generate the ZVS condition at light loads is not stored in the leakage inductance of the transformer, the leakage inductance of the transformer can be minimized, thereby also minimizing the duty cycle loss on the transformer secondary. As a result, the converter of the present invention can be operated at the largest possible duty cycle, thereby minimizing conduction losses on the primary switch and voltage stress on components on the secondary side of the transformer, improving conversion efficiency. In addition, due to the minimized leakage inductance, the secondary parasitic ringing caused by the resonance between the leakage inductance and the junction capacitance of the rectifier is also minimized, thereby also reducing the power of the noise reduction circuit usually required to attenuate the ringing consume.

The circuit of the present invention can be implemented as a DC/DC converter, or as a DC/AC inverter. If implemented as a DC/DC converter, any type of secondary rectifier can be used, for example, a full-wave rectifier with a center-tapped secondary winding, a full-wave rectifier with a current doubler, or a full-bridge full-wave rectifier.

Description of drawings

Fig. 1 shows frequency stabilization, PWM, ZVS, three-level DC/DC converter: (a) power stage; (b) timing diagram of primary switch (prior art);

Fig. 2 shows frequency stabilization, phase shifting, ZVS, three-level DC/DC converter: (a) power stage; (b) timing diagram of switch (prior art);

Figure 3 shows a full-bridge converter (prior art) using coupled inductors to achieve ZVS for the primary switch over a wide range of input voltage and output current;

Fig. 4 shows a preferred embodiment of the soft-switching DC/DC three-level converter according to the present invention;

Fig. 5 is a simplified circuit of a preferred embodiment of the soft-switching DC/DC converter shown in Fig. 4;

Figure 6(a)-(1) shows several layout stages of the soft-switching three-level DC/DC converter in Figure 4 during the switching cycle;

Figure 7(a)-(o) shows the main waveforms of the soft-switching three-stage DC/DC converter in Figure 4: (a) drive signal of switch S1; (b) drive signal of switch S2; (c) switch S3 (d) the driving signal of the switch K4; (e) the voltage waveform v _s1 at the two ends of the switch S1; (f) the voltage waveform v _s2 at the two ends of the switch S2; (g) the voltage waveform v _s3 at the two ends of the switch S3; ( h) voltage waveform v _s4 across switch S4; (i) primary voltage v _p ; (j) voltage v _AB across coupled inductor; (k) primary current waveform i _P ; (I) excitation current waveform i _MC ; (m) current i ₁ ; (n) current i ₂ ; (o) voltage v _s at the input of the output filter;

Figure 8 shows another preferred embodiment of the invention using a transformer with a center tapped primary winding;

Figure 9 shows yet another preferred embodiment of the invention using a single winding inductor;

Figure 10 shows an embodiment of the invention with a pre-charge circuit for capacitors C _B1 and C _B2 .

Detailed ways

Fig. 4 shows a preferred preferred embodiment of a three-stage soft-switching DC/DC converter according to the present invention. The three-level commutation converter in Figure 4 consists of: four series-connected primary switches S ₁ to S ₄ , rail-splitting capacitors C _c1 and C _C2 , "crossover capacitors" C _B1 and C _B2 , isolation transformer TR, and coupled inductor L _C . In this embodiment, the load is coupled to the converter via a full-wave rectifier connected to the center-tapped secondary of the transformer. In addition, the clamping diodes D _C1 and D _C2 are used to clamp the voltages of the outer switches S ₁ and S ₄ to V _IN /2 respectively after the outer switches S ₁ and S ₄ are turned off, and may be finally controlled by the circuit A blocking capacitor C _B is used to prevent transformer saturation in the event of parasitic-generated volt-second imbalances on the transformer windings and mismatches in switching characteristics and timing signals.

It should be noted that in the embodiment in Fig. 4, the secondary output circuit is implemented as a full-wave rectifier with a center-tapped secondary winding. However, the secondary output circuit in the implementation of the DC/DC converter of the present invention can also be implemented with any type of rectifier, such as a full-wave rectifier with a current doubler, or a full-bridge full-wave rectifier. In addition, the converter of the present invention can also be implemented as a DC/AC inverter, that is, no rectifier circuit is provided between the secondary winding of the transformer and the load.

In order to facilitate the description of the operation of FIG. 4, FIG. 5 shows a simplified circuit diagram. In the simplified circuit diagram, it is assumed that the inductance of the output filter _LF is large enough that the output filter can be modeled as a constant current source whose amplitude is equal to the output current I _O during one switching cycle. Furthermore, assume that the capacitances of capacitors C _C1 and C _C2 forming a capacitive divider that divides the input voltage in half are so large that capacitors C _C1 and C _C2 can be driven by voltage sources V ₁ =V _IN /2 and V 2 =V _IN /2 analog. Likewise, assume that the capacitance across capacitors C _B1 and C _B2 is large enough that the capacitors can be modeled as constant voltage sources C _CB1 and C _CB2 , respectively. Due to the coupled inductor winding and transformer winding's The average voltage is zero, and since the switch pair in each bridge lead operates with a 50% duty cycle when one phase-shifted control is used, the magnitude of the voltage sources V _CB1 and V _CB2 in Figure 5 is equal to _V / 4, that is, V _CB1 =V _CB2 =V _IN /4.

To further simplify the analysis of the operation of the circuit shown in Figure 4, it can also be assumed that the resistance of the conducting semiconductor switch is zero and the resistance of the non-conducting switch is infinite. Also, ignore the leakage inductance of the transformer TR and coupled inductor _LC , as well as the magnetizing inductance of the transformer TR, since they have little effect on the circuit operation. However, the magnetizing inductance of the coupled inductor L _C and the capacitance of the primary switches C ₁ -C ₄ cannot be ignored in the analysis because they play important roles in the circuit operation. Therefore, in Fig. 5, the coupled inductance L _C is modeled as an ideal transformer with turns ratio n _1c = 1, and has a magnetizing inductance L _CM in parallel with windings AC and CB connected in series, while transformer TR consists only of turns with than ideal transformer simulation of n _TR . It should be noted that the magnetizing inductance L _CM of inductor L _C represents the inductance measured between terminals A and B when terminal C is open circuited.

Referring to FIG. 5, the following relationship can be established between currents.

i _p =i _p1 +i _p2 (1)

i ₁ =i _p1 +i _MC (2)

i ₂ =i _p2 -i _MC (3)

Since the winding AC of the coupled inductor L _C has the same number of turns as the winding CB, it must be

i _p1 =i _p2 (4)

Substituting equation (4) into equations (1)-(3) gives $i_{\mathrm{<figure-callout\; id="1"\; label="p"\; filenames="A0210841100224.png,A0210841100261.png"\; state="\{\{state\}\}">p</figure-callout>}1}={\mathrm{<figure-callout\; id="2"\; label="i\; p"\; filenames="A0210841100211.png,A0210841100221.png"\; state="\{\{state\}\}">i</figure-callout>}}_p=\frac{{\mathrm{<figure-callout\; id="2"\; label="i\; p"\; filenames="A0210841100211.png,A0210841100221.png"\; state="\{\{state\}\}">i</figure-callout>}}_p}{2},---\left(5\right)$ ${\mathrm{<figure-callout\; id="1"\; label="i"\; filenames="A0210841100224.png,A0210841100261.png"\; state="\{\{state\}\}">i</figure-callout>}}_1=\frac{{\mathrm{<figure-callout\; id="2"\; label="i\; p"\; filenames="A0210841100211.png,A0210841100221.png"\; state="\{\{state\}\}">i</figure-callout>}}_p}{2}+i_{\mathrm{MC}},---\left(6\right)$ ${\mathrm{<figure-callout\; id="2"\; label="i"\; filenames="A0210841100211.png,A0210841100221.png"\; state="\{\{state\}\}">i</figure-callout>}}_2=\frac{i_p}{2}-i_{\mathrm{MC}},-----\left(7\right)$

From equations (6) and (7), it can be seen that the currents i ₁ and i ₂ consist of two components: a primary current component i _p /2 and a magnetizing current component i _MC . The primary current component is directly dependent on the load current, while the magnetizing current component is not directly dependent on the load, but on the volt-second product across the magnetizing inductance. That is, the change in magnetizing current with load current occurs only if the phase shift between the turn-on instants of the outer switches _S1 and _S4 and the corresponding inner switches _S2 and _S3 is changed to maintain output regulation. Generally, at light loads, ie when the load drops to no load, there is a larger change in phase shift with load than at heavier loads. In the current of Figure 4, since the phase shift increases as the load approaches zero, the volt-second product of _LMC also increases, allowing the circuit in Figure 4 to exhibit a maximum magnetizing current at no load, enabling no-load ZVS.

Since the magnetizing current i _MC does not affect the load current, as seen in Figure 5, it represents the circulating current. In general, this circulating current and the energy associated with it should be minimized to reduce losses and maximize conversion efficiency. Since the volt-second product of _LMC exhibits an inverse dependence on load current, the current in Figure 4 circulates less energy at full load than at light load, thus exhibiting ZVS over a wide load range of minimum circulating current feature.

It can also be seen from Figure 5 that

v _AB = v _AC + v _CB (8)

Since the two windings of the coupled inductor L _C have the same number of turns, i.e. since the turns ratio n _LC =1 of _LC , there must be

v _AC = v _CB (9)

or $v_{\mathrm{AC}}=v_{\mathrm{CB}}=\frac{v_{\mathrm{AB}}}{2}------\left(10\right)$

Generally, for a frequency-stabilized phase-shift control voltage, v _AB is a rectangular wave voltage comprising alternating positive and negative pulses of amplitude V _IN /2 separated by a time interval of v _AB =0. According to equation (10) and with reference to FIG. 5 , during the time interval when either of the inner switches S ₁ and S ₄ is closed and when v _AB =0, the primary voltage amplitude is |v _P |=V _IN /4, And during the time interval when |v _AB |=V _IN /2, the primary voltage amplitude is |v _P |=0.

For ease of analysis, Figure 6 shows several layout stages of the converter during a switching cycle, while Figure 7 shows the main waveforms.

As shown in Figure 7, since the switches _S1 and _S2 are closed and the switches _S3 and _S4 are open during the time interval T ₀ -T ₁ , the voltage v _AB =V ₁ =V _IN /2, making the primary voltage v _p =0. Furthermore, during this layout stage, these equivalent circuits are shown in Fig. 6(a), the output current I _O flows through the rectifier D _O2 and the corresponding secondary of the transformer such that the primary current i _P = -I _O /n _TR , where n _TR =n _p / _NS is the turns ratio of the transformer, _NP is the number of turns of the primary winding, and N _S is the number of turns of the secondary winding. Since the primary current is negative, current _i1 and current _i2 are also negative, as shown in Figure 7(m) and (n). At the same time, due to the positive voltage v _AB =V _IN /2, the magnetizing current i _MC increases linearly with the slope V _IN /(2L _MC ), increasing the current i ₁ and decreasing the current i ₂ . Throughout the stage, the voltage v at the input of the output filter is _zero , equal to the secondary voltage because the primary voltage v is _zero . This phase ends at t= _T1 when switch _S1 is opened.

After the switch S ₁ is turned off at t=T ₁ , the current flowing through the transistor of the switch S ₁ is directed to the output capacitor C ₁ of the switch, as shown in FIG. 6( b ). During this layout phase, since the sum of the voltages across capacitors _C1 and _C4 is equal to the constant voltage _VIN /2, current _i2 charges capacitor _C1 and discharges capacitor _C4 at the same rate. As a result, the voltage across switch _S1 increases and the voltage across switch _S4 decreases, as shown in Figure 7(e) and (h). In addition, at this stage, the potential of point A decreases, so that the voltage v _AB decreases from V _IN /2 to zero, and at the same time the primary voltage v _P rises from zero to V _IN /4, as shown in Figure 7(i) and Figure (j ) shown. The positive primary voltage initiates the commutation of the output current i _O from rectifier D _O2 to rectifier D _O1 . This commutation is instantaneous since the leakage inductance TR is ignored. However, in the presence of leakage inductance, the commutation of current from one rectifier to the other takes time. Since both rectifiers are on during this commutation time, ie the secondary of the transformer is short-circuited, the voltage v _S is zero, as shown in Fig. 7(o).

After capacitor _C4 is fully discharged at t= _T2 , i.e. after voltage _vS4 reaches zero, current _i2 continues to flow through anti-parallel diode _D4 and clamping diode _DC1 of switch _S4 instead of _C1 and C ₄ , as shown in Figure 6(c). Since the positive voltage V _IN /4 is applied across the primary winding, the currents i _P , i ₁ , and i ₂ increase from negative to positive. In order to achieve ZVS of switch S4, switch S4 needs to be turned on during the time interval when reverse diode _D4 is conducting, as shown in FIG. 7 . The phase in Fig. 6(c) ends at t= _T3 when the output current i _O is fully commutated from rectifier D _O2 to rectifier D _O1 , ie the primary current becomes i = i _O /n _TR .

During the time interval T ₃ -T ₄ , the current i ₁ flowing through the closed switch S ₂ is supplied from the voltage _source V _CB1 , and the current i 2 flowing through the closed switch S ₄ is supplied from the voltage source V ₂ , as shown in Fig. 6(d ) shown. The phase in Figure 6(d) ends at t= _T4 when switch _S2 is turned off. After switch _S2 is turned off, the current flowing through the transistor of switch _S2 is diverted to its output capacitor _C2 , as shown in Fig. 6(e). At this layout stage, current _i1 charges capacitor _C2 and discharges _C3 at the same rate since the sum of the voltages across capacitors _C2 and capacitor _C3 is equal to the constant voltage V _CB1 +V _CB2 =V _IN /2. As a result, the voltage across switch _S2 increases, while the voltage across switch _S3 decreases, as shown in Figure 7(f) and (g). At the same time, the potential of point A begins to decrease, so that the voltage V _AB drops from zero to -V _IN /2, and at the same time the primary voltage V _P drops from V _IN /4 to zero, as shown in Figure 7(i) and Figure (j) Show. Since the reduction in the primary voltage affects the secondary voltage, _VS also decreases to zero, as shown in Figure 7(O). This phase ends at t= _T5 when the capacitor _C3 is fully discharged and the current _i1 starts to flow through the switch _S3 anti-parallel diode _D3 , as shown in Fig. 6(f). Since the negative voltage V _IN /2 is applied to both ends of the magnetizing inductance L _MC after t=T ₅ , the magnetizing current i _MC begins to decrease linearly to zero with a constant slope V _IN /(2L _MC ), as shown in Figure 7(1 ) shown. After i _MC reaches zero at t=T ₆ , it continues to flow in the negative direction as shown in Fig. 6(g). The layout phase of Figure 6 ends at t= _T7 when switch _S4 is opened and the converter enters the second half of the switching cycle. The operation during the second half of the switching cycle, i.e. the operation during the interval T ₇ -T ₁₃ is identical to the operation during the interval T ₁ -T ₇ as described, except that the switches S ₁ and S ₂ are swapped with the switches S ₃ and S ₄ roles.

From the waveforms (m) and (n) of Figure 6, it can be seen that for all four primary switches S ₁ to S ₄ , the current amplitudes flowing through the switches at the moment of turn-off are the same, that is, $i_2(t=T_1)=i_1(t=T_4)=i_2(t=T_7)=i_1(t=T_{10})=\left|\frac{i_{\mathrm{<figure-callout\; id="2"\; label="p"\; filenames="A0210841100211.png,A0210841100221.png"\; state="\{\{state\}\}">p</figure-callout>}}}{2}\right|+\left|I_{\mathrm{MC}}\right|=\left|\frac{I_{\mathrm{<figure-callout\; id="2"\; label="o"\; filenames="A0210841100211.png,A0210841100221.png"\; state="\{\{state\}\}">o</figure-callout>}}}{2{\mathrm{no}}_{\mathrm{TR}}}\right|+\left|I_{\mathrm{MC}}\right|$

(11) Among them, i _O is the load current, n _TR is the turns ratio of the transformer, and I _MC is the amplitude of the magnetizing current i _MC .

According to equation (11), the commutation of the switches is controlled by the primary The stored energy of both the current ip and the magnetizing current i _MC completes. Although the commutation energy provided by the magnetizing _current i is always stored in the magnetizing inductance L _MC of the coupled inductor _LC , the commutation energy provided by the current _i is either stored in the filter inductance of the secondary output circuit (not shown in FIG. 5 ), or stored in the leakage inductance (not shown in FIG. 5 ) of the transformer TR and the coupled inductor L _C. Specifically, for the inner switches S ₂ and S ₃ , the commutation energy provided by i _p is stored in the output filter inductor _LF , while for the outer switches S ₁ and S ₄ the commutation energy provided by i _p Stored in the leakage inductance of the transformer. Since the leakage inductance of the transformer TR needs to be minimized to minimize secondary parasitic ringing, the energy stored in the leakage inductance is relatively small, ie much smaller than the energy stored in the output filter inductance. As a result, in the circuit of Figure 4, the ZVS of the inner switches _S2 and _S3 is easily achieved over the entire load range, while the ZVS of the outer switches _S1 and _S4 requires an appropriate size of the magnetizing inductance _LMC because in At light loads, almost all the energy required to establish the ZVS condition for the outer switches _S1 and _S4 is stored in the magnetizing inductance.

In a full bridge circuit with a coupled inductor and an isolation transformer, the inductor and transformer can switch roles, as described in patent application Serial No. ______, filed February 5, 2001, specifically by placing the secondary The primary winding is added to a coupled inductor that can be used as a transformer to deliver power to the output circuit connected to its secondary, and the magnetizing inductance of the transformer can be used as an inductor to store energy for ZVS. Figures 8 and 9 show two such embodiments. In general, the operation of the circuits shown in FIGS. 8 and 9 is the same as that of the circuit shown in FIG. 4 . The main difference is that in the circuit of Figure 4, the maximum output voltage (volt-second product) is obtained with a phase shift of 180° between the outer pair of switches and the inner pair of switches, whereas the circuits of Figures 8 and 9 The maximum output voltage (volt-second product) of , occurs when the phase shift is zero. This difference in the control characteristics of the different embodiments has only minor impact on the control loop design, since a simple inversion of the control signal in the voltage control loop is all that is required to obtain the desired control loop characteristics.

As already stated, in the circuit of the present invention, achieving ZVS for the outer switch pair is more difficult than achieving ZVS for the inner switch because the energy available to establish the ZVS condition in the two switch pairs is different. In general, to achieve ZVS, this energy must be at least equal to the energy required to discharge the capacitance of the switch that is about to turn on and simultaneously charge the capacitance of the switch that is just turning off. At heavier load currents, ZVS is mainly achieved by the energy stored in the leakage inductance of the transformer TR. As the load current decreases, the energy stored in the leakage inductance also decreases, while the energy stored in the inductor _LC increases, so that at light loads, _LC provides an increasing share of the energy required for ZVS. In fact, when there is no load, this _LC provides all the energy needed to establish the ZVS condition. Therefore, if the value of L _C is chosen such that ZVS is achieved at no load and at the maximum input voltage V _IN(max) , ZVS can be achieved over the entire load and input voltage range.

Neglecting the inductance of the transformer winding, the magnetizing inductance _LMC required to achieve ZVS of the outer switch in the implementation of Figure 4 is: $L_{\mathrm{MC}}\&le;\frac{1}{32{\mathrm{Cf}}_{\mathrm{the\; s}}^2}------\left(12\right)$

While the inductance L _C required to achieve ZVS of the inner switch in the implementations of Figures 8 and 9 is: $L_{\mathrm{MC}}\&le;\frac{1}{128{\mathrm{Cf}}_{\mathrm{the\; s}}^2}-----\left(13\right)$ where C is the total capacitance (parasitic and external capacitance, if any) on the primary switch of the corresponding switch pair.

As can be seen from FIG. 5 , the current i _MC flowing through the magnetizing inductance L _MC causes a current asymmetry between the inner and outer switch pairs implemented in FIG. 4 . That is, since i ₁ =i ₂ +2i _MC in this circuit (as can be derived _from equations (6) and (7)), the inner switches S ₂ and S ₃ always transmit and S ₄ for greater current. This can be seen from the asymmetry of the current flow between the inner and outer switch pairs which is also exhibited in the embodiments of FIGS. 8 and 9 . Furthermore, if the current imbalance in the circuits of Figures 4, 8, and 9 is so significant that the current _i2 flowing through the outer switches _S1 and _S4 is significantly different from the current _i1 flowing through the inner switches _S2 and _S3 , Switches of different sizes can be selected for the two switch pairs, which reduces implementation cost without sacrificing circuit performance.

It should be noted that in the circuits of the present invention, the parasitic ringing on the secondary side is significantly reduced because these circuits do not require the addition of transformer leakage inductance or large external inductances to store the required energy for ZVS. Since the transformer in the circuit of the present invention can be made with very small leakage inductance, the secondary ringing between the leakage inductance of the transformer and the junction capacitance of the ballast can be greatly reduced. Any remaining parasitic ringing can be attenuated by a small (low power) muffler.

Finally, since the voltage sources V _CB1 =V _IN /4 and V _CB2 =V _IN /4 in Figure 5 can be realized by capacitors C _B1 and C _B2 respectively, as shown in Figures 4, 8, and 9, at the start-up instant Before, these capacitors must be precharged to V _IN /4. That is, without precharging, the voltage across the capacitors is zero, which creates a volt-second imbalance in the transformer windings during start-up. This volt-second imbalance can cause the transformer to saturate, creating overcurrent in the primary that can damage the switch. Figure 10 shows an example of a precharge circuit. The pre-charging circuit in Figure 10 is implemented with resistors R _C1 -R _C4 . It should be noted that many other implementations of pre-charge circuits can be used with any of the circuits of the present invention.

It should also be pointed out that the above detailed description is for describing specific embodiments of the present invention, and is not intended to limit various changes and modifications within the possible scope of the present invention. In addition, the present invention is not limited to DC/DC converters, but can also be applied to multi-pole DC/AC inverters.

references

1. T A Meynard and H. Foch, "Multi-Level Conversion: High Voltage Chopper and Voltage-Source Inverters," IEEE Power Electronics Specialists' Conf. Rec. Pp 397-403, 1992.

2. J.R.Pinheiro and I.Barbi, "The Three-Level ZVS PWM Converter: ANew Concept in High-Voltage DC-to-DC Conversion," IEEE Int.'l Conf. On Industrial Electronics, Control, Instrumentation, and Automation (IECON ) Pro., pp.173-178, 1992.

3. J.S.Lai and F.Z.Peng, "Multilevel Converters-A New Breed of Power Conversion," IEEE Trans.Ind.App., vol.32, no.3, May/June 1996, pp.509-517.

Claims (12)

1. soft handover, frequency stabilization, three stage power source converter with phase shift modulation comprises:

The input power supply;

Be applicable to four controlled switching devices of series connection that connect described input power supply, each described controlled switching device comprises a switch, an anti-parallel connection diode and a capacitor that is coupling in described switch ends that is coupling in described switch ends;

Transformer with primary and secondary winding;

Be arranged on the inductor on the described primary, periodically disconnect and make when closed the weber product maximum of described inductor winding with the outer switch of the gate-controlled switch device of described four series connection of box lunch and corresponding inner switch homophase, with the weber product minimum that makes described Transformer Winding, and when the outer switch of the gate-controlled switch device of described four series connection and corresponding inner switch are anti-phase when periodically disconnecting and be closed, make the weber product minimum and make the weber product maximum of the described winding of described transformer of the described winding of described inductor;

A plurality of capacitors that are arranged on described transformer described elementary, being used to provide voltage is the power supply of the part of described input supply voltage, and be coupled to described four controllable switch, so that the voltage at the described gate-controlled switch two ends of conducting is not the part of the described voltage of described input power supply;

Output circuit is used for load is coupled to the described secondary winding of described transformer.

2. soft handover, frequency stabilization, three stage power source converter with phase shift modulation comprises:

The input power supply;

Be applicable to four controlled switching devices of series connection that connect described input power supply, each described controlled switching device comprises a switch, an anti-parallel connection diode and a capacitor that is coupling in described switch ends that is coupling in described switch ends;

Transformer with primary and secondary winding;

Be arranged on the inductor on the described primary, periodically disconnect and make when closed the weber product maximum of described Transformer Winding with the outer switch of the gate-controlled switch device of described four series connection of box lunch and corresponding inner switch homophase, with the weber product minimum that makes described inductor winding, and when the outer switch of the gate-controlled switch device of described four series connection and corresponding inner switch are anti-phase when periodically disconnecting and be closed, make the weber product minimum and make the weber product maximum of the described winding of described inductor of the described winding of described transformer;

A plurality of capacitors that are arranged on described transformer described elementary, being used to provide voltage is the power supply of the part of described input supply voltage, and be coupled to described four controllable switch, so that the voltage at the described gate-controlled switch two ends of conducting is not the part of the described voltage of described input power supply;

Output circuit is used for load is coupled to the described secondary winding of described transformer.

3. supply convertor according to claim 1, it is characterized in that selecting the inductance of described inductor, must be enough to make the described output capacitance of each the described gate-controlled switch device that will connect to be discharged fully so that the energy of storing in the described inductor is big, so that the voltage at instantaneous described each described gate-controlled switch device two ends of switch connection fully reduces in the whole current range of described load.

4. supply convertor according to claim 1, it is characterized in that described inductor is set to have the coupling and the inductor of two windings of series connection, wherein select the magnetizing inductance of described coupling and inductor, must be enough to make the described output capacitance of each the described gate-controlled switch device that will connect fully to be discharged so that the energy of storing in the described magnetizing inductance is big, so that the voltage at instantaneous described each described gate-controlled switch device two ends of switch connection fully reduces in the whole current range of described load.

5. supply convertor according to claim 1, it is characterized in that also comprising a described winding that described transformer and inductor be provided weber balance capacitor.

6. supply convertor according to claim 1 is characterized in that also comprising a catching diode, is used for the voltage limit at described gate-controlled switch device two ends is arrived the part of the described voltage of described input power supply.

7. supply convertor according to claim 1, it is characterized in that also comprising a plurality of resistors, be used for after described power supply is applied to described supply convertor immediately to described a plurality of capacitor precharge, so that described a plurality of capacitor provides the required voltage of weber product of the described winding of keeping described transformer and inductor.

8. supply convertor according to claim 1 is characterized in that the described elementary winding of described transformer has centre cap.

9. power transformer according to claim 1 is characterized in that the described secondary winding of described transformer has centre cap.

10. power transformer according to claim 1 is characterized in that described output circuit is a full-wave rectifier.

11. power transformer according to claim 1 is characterized in that described output circuit is a current-doubler.

12. require 1 described supply convertor according to full stream, it is characterized in that described output circuit comprises a filter.

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