CN1387396A - Impedance measuring structure - Google Patents
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Abstract
Description
技术领域technical field
本发明是有关于一种阻抗测量结构,且特别是有关于一种可制作于电路基板表面的阻抗测量结构。The present invention relates to an impedance measurement structure, and in particular to an impedance measurement structure that can be fabricated on the surface of a circuit substrate.
背景技术Background technique
由于集成电路(Integrated Circuit,IC)芯片(Die)的讯号依序经由芯片封装用的基板(Substrate)与印刷电路板(Printed Circuit Board,PCB)的内部线路,进而传递至远程外界的电子装置,因此,这些负责传递讯号的基板与印刷电路板,其内部线路对于讯号的完整性(Signal Integrity)有着决定性的影响。随着系统工作频率的日益增加,当基板或印刷电路板内部线路的线宽、线高、线距或介电层厚度误差过大,而发生阻抗不匹配(Impedance Mismatch)的问题时,将导致严重的电压反射(Reflection)现象,因而造成讯号高准位或低准位的判读产生错误,严重的话甚至使得整个系统装置无法正常运作。因此,芯片封装用的基板与印刷电路板于其制作过程当中,如何能准确地控制基板与印刷电路板的内部线路的线宽、线高(线厚)、线距及介电层厚度,而准确控制其内部线路的电性阻抗值是相当重要的。Since the signal of the integrated circuit (Integrated Circuit, IC) chip (Die) passes through the internal circuit of the chip packaging substrate (Substrate) and the printed circuit board (Printed Circuit Board, PCB) in sequence, and then is transmitted to the remote external electronic device, Therefore, these substrates and printed circuit boards responsible for transmitting signals have a decisive impact on the signal integrity (Signal Integrity). With the increasing operating frequency of the system, when the error of the line width, line height, line spacing or dielectric layer thickness of the internal circuit of the substrate or printed circuit board is too large, and the problem of impedance mismatch (Impedance Mismatch) occurs, it will lead to Severe voltage reflection (Reflection) phenomenon, thus causing errors in the interpretation of high-level or low-level signals, and in severe cases, it may even make the entire system device unable to operate normally. Therefore, in the manufacturing process of substrates and printed circuit boards used for chip packaging, how to accurately control the line width, line height (line thickness), line spacing and dielectric layer thickness of the internal circuits of the substrate and printed circuit boards, and It is very important to accurately control the electrical impedance value of its internal circuit.
就公知而言,芯片封装用的基板或印刷电路板均针对实际的应用来加以设计,并须同时设计基板或印刷电路板的内部线路的线宽、线高、线距及介电层厚度,进而控制印刷电路板的内部线路的电阻抗值。值得注意的是,由于芯片封装用的基板或印刷电路板于工艺上的些微偏差,均有可能导致内部线路的线宽、线高、线距或介电层厚度相对地产生误差,使得内部线路的电阻抗值超出或低于原先设计的电阻抗值的公差范围(tolerance)。As far as it is known, the substrate or printed circuit board used for chip packaging is designed for practical applications, and the line width, line height, line spacing and dielectric layer thickness of the internal circuit of the substrate or printed circuit board must be designed at the same time. Furthermore, the electrical impedance value of the internal circuit of the printed circuit board is controlled. It is worth noting that due to slight deviations in the process of the substrate or printed circuit board used for chip packaging, there may be relative errors in the line width, line height, line spacing or dielectric layer thickness of the internal lines, making the internal lines The electrical impedance value exceeds or falls below the tolerance range (tolerance) of the originally designed electrical impedance value.
承上所述,芯片封装用的基板或印刷电路板于制作完成后,均未检测其内部线路的电阻抗值,即进行下一阶段的组装作业,而仅在最终的实际产品上进行电阻抗值的检测。当基板或印刷电路板的内部线路的电阻抗值一旦不符合设计上的要求时,势必将降低最终实际产品的生产合格率。因此,芯片封装用的基板或印刷电路板于制作完成后,有必要预先检测其内部线路的电阻抗值,以排除电阻抗值不符标准的芯片封装用的基板或印刷电路板,使其无法进行下一阶段的组装作业,进而提升最终实际产品的生产合格率,并同时降低其制造成本。As mentioned above, after the substrate or printed circuit board for chip packaging is completed, the electrical impedance value of its internal circuit is not tested, that is, the next stage of assembly work is carried out, and the electrical impedance value is only tested on the final actual product. value detection. Once the electrical impedance value of the substrate or the internal circuit of the printed circuit board does not meet the design requirements, it will inevitably reduce the production pass rate of the final actual product. Therefore, after the substrate or printed circuit board for chip packaging is completed, it is necessary to detect the electrical impedance value of its internal circuit in advance, so as to exclude the substrate or printed circuit board for chip packaging whose electrical impedance value does not meet the standard, so that it cannot be processed. The assembly operation in the next stage can improve the production qualification rate of the final actual product and reduce its manufacturing cost at the same time.
发明内容Contents of the invention
本发明的目的在于提供一种阻抗测量结构,在制作电路基板(如芯片封装用的基板或印刷电路板)时,可利用电路基板表层的图案化线路层,一并将此阻抗测量结构制作于电路基板的表面,当电路基板于制作完成后,可检测此阻抗测量结构的测量迹线的电阻抗值,以判断电路基板的图案化线路层的线宽、线高、线距及介电层厚度,其是否符合原先设计上的要求。The object of the present invention is to provide a kind of impedance measurement structure, when making circuit substrate (such as substrate or printed circuit board for chip packaging), can utilize the patterned line layer of circuit substrate surface layer, and this impedance measurement structure can be made on The surface of the circuit substrate. After the circuit substrate is manufactured, the electrical impedance value of the measurement trace of the impedance measurement structure can be detected to determine the line width, line height, line spacing and dielectric layer of the patterned circuit layer of the circuit substrate. Thickness, whether it meets the requirements of the original design.
基于本发明的上述目的,本发明提出一种阻抗测量结构,适用于一电路基板,此阻抗测量结构具有一第一测量焊垫及一第二测量焊垫,二者均配置于电路基板的表面。并且,此阻抗测量结构还具有一测量迹线,其配置于电路基板的表面,且测量迹线的一端连接至上述第二测量焊垫。其中,电路基板的表面具有一图案化线路层,而阻抗测量结构由此图案化线路层所构成。此外,电路基板具有一接地电路,而第一测量焊垫电连接至接地电路。另外,电路基板具有一保留区域及一切除区域,而此阻抗测量结构配置于切除区域的表面。Based on the above purpose of the present invention, the present invention proposes an impedance measurement structure suitable for a circuit substrate. The impedance measurement structure has a first measurement pad and a second measurement pad, both of which are arranged on the surface of the circuit substrate. . Moreover, the impedance measurement structure further has a measurement trace disposed on the surface of the circuit substrate, and one end of the measurement trace is connected to the second measurement pad. Wherein, the surface of the circuit substrate has a patterned circuit layer, and the impedance measurement structure is formed by the patterned circuit layer. In addition, the circuit substrate has a ground circuit, and the first measurement pad is electrically connected to the ground circuit. In addition, the circuit substrate has a reserved area and a cut-off area, and the impedance measurement structure is arranged on the surface of the cut-out area.
附图说明Description of drawings
图1为本发明实施例的一种阻抗测量结构,其应用于一电路基板的示意图;Fig. 1 is a kind of impedance measurement structure of the embodiment of the present invention, and it is applied to the schematic diagram of a circuit substrate;
图2A、图2B分别为本发明实施例的一种阻抗测量结构,其应用于单一传输线的示意图;2A and 2B are schematic diagrams of an impedance measurement structure of an embodiment of the present invention, which is applied to a single transmission line;
图3A、图3B分别为本发明实施例的另一种阻抗测量结构,其应用于差动讯号传输线的示意图;以及3A and 3B are schematic diagrams of another impedance measurement structure of the embodiment of the present invention, which is applied to a differential signal transmission line; and
图3C、图3D分别为本发明实施例的又一种阻抗测量结构,其应用于差动讯号传输线的示意图。FIG. 3C and FIG. 3D are schematic diagrams of yet another impedance measurement structure according to the embodiment of the present invention, which is applied to a differential signal transmission line.
附图标记说明:Explanation of reference signs:
10:电路基板 12:切除区域10: Circuit board 12: Excision area
12a:板边 12b:切割道12a:
14:保留区域 16:接地电路14: Reserved area 16: Grounding circuit
100:阻抗测量结构 102:第一测量焊垫100: Impedance measurement structure 102: The first measurement pad
104:第二测量焊垫 106:测量迹线104: Second measurement pad 106: Measurement trace
200:阻抗测量结构 202:第一测量焊垫200: Impedance measurement structure 202: The first measurement pad
204:第二测量焊垫 206:第一测量迹线204: Second measurement pad 206: First measurement trace
212:第三测量焊垫 214:第四测量焊垫212: The third measurement pad 214: The fourth measurement pad
216:第二测量迹线 222:第五测量焊垫216: Second measurement trace 222: Fifth measurement pad
具体实施方式Detailed ways
请参考图1,其为本发明实施例的一种阻抗测量结构,其应用于一电路基板的示意图。电路基板10于制作完成后,通常都会将电路基板10多余的板边12a加以裁切去除,而仅保留电路基板10的中央部分。此外,为了要降低小尺寸电路基板的制作成本,通常将多个小尺寸的电路基板的线路同时设计于同一片大尺寸的电路基板10的各个保留区域14,再将这些保留区域14从电路基板10分别裁切下来。为了便于切割作业的进行,在相邻两线路区域14之间通常设计有切割道12b,而电路基板10的板边12a及切割道12b则共同构成电路基板10的切除区域12。Please refer to FIG. 1 , which is a schematic diagram of an impedance measurement structure applied to a circuit substrate according to an embodiment of the present invention. After the
请同样参考图1,电路基板10通常由多层图案化线路层及多层绝缘层相互交错叠合而成,为了确定电路基板10的图案化线路层的导电迹线,其线宽、线高(线厚)、线距及介电层厚度是否都在公差(tolerance)范围内,因此,在制作电路基板10的同时,本发明利用电路基板10表层的图案化线路层来构成一阻抗测量结构100。此外,为了增加阻抗检测作业上的便利性,通常是将阻抗测量结构100设计于电路基板10的表面。另外,由于阻抗测量结构100在测量其电阻抗值后,即失去它的作用,故可将阻抗测量结构100设计位于电路基板10的切除区域12,包括设计在板边12a或切割道12b,且分别邻近于各个保留区域14,即位于未裁切的线路结构的旁边。Please also refer to FIG. 1. The
请同时参考图1、图2A、图2B,其中图2A、图2B分别为本发明实施例的一种阻抗测量结构,其应用于单一传输线(Single End)的示意图。首先,如图2A所示,阻抗测量结构100主要由一第一测量焊垫102、一第二测量焊垫104及一测量迹线106组成,其中第一测量焊垫102配设于电路基板10的表面,并经由绕线而电连接至电路基板10的接地电路16,例如一片状接地结构(ground plane),而第二测量焊垫104亦配设于电路基板10的表面,并相邻于第一测量焊垫102,而测量迹线106则配设于电路基板10的表面,且测量迹线106的一端连接至第二测量焊垫104。因此,在图1的电路基板10于制作完成后,可将阻抗测量仪器的探针分别接触第一测量焊垫102及第二测量焊垫104,即可测量到这一段测量迹线106的电阻抗值。此外,如图2B所示,除了阻抗测量结构100的第一测量焊垫102可经由绕线而电连接至接地电路16外,测量迹线106的另一端亦可经由绕线而电连接至接地电路16,在这样的连接方式下,同样可利用阻抗测量仪器经由第一测量焊垫102及第二测量焊垫104来测量出此段测量迹线106的电阻抗值。Please refer to FIG. 1, FIG. 2A, and FIG. 2B at the same time, wherein FIG. 2A and FIG. 2B are schematic diagrams of an impedance measurement structure of an embodiment of the present invention, which is applied to a single transmission line (Single End). First, as shown in FIG. 2A, the
请再参考图1、图2A,由于测量迹线106的电阻抗值的大小对应测量迹线106的线长、线宽及线高,故可让此测量迹线106预先设计具有特定的线长、线宽及线高,并对应此段测量迹线106的线长、线宽及线高,而设定其电阻抗值的公差范围,因此,在大量制作图1的电路基板10的情况下,可抽样检测电路基板10的阻抗测量结构100,一旦发现阻抗测量结构100的测量迹线106的电阻抗值超出原先设定的电阻抗值范围时,则表示电路基板10的工艺发生问题,例如对位准确度下降或蚀刻率改变等工艺上的问题。Please refer to FIG. 1 and FIG. 2A again. Since the magnitude of the electrical impedance value of the
由于芯片内部的组件及线路的集成度(Integration)均日益增加,为了预防讯号于传输的过程中受到电磁场的干扰,因而发生讯号判读错误的现象,故公知技术产生出差动讯号(Differential Pair)的双传输线的设计。请参考图3A、图3B,其分别为本发明实施例的另一种阻抗测量结构,其应用于差动讯号传输线的示意图。首先,如图3A所示,阻抗测量结构200针对检测差动讯号的成对导电迹线的电阻抗值而设计,阻抗测量结构200主要由第一测量焊垫202、第二测量焊垫204及第一测量迹线206,以及第三测量焊垫212、第四测量焊垫214及第二测量迹线216所组成,其均可由图1的电路基板10的表层的图案化线路层所构成。Due to the increasing integration of the components and circuits inside the chip, in order to prevent the signal from being interfered by the electromagnetic field during the transmission process, the signal interpretation error occurs, so the known technology produces a differential signal (Differential Pair) Dual transmission line design. Please refer to FIG. 3A and FIG. 3B , which are schematic diagrams of another impedance measurement structure applied to a differential signal transmission line according to an embodiment of the present invention. First, as shown in FIG. 3A, the
请同样参考图3A,第一测量焊垫202、第二测量焊垫204及第一测量迹线206均配设于图1的电路基板10的表面,而第一测量焊垫202可经由绕线而电连接至接地电路16,且第二测量焊垫204的位置邻近于第一测量焊垫202的位置,而第一测量迹线206的一端则连接至第二测量焊垫204。此外,第三测量焊垫212、第四测量焊垫214及第二测量迹线216均配置于图1的电路基板10的表面,且第三测量焊垫212、第四测量焊垫214及第二测量迹线216的位置均分别对应第一测量焊垫202、第二测量焊垫204及第一测量迹线206的位置,并且第三测量焊垫212可经由绕线而电连接至接地电路16。Please also refer to FIG. 3A, the
请同样参考图3A,第一测量迹线206及第二测量迹线216的长度可设计相同,故可利用阻抗测量仪器经由第一测量焊垫202及第二测量焊垫204来测量第一测量迹线206的电阻抗值,并同时经由第三测量焊垫212及第四测量焊垫214来测量第二测量迹线216的电阻抗值。此外,请参考图3B,第一测量迹线206的另一端及第二测量迹线216的另一端也可分别经由绕线而电连接至电路基板的接地电路,在这样的连接方式下,也可利用阻抗测量仪器经由第一测量焊垫202及第二测量焊垫204来测量第一测量迹线206的电阻抗值,并同时经由第三测量焊垫212及第四测量焊垫214来测量第二测量迹线216的电阻抗值。同样地,经由上述的阻抗测量结构所测量出的第一测量迹线及第二测量迹线的电阻抗值均不能超出原先设定电阻抗值的公差范围,且两者不能差异过大,否则即表示电路基板10的工艺发生问题。Please also refer to FIG. 3A , the lengths of the
由于图3A、图3B的第一测量焊垫202及第二测量焊垫212均电连接至接地电路16,故可将第一测量焊垫202及第三测量焊垫212整合为图3C、图3D的第五测量焊垫222,其位置可对应位于第二测量焊垫204及第四测量焊垫214的中间位置,而其它第二测量焊垫204、第四测量焊垫214、第一测量迹线206及第二测量迹线216之间的相关位置均不改变,如此将可经由第五测量焊垫222及第二测量焊垫204来测量第一测量迹线206的电阻抗值,并可经由第五测量焊垫222及第四测量焊垫214来测量第二测量迹线216的电阻抗值。值得注意的是,第五测量焊垫222的较佳位置可配置在与第二测量焊垫204及第四测量焊垫214等距处,如此将可获得最佳的测量效果。Since the
本发明实施例的阻抗测量结构制作于一电路基板的表面,例如芯片封装用的基板或一般印刷电路板的表面,并由电路基板表层的图案化线路层所构成。其中,阻抗测量结构由一第一测量焊垫、一第二测量焊垫及一测量迹线所构成,其中第一测量焊垫及第二测量焊垫配置于电路基板的表面,第一测量焊垫经由绕线而电连接至电路基板的接地电路,而测量迹线的一端则连接至第二测量焊垫,因此,可利用阻抗测量仪器分别经由两测量焊垫来测量此段测量迹线的电阻抗值。此外,本发明除了设计一种可对应检测单一传输线的图2A、图2B的阻抗测量结构100外,还设计另一种可对应检测差动讯号传输线的图3A、图3B及图3C、图3D的阻抗测量结构200。The impedance measurement structure of the embodiment of the present invention is fabricated on the surface of a circuit substrate, such as a substrate for chip packaging or a surface of a general printed circuit board, and is composed of a patterned circuit layer on the surface of the circuit substrate. Wherein, the impedance measurement structure is composed of a first measurement pad, a second measurement pad and a measurement trace, wherein the first measurement pad and the second measurement pad are arranged on the surface of the circuit substrate, and the first measurement pad The pad is electrically connected to the ground circuit of the circuit substrate through winding wires, and one end of the measurement trace is connected to the second measurement pad. Therefore, the impedance measuring instrument can be used to measure this section of the measurement trace through the two measurement pads respectively. Electrical impedance value. In addition, in addition to designing an
综上所述,本发明的阻抗测量结构适用于电路基板(如芯片封装用基板或印刷电路板)的电阻抗值的检测,可在电路基板于制作完成后,或是制作过程中,由检测阻抗测量结构的测量迹线的电阻抗值是否在原先设定的电性阻抗值的公差范围内,用以表示电路基板的内部线路的线宽、线高、线距及介电层厚度,其是否符合原先设计上的要求,进而避免不合格的电路基板继续进行下一阶段的组装工艺,如此将可有效降低最终实际产品的工艺成本,并提高其工艺合格率。In summary, the impedance measuring structure of the present invention is suitable for detecting the electrical impedance value of a circuit substrate (such as a substrate for chip packaging or a printed circuit board). Whether the electrical impedance value of the measurement trace of the impedance measurement structure is within the tolerance range of the originally set electrical impedance value is used to indicate the line width, line height, line distance and dielectric layer thickness of the internal circuit of the circuit substrate. Whether it meets the requirements of the original design, so as to avoid unqualified circuit substrates from continuing to the next stage of assembly process, which will effectively reduce the process cost of the final actual product and improve its process qualification rate.
虽然本发明已以一实施例说明如上,然其并非用以限定本发明,任何熟悉此技术者,在不脱离本发明的精神和范围内,当可作些许的更动与润饰,因此本发明的保护范围当以权利要求书为准。Although the present invention has been described above with an embodiment, it is not intended to limit the present invention. Any person familiar with the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be determined by the claims.
Claims (13)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02121925 CN1278592C (en) | 2002-05-24 | 2002-05-24 | Impedance measurement structure |
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| Application Number | Priority Date | Filing Date | Title |
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| CN 02121925 CN1278592C (en) | 2002-05-24 | 2002-05-24 | Impedance measurement structure |
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| CN1387396A true CN1387396A (en) | 2002-12-25 |
| CN1278592C CN1278592C (en) | 2006-10-04 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101788612B (en) * | 2009-01-23 | 2012-09-05 | 南亚电路板股份有限公司 | Resistance measurement module of printed circuit board and its measurement method |
| CN102967762A (en) * | 2012-11-14 | 2013-03-13 | 大连太平洋电子有限公司 | Method for testing micro-resistance library sheet resistance value of printed wiring board |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101359009B (en) * | 2007-08-03 | 2010-10-27 | 中芯国际集成电路制造(上海)有限公司 | Measuring device for chip resistance |
-
2002
- 2002-05-24 CN CN 02121925 patent/CN1278592C/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101788612B (en) * | 2009-01-23 | 2012-09-05 | 南亚电路板股份有限公司 | Resistance measurement module of printed circuit board and its measurement method |
| CN102967762A (en) * | 2012-11-14 | 2013-03-13 | 大连太平洋电子有限公司 | Method for testing micro-resistance library sheet resistance value of printed wiring board |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1278592C (en) | 2006-10-04 |
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