CN1380605A - Rack construction using error distributed segmented table to repair memory body and its method - Google Patents
Rack construction using error distributed segmented table to repair memory body and its method Download PDFInfo
- Publication number
- CN1380605A CN1380605A CN 01110463 CN01110463A CN1380605A CN 1380605 A CN1380605 A CN 1380605A CN 01110463 CN01110463 CN 01110463 CN 01110463 A CN01110463 A CN 01110463A CN 1380605 A CN1380605 A CN 1380605A
- Authority
- CN
- China
- Prior art keywords
- memory
- address
- memory page
- leaf
- segmented table
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 34
- 230000008439 repair process Effects 0.000 title claims description 36
- 238000010276 construction Methods 0.000 title 1
- 238000012360 testing method Methods 0.000 claims abstract description 16
- 238000009826 distribution Methods 0.000 claims description 34
- 238000013507 mapping Methods 0.000 claims description 24
- 238000005520 cutting process Methods 0.000 claims description 23
- 238000003860 storage Methods 0.000 claims description 7
- 230000008676 import Effects 0.000 claims description 5
- 238000012216 screening Methods 0.000 claims description 4
- 238000003491 array Methods 0.000 claims description 3
- 239000012141 concentrate Substances 0.000 claims description 2
- 238000007689 inspection Methods 0.000 claims description 2
- 230000011218 segmentation Effects 0.000 claims 1
- 230000002950 deficient Effects 0.000 description 19
- 238000010586 diagram Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 238000012956 testing procedure Methods 0.000 description 3
- 238000013459 approach Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000006073 displacement reaction Methods 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000008034 disappearance Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000002650 habitual effect Effects 0.000 description 1
- 230000035800 maturation Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000009966 trimming Methods 0.000 description 1
Images
Landscapes
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
The invention relates to a configuration and method for patching dynamic random access memory (DRAM) by using generated memory pages of segmental list about error allocation. Memory pages with proper size on DRAMare as a segmented basic block. The memory pages of segmental list about error allocation are built at each time of booting system and testing memory body. The amounts of allowing error that occurs within a basic region are setup. When the errors exceed the limited region, the segmented blocks with lower error rate replace the segmented blocks with excess of errors so as to make the DRAM operate normally.
Description
The present invention is a kind of framework and method of repairing Dynamic Random Access Memory, particularly produce the segmented table that the memory page fault distributes, and according to this segmented table repairing address of encoding out, and point to a new heavily mapping address again, make access action occur in heavily mapping address, normal to keep the running of dynamic access memory body.
Past 25 years, the demand of memory body (as: SDRAM, SSDRAM etc.) storage volume has increased by 106 times, this is because the scaling and the introduction of the introduction of an electric crystal one capacitor stores lattice, channel capacitor device and one-tenth stack capacitor, and the every The Application of Technology of the scaling of electric crystal, significantly dwindle the size of SDRAM memory location, allowed each wafer to have higher memory location density.But unfortunately, be accompanied by the increase of density, the aforementioned processing procedure expense (processing costs) that minimizes feature also and then rises rapidly.
The SDRAM producer with profit knows that all production capacity is to keep the principal element of profit, therefore make the many funds of most wafer foundries (fab) investment reduce on the non-non-defective unit, or combining All Jobs person, technician and slip-stick artist constantly make great efforts to improve yield.After analyzing last 25 years wafer foundry's turnout, VLSI research report in 1996 points out that in 1991, a ripe wafer foundry need invest 600,000,000 to 700,000,000 dollars at least and just can reach about 85% yield (need not trimming).
Yet, put down in writing according to " the International Technology Roadmapfor Semiconductors in Defect Reduction " that published in 1991 by SIA: for the wafer foundry of maturation, in any case reduce the disappearance that processing procedure/equipment produced, also can only reach 85%～95% yield at most, as shown in Figure 1.
And be the consumed cost that reduces by 5%～15% defective product, the SDRAM producer carries out Hotfix usually again, is non-defective unit raising yield in the hope of 5%～15% defective product can be repaired.At present, two kinds of repairing methods that the SDRAM producer habitually practises are as follows:
(1) logical approach:
As shown in Figure 2, its main feature is to include testing procedure and repair step; This testing procedure is that whether defectiveness memory location (defected cells) 110 exists in the test memory body 100, if find defectiveness, then writes down the address of these defective memory locations 110; This repairing step is that the mat comparer 120 defective address that testing procedure is stored 130 does one relatively with the address of the desire access data of CPU transmission, if this address is in record, then this address is remapped (remapping) to repair memory body 140 (normally adopting SRAM), substitute the memory location of test memory body generation defective with a memory location wherein, and repair the state that can normally use.The shortcoming of this repairing method is as follows:
1.CPU the address signal of sending, except that the memory body 100 that will offer test, also needing provides to repair memory body 140, so address signal must need enough fan-outs (fanout) ability, otherwise signal can be declared by Wrong.
2. the speed of Xiu Buing is slow.Because of comparer 120 necessary then comparisons, will make system spend the more time at repairing memory page or leaf.
3. must need a comparer 120 in large scale and high performance and carry out address relatively, the very high Expensive of its price.
(2) backup fault tolerant approach:
As shown in Figure 3, its main feature is to repair in wafer sort, be in wafer manufacturing, to make a backup array element (spare array elements) 220 in memory body 200, CPU sees off address 230 signals (row address) earlier to memory body 200 memory locations during test, after waiting for suitable time delay (TRCD), send row address (column address) again, be able to each memory location is carried out access test, in case find defective memory location 210, promptly the mode of repairing with laser will back up array element 220 replacement defective memory locations 210, and repair the state that can normally use.The shortcoming of this repairing method is as follows: 1. can only repair in wafer sort, in case after wafer cuts, encapsulates, promptly can't utilize this method to repair again.2. each particle (die) needs the 1.5 second time of cost to repair the overlong time of repairing.3. increase the extra cost that laser is repaired.
Above-mentioned two kinds of existing habitual method for repairing and mending especially back up the very big burden that fault-tolerant patching more causes the SDRAM producer's cost, all nonideal mode in the enforcement of reality.
Fundamental purpose of the present invention provides a unique memory body bug patch framework and method thereof, so that the SDRAM producer need not abandon the product of those inevitable defectives, more can significantly reduce test and the extra cost cost of repairing, increase the SDRAM producer's interests.
For reaching above-mentioned purpose, the present invention proposes a kind of method that produces the segmented table of memory page fault distribution, is to produce when start or memory body test each time, includes the following step: the dynamic random memory body is divided into a plurality of memory pages or leaves with suitable size; Statistical data according to the memory body Fault Distribution is a benchmark with 4K, and every 4K * 2n scope is done to cut apart for several times as cutting apart unit as the memory number of pages of cutting unit (n is the integer more than or equal to 1); And corresponding every 8K, 16K, 32K, the possible errors amount of memory bodys such as 128K, corresponding memory body number and the number of comparators setting tolerable false memory number of pages, arrange storage false memory page or leaf address.
In addition, the present invention proposes a kind of to produce the method for the segmented table to repair Dynamic Random Access Memory of remembering the page fault distribution, includes the following step:
A. system boot;
B. carry out test-based examination to find wrong address and distribution thereof in memory chip;
C. when in the wrong scope that is distributed in planning in advance, then set up the segmented table of a Fault Distribution;
D. produce when concentrating on a certain scope when wrong distribution, then set up the segmented table of a Fault Distribution and establish
Location, location limiter;
E. import address to the address limiter;
F. whether comparer inspection input address is in different address scopes;
G. if there is not the mistake of discovery, then will import the address mapping to SDRAM, and the mapping address is read data thus;
H. if find mistake, will produce a wrong enable signal so that system can not read data to former input address,
And produce a rub-out signal to scrambler;
I. this scrambler is set up one at this rub-out signal and is repaired address;
J. repair memory body points to a new heavily mapping address again according to this repairing address;
K. with this heavily the mapping address replace former input address;
L. data will be read out from the SDRAM of this heavy mapping address.
Cooperate said method the present invention to propose a kind of framework, it comprises at least:
A plurality of address limiters, be in the segmented table that distributes according to the memory page fault of aforementioned generation, when finding that amount of error is cut apart the block restriction above this, to remedy the mistake that this cuts apart the block excess to use the lower wrong limit of cutting apart block of other error rate to the memory body address restriction of this block;
A plurality of corresponding memory bodys are the memory page or leaf address that make a mistake in order to storage, and its employed amount is with to cut apart the amount of error that block allows corresponding;
A plurality of comparator arrays are the address after the screening of the input address of comparison access requirement and address limiter, judging whether being different memory body address zone, and conclude whether wrong existence, and produce rub-out signal to scrambler;
One scrambler is to receive to set up one after the rub-out signal and repair address and correspond to repair memory body;
One repair memory body is that the aforementioned memory page or leaf address that obtains to need to repair of should encoding is pointed to a new heavily mapping address again, and stores these data;
One multiplexer is that the wrong enable signal that produced by comparator array is controlled, so that former input address is selected by system or heavily the mapping address reads data.
Because the present invention is that memory page or leaf with the suitable size of Dynamic Random Access Memory is as cutting apart basic block, when start or memory body test each time, set up the segmented table that the memory page fault distributes, and set the quantity that this base region tolerable makes a mistake, when mistake surpasses this limited range, can use the lower wrong limit of cutting apart block of other error rate and remedy the mistake that this cuts apart the block excess, normal to keep the running of dynamic access memory body, significantly reduce test and the extra cost cost of repairing, therefore it provides a unique memory body bug patch framework and method thereof, so that the SDRAM producer need not abandon the product of those inevitable defectives, increase the SDRAM producer's interests.
Fig. 1 shows the yield statistics of memory body in the wafer current foundries;
Fig. 2 shows the synoptic diagram of the logical patch method of memory body;
Fig. 3 shows the synoptic diagram of the fault-tolerant patching of backup of memory body;
Fig. 4 shows the normal memory body Fault Distribution figure that is obtained according to the statistical information data;
Fig. 5 shows the segmented table of Fault Distribution in an embodiment of the present invention;
Fig. 6 shows the interior configuration diagram of memory chip in an embodiment of the present invention;
The error curve figure of Fig. 7 displayed map 4 is offset left from the centre;
Fig. 8 shows process flow diagram of the present invention.
For disclosing the present invention in detail, below cooperate graphic elaborating for an embodiment.Learn by experiment, this distribution of memory body Fault Distribution image height, as shown in Figure 4, according to statistical information, we can the every 8K of inference, 16K, 32K, the amount of error of memory bodys such as 128K is so that we are when setting up wrong segmented table (Slicing Table ofFault Distribution), can not over-evaluate or underestimate the quantity of defective memory page or leaf, all resources all may effectively be used.The present invention utilizes in the above-mentioned experiment value general to build in the memory chip, when system boot and SDRAM memory page or leaf is examined, to help to set up the segmented table of a memory body Fault Distribution, the segmented table of promptly setting up the memory body Fault Distribution is a kind of instant running.
Suppose a 2G SDRAM, its each memory page or leaf is 4K Bytes, total total 512K memory page or leaf, and the statistical data of known 2G SDRAM all defect memory page or leaf, and, can set up the contingency table of a Fault Distribution based on these data under normal operation for the quantity of the defective of every 8K, 16K, 32K, 128K memory page or leaf, it will directly insert corresponding memory body sum and corresponding comparer, except that the size of repair memory body, store the address that the memory page or leaf (memory location) to defective remaps.
In the ideal, more comparer can be carried out simultaneously so that the defective page or leaf is found fast and repaired; Yet extra relevant memory body (it can be SRAM) and comparer are the higher costs of requirement, so consider should helping, will can not use to surpass 16 relevant memory bodys and comparer.
Fig. 5 shows the detailed content of the segmented table of Fault Distribution in an embodiment of the present invention:
Statistical data according to the memory body Fault Distribution is a benchmark with 4K, every 4K * 2n scope is done to cut apart for several times as cutting apart unit as the memory number of pages of cutting unit (n is the integer more than or equal to 1), promptly be to be that cut coverage is done cutting for several times with every 8K, every 16K, every 32K, every 128K respectively in the present embodiment, these scopes can be according to the deviser be stipulated during at practical application certainly.In the scope of these cuttings, and the corresponding memory body number and the number of comparators of tolerable false memory number of pages, arrangement storage false memory page or leaf address are set as follows in each cut coverage:
1. in every 8K memory page or leaf, allow 2 false memory pages or leaves (memory location), and the memory body of arranging 2 correspondences is stored in comparer address that meets of seeking in 8K memory page or leaf of 8K the interior false memory page or leaf address of being found of memory page or leaf scope and 2 correspondences.
2. in every 16K memory page or leaf, allow 2 false memory pages or leaves (memory location), and the memory body of arranging 2 correspondences is stored in comparer address that meets of seeking in 16K memory page or leaf of 16K the interior false memory page or leaf address of being found of memory page or leaf scope and 2 correspondences.
3. in every 32K memory page or leaf, allow 2 false memory pages or leaves (memory location), and the memory body of arranging 2 correspondences is stored in comparer address that meets of seeking in 32K memory page or leaf of 32K the interior false memory page or leaf address of being found of memory page or leaf scope and 2 correspondences.
4. in every 128K memory page or leaf, allow 4 false memory pages or leaves (memory location), and the memory body of arranging 4 correspondences is stored in comparer address that meets of seeking in 128K memory page or leaf of 128K the interior false memory page or leaf address of being found of memory page or leaf scope and 4 correspondences.
Therefore with a 2G SDRAM, each memory page or leaf is 4K, with shared 512K memory number of pages amount.If with 8K memory page or leaf (promptly with 2 4K memory pages or leaves) is the cutting unit, can cut out 64 8K memory pages or leaves altogether, and every 8K memory page or leaf can allow 2 faulty pages to exist, and therefore can allow 128 faulty pages to exist altogether under this cut coverage.
If serve as the cutting unit with 16K memory page or leaf (promptly with 4 4K memory pages or leaves) again, can cut out 32 16K memory pages or leaves altogether, and every 16K memory page or leaf can allow additionally 2 faulty pages to exist again, and therefore can additionally allow 64 faulty pages to exist altogether again under this cut coverage.
If serve as the cutting unit with 32K memory page or leaf (promptly with 8 4K memory pages or leaves) again, can cut out 16 32K memory pages or leaves altogether, and every 32K memory page or leaf can allow additionally 2 faulty pages to exist again, and therefore can additionally allow 32 faulty pages to exist altogether again under this cut coverage.
If with 128K memory page or leaf (promptly with 32 4K memory pages or leaves) is the cutting unit, can cut out 4 128K memory pages or leaves altogether, and every 16K memory page or leaf can allow additionally 4 faulty pages to exist again, and therefore can additionally allow 16 faulty pages to exist altogether again under this cut coverage.
To sum up state, a 2G SDRAM can allow 240 false memory pages or leaves altogether and have (128+64+32+16=240).
Below be the example explanation with the actual job in the memory chip (entering to address output) from address, as shown in Figure 6, the framework in the memory chip includes: several address limiters (Address Limiter) 310, several corresponding memory bodys (associate memory) 320, several comparator arrays (compartor array) 330, scrambler (encoder) 340, repair memory body (repair memory) 350 and multiplexer (multiplexer) 360; Division is as follows:
Address limiter 310: be according in the segmented table to Fault Distribution, when finding that amount of error is cut apart the block restriction above this, to remedy the mistake that this cuts apart the block excess to use the lower wrong limit of cutting apart block of other error rate to the memory body address restriction of this block.Shown in Figure 4 is the normal memory body Fault Distribution zone that is obtained according to the statistical information data, yet when SDRAM its lower address scope have higher, during than the grave error ratio, its error curve figure will be offset left from the centre and as shown in Figure 7, the error number that will allow above the cutting distributed areas in factual error page or leaf (memory location) quantity of lower address scope.
In example shown in Figure 7, nearly there is the faulty page quantity of 10 maximum drop in the scope of 32K memory page or leaf.But the mistake of allowing according to the cutting distributed areas is that every 8K has 2 mistakes, and every 16K has 4 mistakes, and every 32K has 6 mistakes, and every 128K has 10 mistakes.In order to cover these extra faulty pages, we will " by " in the limit of 128K.Although can arrange the error tolerance distributed areas, always allow that wrong quantity is constant.In other words,, avale, promptly must sacrifice other regional tolerable mistake limits and remedy this special area, so-called memory body address restriction that Here it is in the constant feelings of wrong sum if certain zone surpasses the wrong limit in this zone.When system boot, after memory body should be crossed test-based examination, system will find to take place the memory body address block of maximum number of errors, in order to use the wrong limit that covers in each block flexibly, the wrong limit of sacrificing several zones be remedied the zone that exceeds the quata.
Corresponding memory body 320: the memory page or leaf address that makes a mistake in order to storage, its employed amount is with to cut apart the amount of error that block allows corresponding, as shown in Figure 5, a 2G bit (～231 bit) SDRAM (address A30:A0), each memory page or leaf is 4K (～212 bit) (address A11:A0), i.e. the total individual memory page or leaf of 512K (219) (address A30:A12).Segmented table according to the Fault Distribution of Fig. 5, every 8K memory page or leaf (32M size) allowed 2 false memory pages or leaves (memory location), and arrange 2 corresponding memory bodys to remove to deposit the address of false memory page or leaf, same, every 16K, 32K, 128 memory pages or leaves are additionally to increase the address that 2,2 and 4 corresponding memory bodys remove to deposit the false memory page or leaf respectively.And we need increase by 1 bit and confirm whether have or not defective (if this bit value does not have a defective for " 0 " expression; Be " 1 " expression defectiveness), so for 8K (225size) memory body scope, the size of each corresponding memory body should be (2G/32M) * (displacement address+1) bit.In this this displacement address (address offset) is (A30:A25).
Comparator array 330: be the address after input address 380, address limiter 310 screenings of comparison access requirement and the output address of corresponding memory body 320, judging whether being different memory body address zone, and conclude whether wrong existence.When the input address 380 of SDRAM access requirement entered memory chip, this address will be screened by memory body address limiter 310 earlier.After the process screening was passed through, the output address of input address 380 and corresponding memory body 320 will be compared device 330 simultaneously and check whether be different memory body address zones.This comparison will produce delay (delay), but memory body will carry out its normal operation in relatively, and therefore not having any effect can lose by Damage.If there is not the defective page or leaf to be found, its address will still carry out data access according to normal procedure; Can find to have a rub-out signal can be sent to scrambler 340 as the defectiveness page or leaf.
Scrambler 340: after scrambler 340 receives rub-out signal, will set up a repairing address and correspond to repair memory body 350, this repair memory body 350 has comprised the heavily information of mapping address.Repair address and be to be set up by special coding method, it will comprise 2 kinds of data: the one, and from that memory page or leaf mistake that scope was allowed to, another is the part of input address.
Repair memory body 350: repair memory body 350 points to a new heavily mapping address again with the aforementioned memory page or leaf address that obtains to need to repair of should encoding, and stores these data.Should get Decision as for the size of repair memory body 350 and allow limit in the faulty page of length of repairing address and cutting distributed areas.
Multiplexer 360: be that the wrong enable signal that produced by comparator array 330 is controlled, so that former input address is selected by system or heavily the mapping address reads data.
Flow process of the present invention as shown in Figure 8, comprise the following steps: system boot (as step 401) after, carry out test-based examination to find wrong address and distribution (as step 402) thereof in memory chip; When in the scope that is distributed in advance planning of mistake, then set up the segmented table (as step 403) of a Fault Distribution; When the distribution generation of mistake concentrates on a certain scope, then set up the segmented table of a Fault Distribution and set address limiter 310 (as step 404), memory controller input address is to address limiter 310 (as step 405) then, then comparator array 330 checks that according to the segmented table of Fault Distribution whether input address 380 is in different address scopes (as step 406); If do not have the mistake of discovery, then will import address 380 mappings to SDRAM, and the mapping address read data (as step 407) thus; If find mistake, to produce a wrong enable signal to multiplexer 360, isolate SDRAM and former input address, so that system can not read data to former input address, and produce a rub-out signal to scrambler 340 (as step 408), so scrambler 340 is set up one at mistake and is repaired address (as step 409), and repair memory body 350 points to a new heavily mapping address (as step 410) again according to repairing address, heavily the mapping address replaces former input address (as step 411) simultaneously, and last data will be read out (as step 412) from the SDRAM of heavy mapping address.
In sum, provided by the present invention a kind of to produce the framework and the method for the segmented table to repair Dynamic Random Access Memory of remembering the page fault distribution, can make the SDRAM producer need not abandon the product of those inevitable defectives, more can significantly reduce test and the extra cost cost of repairing, increase the SDRAM producer's interests,, file an application in accordance with the law so met the important document of Patent Law invention, please auditor's sifting, and pray patent early.
Below the present invention has been done a detailed description, the above can not limit scope of the invention process.To being familiar with the personage of this technology, the variation when carrying out various equivalences to it all should be included in spirit of the present invention and the scope.
Claims (11)
1. a method that produces the segmented table of memory page fault distribution is to produce when start or memory body test each time, it is characterized in that including the following step:
A. memory body is divided into a plurality of memory pages or leaves with suitable size;
B. according to the possible errors amount of the corresponding every 4K of the statistical data of memory body Fault Distribution * 2n scope;
C. to make repeated segmentation as cutting apart unit corresponding to above-mentioned memory page or leaf scope;
D. set the corresponding memory body number and the comparison of tolerable false memory number of pages, arrangement storage false memory page or leaf address
Device quantity.
2. the method for the segmented table that generation memory page fault according to claim 1 distributes, it is characterized in that: among the step b, n is the integer more than or equal to 1, promptly with scopes such as 8K, 16K, 32K, 64K, 128K.
3. the method for the segmented table that generation memory page fault according to claim 1 distributes, it is characterized in that: step c is 1 o'clock with n, be to serve as the cutting unit with every 8K memory page or leaf, then steps d is set and is allowed that 2 false memory pages or leaves exist, and arrange to have 2 corresponding memory bodys and 2 comparers.
4. the method for the segmented table that generation memory page fault according to claim 1 distributes, it is characterized in that: step c is 2 o'clock with n, be to serve as the cutting unit with every 16K memory page or leaf, then steps d is set and is allowed that 2 false memory pages or leaves exist, and arrange to have 2 corresponding memory bodys and 2 comparers.
5. the method for the segmented table that generation memory page fault according to claim 1 distributes, it is characterized in that: step c is 3 o'clock with n, be to serve as the cutting unit with every 32K memory page or leaf, then steps d is set and is allowed that 2 false memory pages or leaves exist, and arrange to have 2 corresponding memory bodys and 2 comparers.
6. the method for the segmented table that generation memory page fault according to claim 1 distributes, it is characterized in that: step c is 5 o'clock with n, be to serve as the cutting unit with every 128K memory page or leaf, then steps d is set and is allowed that 4 false memory pages or leaves exist, and arrange to have 4 corresponding memory bodys and 4 comparers.
7. the method for the segmented table that generation memory page fault according to claim 1 distributes, it is characterized in that: the segmented table that this memory page fault distributes is built in the memory chip in being.
8. one kind to produce the framework of the segmented table to repair Dynamic Random Access Memory that the memory page fault distributes, and includes:
A plurality of address limiters, be in the segmented table that the memory page fault distributes, when finding that amount of error is cut apart the block restriction above this, will remedy the mistake that this cuts apart the block excess to use the lower wrong limit of cutting apart block of other error rate to the memory body address restriction of this block;
A plurality of corresponding memory bodys are the memory page or leaf address that make a mistake in order to storage, and its employed amount is with to cut apart the amount of error that block allows corresponding;
A plurality of comparator arrays are the address after the screening of the input address of comparison access requirement and address limiter, judging whether being different memory body address zone, and conclude whether wrong existence, and produce rub-out signal to scrambler;
Scrambler is to receive to set up one after the rub-out signal and repair address and correspond to repair memory body;
Repair memory body is that the aforementioned memory page or leaf address that obtains to need to repair of should encoding is pointed to a new heavily mapping address again, and stores these data.
9. the method for the segmented table that generation memory page fault according to claim 8 distributes, it is characterized in that: it also comprises a multiplexer, be that the wrong enable signal that produced by comparator array is controlled, so that former input address is selected by system or heavily the mapping address reads data.
10. the method for the segmented table that generation memory page fault according to claim 8 distributes is characterized in that: this repairing address comprises an address bit and an affirmation bit.
11. the method with the segmented table to repair Dynamic Random Access Memory of generation memory page fault distribution includes the following step:
A. system boot;
B. carry out test-based examination to find wrong address and distribution thereof in memory chip;
C. when in the wrong scope that is distributed in planning in advance, then set up the segmented table of a Fault Distribution;
D. when wrong distribution generation concentrates on a certain scope, then set up the segmented table and the setting of a Fault Distribution
The address limiter;
E. import address to the address limiter;
F. whether comparer inspection input address is in different address scopes;
G. if there is not the mistake of discovery, then will import the address mapping to memory body, and the mapping address is read data thus;
H. if find mistake, will produce a wrong enable signal so that system can not read data to former input address,
And produce a rub-out signal to scrambler;
I. this scrambler is set up one at this rub-out signal and is repaired address;
J. repair memory body points to a new heavily mapping address again according to this repairing address;
K. with this heavily the mapping address replace former input address;
L. data will be read out from the memory body of this heavy mapping address.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01110463 CN1380605A (en) | 2001-04-11 | 2001-04-11 | Rack construction using error distributed segmented table to repair memory body and its method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01110463 CN1380605A (en) | 2001-04-11 | 2001-04-11 | Rack construction using error distributed segmented table to repair memory body and its method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1380605A true CN1380605A (en) | 2002-11-20 |
Family
ID=4658606
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 01110463 Pending CN1380605A (en) | 2001-04-11 | 2001-04-11 | Rack construction using error distributed segmented table to repair memory body and its method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1380605A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7529997B2 (en) | 2005-03-14 | 2009-05-05 | International Business Machines Corporation | Method for self-correcting cache using line delete, data logging, and fuse repair correction |
| US7770067B2 (en) | 2005-10-27 | 2010-08-03 | International Business Machines Corporation | Method for cache correction using functional tests translated to fuse repair |
-
2001
- 2001-04-11 CN CN 01110463 patent/CN1380605A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7529997B2 (en) | 2005-03-14 | 2009-05-05 | International Business Machines Corporation | Method for self-correcting cache using line delete, data logging, and fuse repair correction |
| US7770067B2 (en) | 2005-10-27 | 2010-08-03 | International Business Machines Corporation | Method for cache correction using functional tests translated to fuse repair |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5822256A (en) | Method and circuitry for usage of partially functional nonvolatile memory | |
| CN1093641C (en) | Memory testing apparatus | |
| JP4308637B2 (en) | Semiconductor test equipment | |
| CN1045133C (en) | Semiconductor memory apparatus | |
| US8037376B2 (en) | On-chip failure analysis circuit and on-chip failure analysis method | |
| CN1106018C (en) | Dimension programmable fusebanks and methods for making the same | |
| US8095832B2 (en) | Method for repairing memory and system thereof | |
| US7237154B1 (en) | Apparatus and method to generate a repair signature | |
| Jeong et al. | A fast built-in redundancy analysis for memories with optimal repair rate using a line-based search tree | |
| US20100169705A1 (en) | Backup line allocation apparatus, memory repairing apparatus, backup line allocation method, memory manufacturing method, and recording medium | |
| KR20000067917A (en) | Semiconductor memory tester with redundancy analysis | |
| CN1264127A (en) | Semiconductor memory device with redundancy memory circuit | |
| US6119049A (en) | Memory module assembly using partially defective chips | |
| KR101373668B1 (en) | An apparatus and a Built-in Redundancy Analysis for memory repairing | |
| Huang et al. | A simulator for evaluating redundancy analysis algorithms of repairable embedded memories | |
| CN101002282B (en) | Semiconductor storage device and redundancy method for semiconductor storage device | |
| CN1212397A (en) | Apparatus and method for analyzing circuit test results and recording medium storing analysis program | |
| CN1819062A (en) | Method and apparatus for providing flexible modular redundancy allocation for memory built in self test of sram with redundancy | |
| CN1380605A (en) | Rack construction using error distributed segmented table to repair memory body and its method | |
| US8694838B2 (en) | Cache memory, processor, and production methods for cache memory and processor | |
| CN1577633A (en) | Method for reading out defect information item of self integrated chip and integrated memory chip | |
| US20040225939A1 (en) | Built-in self test system and method for two-dimensional memory redundancy allocation | |
| US20040054815A1 (en) | Circuit and/or method for automated use of unallocated resources for a trace buffer application | |
| US20230317198A1 (en) | Dynamic fault clustering method and apparatus | |
| EP0096030A1 (en) | ARRANGEMENT FOR FAST DETERMINATION OF LOCATIONS IN LARGE STORAGE. |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| AD01 | Patent right deemed abandoned | ||
| C20 | Patent right or utility model deemed to be abandoned or is abandoned |