CN1379461A - Dual Damascene Process for Interconnect Structure - Google Patents

Abstract

A method for fabricating an interconnect structure using a dual damascene process. The interconnect structure has a dielectric layer and a photoresist layer formed thereon. The method of the present invention forms a channel pattern and a dielectric layer window pattern in the photoresist layer, and transfers the channel pattern and the dielectric layer window pattern to the dielectric layer to etch a channel and a dielectric layer window in the dielectric layer. The trench pattern and the via pattern can be formed in the photoresist layer by using only a single mask. The single mask includes a trench defining portion having a first transmittance to define a pattern for a trench in a photoresist, and a via defining portion having a second transmittance to define a pattern for a via in a photoresist. The first and second transmission coefficients may each include a different phase of light.

Description

Dual Damascene Process for Interconnect Structure

The present invention relates to a semiconductor process, and more particularly to an improved dual damascene process for fabricating interconnect structures.

The dual damascene process for interconnect formation includes:

1. First etch a trench in the first dielectric layer.

2. Fill the trench with a metal such as aluminum or copper.

3. Use chemical mechanical polishing (CMP) to remove the extra metal on the trench.

In the dual damascene process, a plurality of vias and channels are patterned on the first and second dielectric layers respectively, and the vias and channels are filled with metal, and then chemical mechanical Grinding removes excess metal so that the metal is only present in the holes and channels.

The main advantage of the dual damascene process is that it eliminates the need for metal etching, which is important especially for copper metals that are difficult to pattern by conventional plasma etching. The second advantage is that the ability to eliminate dielectric trench filling is a big challenge for companies, especially as structures move toward smaller sizes.

FIG. 1A to FIG. 1G are diagrams illustrating the process of a conventional dual damascene fabricating interconnection structure.

FIG. 1A illustrates a method for patterning a photoresist to form an interconnection structure, and defining a via pattern in a first photoresist layer. The structure includes a substrate 2 , a thin dielectric layer 4 (such as silicon dioxide), and a first photoresist layer 6 coated on the silicon dioxide layer 4 . The first mask layer 8 is used to define a via pattern in the photoresist layer 6 .

FIG. 1B illustrates the local interconnect structure after the via pattern 7 of the first mask layer 8 is formed in the photoresist layer 6 by known lithography techniques.

1C illustrates that the silicon dioxide layer 4 is etched to obtain the same via 10 as the via pattern 7, and then the local interconnect structure of the photoresist layer 6 is removed.

FIG. 1D illustrates a method of fabricating an interconnection structure from the second photoresist layer 12 with trench patterns.

FIG. 1E illustrates the local interconnect structure after the channel pattern 13 of the second mask layer 11 is formed in the photoresist layer 12 by known lithography techniques.

FIG. 1F illustrates that the silicon dioxide layer 4 is etched to obtain the local interconnection structure of the channel 14 identical to the channel pattern 13 .

FIG. 1G illustrates the local interconnect structure after removing the photoresist layer 12 . Metal can be deposited in via 10 and trench 14 by this method.

The process steps illustrated in FIGS. 1A-1G require two photoresist layers 6 , 12 and two masks 8 , 11 , and additionally require two separate etching process steps. (FIG. 1C and FIG. 1F) Unfortunately, these additional process steps increase the cost, the time of the process cycle, and increase the variability of the process.

In addition, layer-to-layer alignment control, such as the number of reticles in a process, increases in importance as component dimensions shrink. Conversely, reducing the number of mask layers used can reduce the alignment error problem, so that the layer-to-layer alignment control capability will increase to a satisfactory result.

The object of the present invention is to provide a dual damascene process of an interconnection structure, which can reduce the number of process steps in the process of forming the via window and the channel.

Another object of the present invention is to provide a dual damascene process for an interconnection structure, which can reduce the required number of photoresist layers and photomasks during the formation of vias and trenches.

Another object of the present invention is to provide a dual damascene process for interconnection structures, which can utilize a single photoresist layer and a single mask layer to reduce the alignment problem of using multiple masks in the past.

Yet another object of the present invention is to provide a dual damascene process for an interconnection structure, which can simultaneously form a via pattern and a channel pattern by using a single photoresist layer and a single mask layer.

Based on the above purpose, a dual damascene process that can overcome the disadvantages discussed above is proposed to provide a method for manufacturing an interconnection structure.

In order to accomplish the object of the present invention, a dual damascene process of an interconnection structure is proposed. The interconnection structure has a dielectric layer, and a photoresist layer is formed on it. In the method of the present invention, a channel and a via are etched into the dielectric layer by means of the photoresist layer on which the channel pattern and the via pattern have been formed, and the channel pattern and the via pattern are transferred to in the dielectric layer.

According to one example of the present invention, a single mask can be used to form the channel pattern and the via pattern in the photoresist layer. The single mask includes a channel defining portion having a first transmittance to define a pattern in the photoresist as a channel, and a via defining portion having a second transmittance to define a pattern in the photoresist. Define the pattern as the via in the photoresist. The first transmittance coefficient and the second transmittance coefficient may respectively include different phases.

In order to make the above and other advantages and features of the present invention understandable, a detailed description will be given referring to the patent specification and accompanying drawings.

Graphic description:

The invention is described by way of non-specific examples and in conjunction with the accompanying drawings. References to the same parts will have the same numerals and symbols in the different figures unless a difference is meant.

1A to FIG. 1G are partial diagrams illustrating the steps of fabricating an interconnection structure in a conventional dual damascene process.

The partial diagrams of FIGS. 2 to 7 illustrate the steps of fabricating the interconnect structure in an example of the present invention.

FIG. 8 illustrates a top view of a reticle of the present invention illustrated in FIG. 3 .

FIG. 9 illustrates a side view taken through the line 9'-9' of FIG. 8. FIG.

Explanation of reference signs:

2: Substrate

4: Dielectric layer

6: The first photoresist layer

7, 60: via pattern

8: The first mask layer

10, 78: Vial

11: Second mask layer

12: Second photoresist layer

13, 59: channel pattern

14, 74: channel

30: base

34, 44: insulating layer

38: First etch stop layer

48: Second etch stop layer

54: photoresist layer

58: pattern

64: mask

70: Quarantine

80: metal layer

84, 88: Side isolation area

94, 98: Defining Quarantines

Example

In order to fully understand the present invention, multiple detailed descriptions, such as materials, thicknesses, continuous processes, etc., will be presented in the following detailed description. However, if it is obvious that it is a technique in the present invention, its detailed description will not be given. In order to avoid unnecessary obscurity to the present invention, well-known semiconductor industrial processes, materials, and equipment, for example, are not described in detail.

The invention will be described in terms of a dual metallization process. The technique of varying the metallization weight is obviously a common technique, and the invention applies equally to single-weight and multiple-weight devices. However, the present invention also applies to other known conventional technologies and interconnect structures without difficulty.

The partial diagrams of FIGS. 2 to 6 illustrate the steps of fabricating the interconnect structure in an example of the present invention.

FIG. 2 illustrates a local interconnect structure after photoresist 54 deposition. The structure includes a substrate 30, a first insulating layer 34 is deposited in the substrate 30, a first etch stop layer 38 is deposited in the first insulating layer 34, and a second insulating layer 44 is deposited in the first etch stop layer 38. , followed by a second etch stop layer 48 .

The substrate 30 may be made of a semiconductor material, such as silicon or gallium arsenide (GaAs), as a semiconductor substrate, or a dielectric layer may be formed of an insulating material. When the substrate 30 is a semiconductor substrate, the substrate 30 may include transistors, semiconductors, and other known semiconductor components. When the substrate 30 is a dielectric layer, the substrate 30 may include vias and contacts (not shown) that provide electrical conduction between the interconnects and the bonding circuitry of the lower structure (not shown).

The first insulating layer 34 and the second insulating layer 44 are not limited to be made of dielectric layers, such as silicon dioxide. The first etch stop layer 38 and the second etch stop layer 48 are not limited to silicon nitride layers. The insulating layers 34, 44 and etch stop layers 38, 48 may be deposited using conventional techniques, such as spin-on deposition (SOD) or chemical vapor deposition (CVD).

A photoresist layer 54 is coated on the second etch stop layer 48 . For example, the thickness of the photoresist layer 54 can be from 0.4 μm to 2.0 μm. This thickness is the same as a conventional photoresist layer. For the present invention, a single photoresist layer 54 is used that includes the trench pattern and the via pattern.

FIG. 3 illustrates a local interconnect structure after the photoresist layer 54 has a distinct pattern 58 . Pattern 58 is formed in photoresist 54 using a single mask 64 and known lithography techniques.

According to the present invention, the pattern 58 includes both a channel pattern 59 and a via pattern 60 . In conventional processes, separate photoresists are used for each pattern, in other words, one photoresist includes the channel pattern and the second photoresist includes the via pattern. In addition, previous technologies were limited to a single pattern per photoresist.

In accordance with the present invention, a single mask 64 is used to establish the channel pattern 59 and the via pattern 60 in the photoresist 54 . The mask 64 includes patterns that produce different thicknesses in the photoresist with different transmittance coefficients or different phase shifts. For example, the thickness of the photoresist 54 under the via pattern 60 is very small or zero, while the thickness of the photoresist 54 under the channel pattern 59 is in the range of 0.2 μm to 1.5 μm. The mask 64 will be described in detail later when referring to FIG. 7 and FIG. 8 .

FIG. 4 illustrates the local interconnect structure after the trench 74 has been etched into an isolation portion 70 . A first chemical etch is specifically used to etch the second etch stop layer 48 and the second insulating layer 44 to establish the isolation region 70 . The etching stops until the first etch stop layer 38 is reached. If the photoresist is not removed to protect the first etch stop layer 38 , the etch must be selective to the first etch stop layer 38 . (such as the chemical etch cannot remove the first etch stop layer 38 or only has a minimal impact on the first etch stop layer 38) For example, for example, a chemical method based on fluorinated carbon or with Fluorocarbon-based reactive ion etching (RIE) would not significantly attack the silicon nitride layer 38 for etching the silicon dioxide layer 44 .

FIG. 5 illustrates the local interconnect structure after via 78 is formed. A different form or a second chemistry that is the same as the first chemistry can be used to etch through the first etch stop layer 38 and the first insulating layer 34 .

FIG. 6 illustrates the local interconnect structure after any excess or remaining photoresist 54 has been stripped. A conductive metal 80 (including but not limited to copper, aluminum, or tungsten) is then deposited to fill via 78 and trench 74 by known techniques, as shown in FIG. 7 . Metal deposition techniques may utilize physical vapor deposition (PVD), electroplating, or chemical vapor deposition (CVD). Appropriate adhesion/barrier layers and source layers (eg copper source from copper electroplating) are deposited prior to host metal deposition as is known. The extra conductive material can be removed using known techniques such as chemical mechanical polishing (CMP) or etch back techniques before proceeding to the next process. Especially when the metal is etched back, the upper surface of the metal will form a plane with the upper surface of the second etch stop layer 48 .

FIG. 8 illustrates a top view of a reticle 64 of the present invention illustrated in FIG. 3 . FIG. 9 illustrates a side view taken through the line 9'-9' of the reticle 64 of FIG. In the context of the present invention, a single photoresist layer 54 and a single mask 64 are used to create the pattern in the photoresist layer 54 . By using the single mask 64, the present invention (1) saves process time and cost, (2) improves process efficiency, and (3) avoids the cost of two or more masks in the process. Alignment error problem. Therefore, it can be used in mass production.

By way of example, the mask 64 includes two light-tight side isolation regions 84 , 88 . The side isolation regions 84, 88 each have a transmittance index or coefficient of 0%. (that is, no light penetrates the isolation regions) The mask 64 also includes a channel defining the isolation region 94 to establish the channel pattern on the photoresist 54, and a via defining the isolation region 98 to establish the channel pattern on the photoresist 54. The boundary layer pattern of the resistance 54.

A trench defining the isolation region 94 has a first transmittance, eg, in the range of 20% to 80%. A via defining isolation region 98 has a second transmittance such as 100% or slightly lower than 100%. The transmittance factor (also referred to as the transmittance index) is expressed as a percentage and can be attributed to the amount of light passing through the isolated regions of the reticle.

Different isolation regions in the mask may also have different phase transitions. For example, a channel defining isolation region 94 has a first phase, eg, in the range of 0° to 180°. The phase is expressed in degrees and is attributable to the amount of phase shift of light passing through the isolation regions of the reticle.

The present invention is understandably corrected as (1) only the transmittance index between two different reticle 64 isolation regions; (2) only the phase of the different reticle 64 isolation regions; (3) or the different reticle Transmittance index and phase of 64 isolation regions. The present invention can selectively change parameters to create a pattern in the photoresist 54 for special purposes. It is important that both the channel pattern 59 and the via pattern 60 are formed in the photoresist 54 . For example, both the channel pattern 59 and the via pattern 60 are formed in the photoresist 54 at the same time.

By way of example, differences in transmittance index and phase between a channel defining isolation region 94 and a via defining isolation region 98 result in variations in the thickness of photoresist 54 passing through pattern 58 . In other words, a via defining isolation region 98 is used to create via pattern 60 , and a trench defining isolation region 94 is used to create channel pattern 59 . A higher transmittance index will allow more light to pass through the isolated regions of the mask 64, whereas the isolated regions of the photoresist 54 exposed under the isolated regions 94 or 98 have more light and are compared to those exposed to less light. The isolation region of the photoresist 54 reduces the thickness of the photoresist 54 in comparison. The thickness of the photoresist 54 directly under the via pattern 60 (in this example, the photoresist 54 has no or very small thickness) is smaller than the thickness of the photoresist 54 directly under the trench pattern 59. Come thin. In contrast, the present invention can use different transmittance indices, phases, or both to selectively control the thickness of the same pattern in the photoresist 54 .

Thus, the single mask 64 and method of the present invention allow all steps of the process of FIGS. 1A-1G to be minimized. For example, the present invention may actually render the steps of FIG. 1C, FIG. 1D, and FIG. 1E unnecessary, saving process time.

Although the invention is described in relation to a dual damascene process, the invention can be used to increase overall efficiency, reduce cost, process time, and layer-to-layer for any process that uses two or more masks to create vias and trenches Alignment issues.

In the foregoing detailed description, the invention has been described in terms of a specific embodiment. However, various obvious modifications and changes can be made without departing from the spirit and scope of the invention. On the contrary, the description and diagram focus on the meaning of the description and limit the meaning.

Furthermore, the details of the structure and the fabrication of the provided structure may vary and may or may not be required to select the isolation regions of the structure according to the actual material and know the strength and constraints required by the process of the material. Other detailed descriptions not provided are those of known or determined to be of ordinary skill and have been deliberately omitted to avoid obscuring the nature of the invention. Changes in the method and structure of the present invention are contemplated, as long as they do not violate the spirit and scope of the present invention defined in the claims.

Claims (29)

1. A double-embedding process of an interconnection structure, characterized in that: comprising the following steps: (a) depositing a first insulating layer on a substrate; (b) depositing a second insulating layer on the first insulating layer; (c) depositing a photoresist layer on the second insulating layer; and (d) forming a channel pattern and a via pattern in the photoresist layer. 2. The dual damascene process of interconnect structure as claimed in claim 1, wherein the step (d) further comprises: The channel pattern and the via pattern are simultaneously formed in the photoresist layer using a single mask. 3. The dual damascene process of interconnection structure as claimed in claim 2, is characterized in that: further comprises: using the single mask including a channel defining portion having a first transmittance to be defined in the photoresist as the channel pattern and including a via defining portion having a second transmittance to Defined in the photoresist as the via pattern. 4. The dual damascene process of the interconnection structure as claimed in claim 3, wherein the first light transmittance of the single mask ranges from 0% to 100%, and the second light transmittance is 100% %. 5. The dual damascene process of the interconnection structure as claimed in claim 3, wherein the channel definition portion having the first transmittance coefficient is defined in the photoresist as the channel pattern, A first phase is included, and the via-defining portion with a second transmittance, defined in the photoresist as the via pattern, includes a second phase. 6. The dual damascene process of the interconnect structure as claimed in claim 5, wherein the first phase ranges from 0 degrees to 180 degrees, and the second phase is 0 degrees. 7. The dual damascene process of the interconnect structure according to claim 1, wherein the step of depositing the first insulating layer further comprises: the step of depositing a first etch stop layer over the first insulating layer; and The second insulating layer is deposited on the first etch stop layer. 8. The dual damascene process of the interconnect structure according to claim 7, wherein the step of depositing the second insulating layer further comprises: Deposition of a second etch stop layer on the second insulating layer. 9. The dual damascene process of interconnect structure as claimed in claim 8, characterized in that: further comprising: etching a trench in the second etch stop layer; and The channel is etched in the second insulating layer. 10. The dual damascene process of interconnect structure as claimed in claim 9, characterized in that: further comprising: etching a via in the first etch stop layer; and The via is etched in the first insulating layer. 11. The dual damascene process of interconnect structure as claimed in claim 10, characterized in that: further comprising: remove any excess photoresist; and Filling a conductive metal into the via and the trench. 12. The dual damascene process of interconnection structure as claimed in claim 11, characterized in that: further comprising: The conductive metal is ground such that the top surface of the conductive metal is planar with the top surface of the second etch stop layer. 13. An etching method of a dual damascene process using a single photoresist layer to form a trench and an interconnection structure of a via in a dielectric layer, characterized in that: comprising: (a) forming a channel pattern and a via pattern in the photoresist layer; and (b) transferring the channel pattern and the via pattern into the dielectric layer. 14. The etching method of the double damascene process of the interconnection structure as claimed in claim 13, wherein the step (a) comprises using a single photomask to form the channel pattern and the interposer in the photoresist layer Layered window pattern. 15. The etching method for the dual damascene process of the interconnect structure according to claim 14, wherein the step (a) further comprises simultaneously forming the channel pattern and the via pattern in the photoresist layer . 16. The etching method for the dual damascene process of the interconnection structure as claimed in claim 14, characterized in that: further comprising: The single mask includes a channel defining portion having a first transmittance for defining the channel pattern in the photoresist, and a via defining portion having a second transmittance for defining in the photoresist The photoresist is defined as the via pattern. 17. The etching method of the dual damascene process of the interconnection structure as claimed in claim 16, wherein the first light transmittance of the single mask ranges from 0% to 100%, and the second light transmittance then 100%. 18. The etching method for the dual damascene process of the interconnection structure as claimed in claim 16, wherein the channel definition portion having the first transmittance coefficient is defined in the photoresist as the channel The trace pattern includes a first phase, and the via-defining portion with the second transmittance is defined in the photoresist as the via pattern includes a second phase. 19. The etching method for the dual damascene process of the interconnection structure as claimed in claim 18, wherein the first phase ranges from 0 degrees to 180 degrees, and the second phase is 0 degrees. 20. The etching method for the dual damascene process of the interconnection structure as claimed in claim 13, further comprising completely etching the channel pattern in the dielectric layer. 21. The etching method for the dual damascene process of the interconnect structure as claimed in claim 20, further comprising completely etching the via pattern in the dielectric layer. 22. The etching method for the dual damascene process of the interconnect structure according to claim 21, further comprising: remove any excess of the photoresist; and Filling a conductive metal into the via and the trench. 23. The etching method for the dual damascene process of the interconnect structure according to claim 22, further comprising: The conductive metal is ground such that the top surface of the conductive metal is planar with the top surface of the second etch stop layer. 24. A dual-embedding process of an interconnection structure, characterized in that: comprising: (a) depositing a photoresist over a fabrication structure having a first insulating layer and a second insulating layer; (b) defining a channel pattern and a via pattern in the photoresist using a single mask; (c) completely etching the channel pattern and the via pattern in the first insulating layer and the second insulating layer. 25. The dual damascene process of the interconnect structure as claimed in claim 24, wherein the step (b) further comprises: using a single mask including a channel defining portion having a first transmittance to be defined in the photoresist as the channel pattern and including a via defining portion having a second transmittance to Defined in the photoresist as the via pattern. 26. A single photomask for etching a trench pattern and a via pattern, characterized in that it comprises: a channel defining portion having a first transmittance to define a channel pattern; and A via definition portion has a second transmittance coefficient to define a via pattern. 27. The single mask as claimed in claim 26, wherein the first transmittance ranges from 0% to 100%, and the second transmittance is 100%. 28. The single mask of claim 26, wherein the channel defining portion includes a first phase, and the via defining portion includes a second phase. 29. The single mask as claimed in claim 28, wherein the first phase ranges from 0 degrees to 180 degrees, and the second phase ranges from 0 degrees.

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