CN1378214A - High-speed multiplex first-in-first-out memory structure - Google Patents

Abstract

A high-speed multi-channel first-in first-out memory structure comprises at least two memory cell arrays, an integral decoding circuit positioned between the at least two memory cell arrays, a write-in control circuit and a read-out control circuit respectively positioned above and below the integral decoding circuit, two data input buffers respectively positioned on the at least two memory cell arrays, and two multiplexing circuits and two output circuits sequentially positioned below the two memory cell arrays, wherein a write-in clock buffer and a read-out clock buffer are respectively arranged above and below the integral decoding circuit.

Description

High-speed multiplex first-in-first-out memory structure

The present invention relates to a memory structure such as dynamic random access memory (SRAM), and more particularly to a high speed multiplex first-in-first-out memory structure.

A memory structure that provides a huge storage capacity (referring to a large size) in a single chip is widely used in electronic systems, such as computers, communications, and consumer electronics equipment and the like. Recent advances in semiconductor technology, especially the provision of complete systems on a single chip, have made it possible to embed a memory in an integrated circuit so that it is possible to make the integrated circuit act like a complete system.

As the industry tends to continuously increase the number of memory bits of each chip, the size of embedded memories applied to high-speed, dual-frequency, multiplexed output, and demultiplexed input is gradually increasing.

Figure 1 shows a large-scale memory structure with high-speed dual-frequency, multiplexed output, and multiplexed input in the past, including a global decoder circuit (global decoder circuit) 11, four two-two points placed in the global decoder circuit 11 two side and connected to the memory cell array (memory cell array) 12 of the overall decoding circuit 11, a write control circuit (write control circuit) 13 located on the overall decoding circuit 11 and connected to the overall decoding circuit 11, and a write control circuit (write control circuit) 13 located on the overall decoding circuit 11 Below and connected to the read control circuit (read control circuit) 14 of the overall decoding circuit 11, a pre-decoder located between the overall decoding circuit 11 and the read control circuit 14 and connected to the overall decoding circuit 11 and the read control circuit 14 A circuit (pre-decoder circuit) 15, a read clock buffer (read clock buffer) 16 located under the read control circuit 14, a write clock buffer (write clock buffer) 17, and two intervals are arranged in parallel in each A data output buffer (data input buffer) 18 on the memory cell array 12 and connected to the write clock buffer 17. The overall decoder 11 is composed of a write-in overall decoding part 111 and a read-out overall decoding part 112 . Each memory cell array 12 is formed by a region decoder 121 and two unit cell sub-arrays 122 respectively located on both sides of the region decoder 121, and each unit cell sub-array 122 is a memory cell array with m columns and n rows, A multiplexer 123 connected to each row, a sense amplifier 124 connected to the multiplexer 123, and an output circuit 125 connected to the sense amplifier 124 are arranged under each unit cell sub-array 122, and each output circuit 125 is connected to a readout Clock buffer 16.

The following describes the writing and reading operations of the conventional memory structure:

1. Write operation:

The data that needs to be written into the corresponding storage unit will be sent to the data input buffer 18. When the address group corresponding to these data is sent to the write control circuit 13, the write control circuit 13 is used to generate the control signal required for writing into the storage unit. The address group is decoded by writing into the overall decoding part 111 and the area decoding circuit 121 to determine which column of memory cells to be located in the corresponding address group to start driving, and the write clock buffer 17 is used to generate a clock signal (clocksignal ) is synchronously transmitted to the corresponding storage unit by controlling the data in the data input buffer 18, so as to write the data into the storage unit to complete the write operation.

2. Readout operation:

When the address group to be read is sent to the read control circuit 14, the read control circuit 14 is used to generate the control signal required for reading the memory cell, and through the pre-decoding circuit 15, read the whole decoding part 112 and the area The decoding part 121 decodes the address group to determine which row of memory cells is driven, and the data stored in the memory cells is sent to the multiplexer 123 through the control of the control signal, and the multiplexer 123 determines which memory cells. can be output, and the data of which memory cells cannot be output, and the data output by the multiplexer 123 is amplified by the sense amplifier 124 and then sent to the output circuit 125, and finally the read clock buffer 16 generates a clock signal to control the output circuit 125 synchronously sends data to an external device.

However, the previous memory structure still has the following disadvantages:

1. The circuit clock may be inconsistent:

Since the write clock circuit 17 and the read clock circuit 16 are on the same side of the overall decoding circuit 11, the path to the data input buffer 18 on the other side of the overall decoding circuit 11 is too long, and the process of transmission is due to Due to the RC effect, the time to arrive at the different positions 181 and 182 of the data input buffer 18 may differ too much, so that it cannot work synchronously, resulting in inconsistencies in the hidden clocks of the overall circuit. The clock signal is disturbed.

2. The data transmission may be wrong:

Because of the multiplexing output, the data of the weak signal sent by the memory cell array 12 must be transmitted to the multiplexer 123 through the bit line (bit line), but in the transmission process, because the weak signal on the bit line is actually Transmitted on a long-distance metal wire, the capacitive effect (coupling effect) of the long-distance metal wire will interfere with the correct weak signal, causing it to generate a wrong signal. For example, the signal originally intended to transmit logic "1" is due to the capacitive effect A logic "0" is formed, thus causing the problem that the data transmitted from the memory cell array to the multiplexer may be wrong.

3. The size of the overall circuit is too large:

In the conventional memory structure, each memory cell array 12 needs to be provided with a regional decoding circuit 121, so that the memory cell array 12 must be expanded laterally to increase the size, resulting in the overall decoding circuit 11 to the regional decoding circuit 121 to control the opening and driving of the memory cells. The path is lengthened, and an error signal may be generated due to the RC effect, and the path from the data input buffer 18 to each storage unit is also lengthened thereupon. In order to avoid the attenuation of the data signal, the data input buffer 18 for amplifying the data signal also follows The increase, resulting in the overall circuit size is too large.

An object of the present invention is to provide a high-speed multi-channel FIFO memory structure capable of shortening the transmission path of a clock signal of a clock buffer.

Another object of the present invention is to provide a high-speed multi-channel FIFO memory structure that can realize the effect of accurate transmission of clock signals and consistent clocks of the entire circuit.

Another object of the present invention is to provide a high-speed multiplex FIFO memory structure capable of correctly transmitting data.

Another object of the present invention is to provide a high-speed multi-channel FIFO memory structure that can effectively utilize the area and effectively reduce the size.

To achieve the above object, the present invention is a high-speed multi-channel FIFO memory structure, comprising at least two memory cell arrays, an integral decoding circuit, a write control circuit, a read control circuit, two data input buffers, a Write clock buffer, two multiplexing circuits, two output circuits and one read clock buffer, wherein:

Each memory cell array is arranged into m columns and 2n rows, and each column of memory cells in the column of memory cells has a set of corresponding word lines and a regional decoding unit arranged in the column, so that each memory cell array A region decoder is formed in

The overall decoding circuit is located between the at least two memory cell arrays and connected to the area decoders of each memory array, and the overall decoding circuit and the area decoder are used to decode the external address group to determine the corresponding bit The turn-on driving of the word line of the column memory cell of the address group;

The writing control circuit is located above the overall decoding circuit and connected to the overall decoding circuit to receive an external address group and generate a writing control signal required for writing into the memory unit, together with the address group sent to the overall decoding circuit;

The read control circuit is located below the overall decoding circuit and connected to the overall decoding circuit to receive an external address group and generate a read control signal required to read the memory unit, together with the address group sent to the overall decoding circuit;

Each data input buffer is connected to the corresponding memory cell array for temporarily storing and amplifying the data to be input to the corresponding memory cell in the memory cell array;

The write clock buffer is located above the write control circuit and is connected to the data input buffer for controlling the data temporarily stored in the two data input buffers to be synchronously input to the corresponding memory cells in the memory cell array;

Each multiplexing circuit is connected to the memory cells of 2n rows of each memory cell array with a bit line, and is used to receive and selectively output the data output by the memory cells in the 2n rows;

Each output circuit is respectively connected to a corresponding multiplexing circuit for temporarily storing and amplifying the data output by the multiplexing circuit; and

The read clock buffer is connected to the two output circuits for synchronously outputting the data in the at least two output circuits to an external device;

Therefore, when the write address group is input to the write control circuit and the data is input to the data input buffer, the write control circuit generates a write control signal and the overall decoding circuit and the area decoder for the write bit The address group is decoded to drive the memory cell column corresponding to the address group to be turned on and in the write state, and the write clock buffer is controlled to synchronously input the data in the data input buffer to the memory cell; on the contrary, when the read When the address group is input to the readout control circuit, the readout control circuit generates a readout control signal and the overall decoding circuit decodes the readout address group to drive the memory cell row corresponding to the address group to open and In the read state, the data stored in the memory unit is transmitted to the multiplexer circuit, and through the multiplexer circuit, the data is selectively output to the corresponding output circuit for temporary storage according to the readout address group, and the readout The clock buffer controls the synchronous output of the data temporarily stored in the output circuit.

Below in conjunction with accompanying drawing and embodiment the present invention is described in detail:

FIG. 1 is a schematic diagram of a conventional memory structure;

Fig. 2 is a schematic circuit diagram of a preferred embodiment of the present invention;

Fig. 3 is the schematic circuit diagram of another preferred embodiment of the present invention;

Fig. 4 is a schematic circuit diagram of a region decoding unit of the region decoder in Fig. 2;

FIG. 5 is a schematic circuit diagram of a region decoding unit of the region decoder in FIG. 3 .

Before the present invention is described in detail, it should be noted that like reference numerals are used to designate like elements throughout the specification.

Please refer to shown in Fig. 3, the present invention is aimed at and can satisfy double frequency, multiplex output (multiplex output), demultiplex input (demultiplex input), large-scale embedded (embedded) dynamic random access memory (SRAM) ) needs to design. A preferred embodiment of the present invention includes four memory cell arrays (memory cell array) 2, a global decoder circuit (global decoder circuit) 3, a write control circuit (writecontrol circuit) 4, a read control circuit (read control circuit) ) 5. Two data input buffers (data input buffer) 6, one write clock buffer (writeclock buffer) Freq1, two multiplexing circuits 7, two output circuits 9 and one read clock buffer (read clock buffer) Freq2 .

Each memory cell array 2 is arranged into a matrix of m columns and 2n rows, and in the column of memory cells, each column of memory cells has a set of corresponding bit lines (bit line) 211 and a center set in the column The area decoding unit 221 in is used to divide each memory cell array into two m×n unit cell sub-arrays 21 and a area decoder 22 located in the two arrays 21 .

The global decoding circuit 3 is located in the center of the memory cell array 2, and both sides of the global decoding circuit 3 are respectively connected to the regional decoders 22 of the two memory cell arrays 2 by global word lines. The overall decoding circuit 3 and the area decoder 22 are used to decode the external address group to determine the turn-on driving of the word lines of the column memory cells corresponding to the address group. The overall decoding circuit 3 is formed by a write-in overall decoding part 31 and a read-out overall decoding part 32 .

The writing control circuit 4 is located above the overall decoding circuit 3 and connected to the overall decoding circuit 3 to receive an external writing address group and generate the writing control signal required for writing into the storage unit, together with the bit The address group is transmitted to the writing overall decoding part 31 of the overall decoding circuit 3 .

The readout control circuit 5 is located below the overall decoding circuit 3 and is connected to the overall decoding circuit 3 to receive an external readout address group and generate the readout control signals required for reading out the memory cells, together with the bits The address group is transmitted to the read-out overall decoding part 32 of the overall decoding circuit 3 for decoding. In this embodiment, a pre-decoder circuit (Pre-decoder circuit) 51 is further arranged between the readout control circuit 5 and the overall decoding circuit 3, and the readout unit of the readout control circuit 5 and the overall decoding circuit 3 is connected. The decoding section 32 is used for partial decoding before the address group is sent to the reading decoding section 32.

The two data input buffers 6 are connected to an external device (not shown in the figure) and respectively connected to the two memory cell arrays 2 for temporarily storing and amplifying data sent by the external device to be input into the memory cell array 2 .

The write clock buffer Freq1 is located above the write control circuit 4, closer to the two data input buffers 6 than in the past, and connected to these data input buffers 6 to generate a clock signal (clock signal) to control temporary storage. The two data input buffers 6 are synchronously input to the corresponding memory cells in the memory cell array 2 .

The two multiplexing circuits 8 are respectively disposed on two sides of the readout control circuit 5 and are respectively located below the two memory cell arrays 2 . In this embodiment, each multiplexing circuit 8 includes two first multiplexers 81 and a second multiplexer 82 between the two first multiplexers 81, wherein the second multiplexer 82 is a bit The lines are respectively connected to the memory cells of the n rows of the adjacent unit cell sub-array 21 in the two memory cell arrays 2 above it, and the two first multiplexers 81 are respectively connected to the other unit cell sub-array in the two memory cell arrays 2 21 rows of memory cells, that is, the second multiplexer 82 is connected to 2n rows of memory cells, and the connected cell sub-array 21 is located at the center of the two memory cell arrays 2 . Each multiplexer 81, 82 is used to receive the data output from each connected bit line, and selectively (ie, determine according to the address group) which bit line data to output.

Each output circuit 9 includes three amplifying circuits 91 respectively connected to the corresponding multiplexers 81, 82 for temporarily storing the data output by the multiplexers 81, 82 and amplifying the current of these data to strengthen the driving of the data. ) capability for easy transmission to external devices.

The read clock buffer Freq2 is connected to the two output circuits 9 to generate a clock signal (clock signal) to control the output of data temporarily stored in the two output circuits 9, so that the data in the two output circuits 9 can be synchronously output to External devices (not shown in the figure). Generally speaking, the frequencies of the clock signals generated by the write clock buffer Freq1 and the read clock buffer Freq2 are different.

It is worth noting that, in order to strengthen the weak signal transmitted by the bit line between the memory cell array 2 and the multiplexing circuit 8, to effectively avoid the problem that the previous signal is interfered by the capacitive effect and cause errors, so in this embodiment A sense amplifier circuit 7 is arranged below two memory cell arrays 2 respectively, and each sense amplifier circuit 7 includes two first sensor cells connected to the n-row memory cells of the primary unit cell sub-array 21 of the memory cell array 2 respectively. An amplifier (sense amplifier) SA1 and a second sense amplifier SA2 located between the two first sense amplifiers SA1 and respectively connected to n rows of memory cells in a unit cell sub-array 21 of the two memory cell arrays 2 . The same as the multiplexer, the second sense amplifier SA2 is connected to 2n rows of memory cells, and each first sense amplifier SA1 is connected to n rows of memory cells, and the unit cell sub-array 21 connected to the second sense amplifier SA2 Located in the middle of the unit cell sub-array 21 to which the first sense amplifier SA1 is connected. In addition, each first sense amplifier SA1 is respectively connected to the corresponding first multiplexer 81 , and each second sense amplifier SA2 is respectively connected to the corresponding second multiplexer 82 . Therefore, the data of the weak signal output by the memory cells of each row first enters the corresponding sense amplifiers SA1 and SA2, and the weak signal of the data is amplified into a full-swing signal, and then transmitted to the multiplexing circuit 81 on the bit line, so that Effectively avoid the problem that weak signals are susceptible to interference in the past.

In order to make the present invention easier to understand, the write and read operations of this embodiment are described in the following paragraphs:

1. Write operation:

When the write address group is input to the write control circuit 4, and the data is input to the data input buffer 6 for temporary storage, the write control circuit 4 generates a write control signal, and together with the write address group is input to the whole The decoding circuit 3, and the writing overall decoding part 31 and the area decoder 22 of the overall decoding circuit 3 decode the writing address group to drive the memory cell column corresponding to the address group to open, and due to the write control signal After being controlled to be in the write state, the write clock buffer Freq1 controls the data temporarily stored in the data input buffer 6 to be synchronously input to the storage unit in the write state for write operation, so that the data can be written into the corresponding address In the memory cells of the group, the write operation is completed, and because the write clock buffer Freq1 of the present invention is arranged above the write control circuit 4, it is closer to the data input buffer 6 than the conventional memory structure, so that the transfer clock The path of the signal is shorter than before, so the data input buffer 6 located on the left and right sides of the write clock buffer Freq1 is extremely balanced, and the two data input buffers 6 will not cause the clock signal to reach the buffer 6 due to the RC effect The time difference at different points on the Internet is too large, which effectively avoids the disadvantage that it may not be possible to work synchronously in the past.

2. Read operation:

When the readout address group is input to the readout control circuit 5, the readout control circuit 5 generates a readout control signal, and the readout address group passes through the pre-decoding circuit 51 to the readout overall decoding part 32 of the overall decoding circuit 3, Therefore, in the read operation, the read address group is decoded by the pre-decoding circuit 51 and the read whole decoding part 32 to drive the memory cell columns corresponding to the address group to be turned on, and these cells are activated by the read control signal. The memory cells are in the readout state, so the data stored in these memory cells are output to the sense amplifier circuit 7, and the sense amplifier circuit 7 amplifies the data that is still a weak signal, so that it becomes the full-scale data and then passes the bit Line output to the multiplexing circuit 8, and then through the multiplexing circuit 8, selectively output data to the corresponding output circuit according to the read address group to amplify the current of the data to increase the driving capability of the data, and finally read the clock buffer Freq2 The generated clock signal is used to control the synchronous output of the data temporarily stored in the output circuit to the external device. It can be seen that the present invention first amplifies the data through the sensor amplifier circuit 7, and then transmits it to the multiplexing circuit 8, which is different from the previous method of directly transmitting the data of weak signals to the multiplexer, so it can effectively avoid the previous method. False signals occur due to weak signals being disturbed by capacitive effects.

Please refer to FIG. 3 , which is a schematic circuit diagram of another embodiment of the present invention. It differs from the foregoing embodiments in that the area decoder 22 ′, in order to solve the problem that the area decoder 22 ′ occupies a large area in the memory cell array 2 Disadvantages, so in this embodiment, part of the area decoder 22' is set outside the memory cell array 2, instead of setting all the area decoders in the memory cell array 2, and because the memory cell array 2' and the data There is still free space between the input buffers 6, so the part 222' of the area decoder is placed on the memory cell array 2'. The area decoder 22' of this embodiment can be respectively arranged in the main part 223' in the memory cell array 2' and the peripheral part 222' outside the memory cell array 2', wherein the peripheral part 222' is not connected with the main part 223' is connected to the writing control circuit 4. The peripheral part 222' may include at least one logical parameter of the regional decoder 22'. For example, please refer to FIG. 4, when the regional decoding unit 221 of the regional decoder 22 in FIG. When the gate (AND gate) is 23, assuming that the signals input to the three input terminals are A, B, and C respectively, then the output terminal signal Y=ABC, and use the De Morgan's laws (De Morgan's laws) shown in the following formulas 1 and 2 to perform operations :

  AB...＝ A+ B+… (Formula 1)

  A+B+...＝ A· B… (Formula 2)

so $Y=\mathrm{ABC}=\stackrel{\‾}{\stackrel{\‾}{\left(\mathrm{AB}\right)C}}=\stackrel{\‾}{\stackrel{\‾}{\left(\mathrm{AB}\right)}+\stackrel{-}{C}}$

Therefore, as shown in Figure 5, a NAND gate 24 (NAND gate) with two input terminals can be used to input signals A, B and an inverter 25 (NOT gate) to input signal C respectively, and then a NOR gate can be used to 26 (NOR gate) to receive the output of both, so that the output Y=ABC of the NOR gate 26, so in this example, the peripheral part 222' of the area decoder 22' can be the inverter 25, and the main part 223 ' is the remaining NAND gate 24 and NOR gate 26.

In summary, the present invention does have the following advantages:

1. The clock signal can be accurately transmitted and the overall circuit clock is consistent;

Because in the present invention, the two clock buffers Freq1 and Freq2 are respectively arranged on the upper and lower sides of the overall decoding circuit 3 and are located in the middle of the overall circuit, which is different from placing the two clock buffers on the same side of the overall circuit in the past, so On the one hand, the present invention makes the feed-in of the clock signal to the components (such as the data input buffer 6 and the output circuit 9) respectively located on its left and right sides more balanced; It is short in the past, so that the present invention can effectively avoid the shortcomings of the clock signal distortion caused by the overly long transmission path of the clock signal in the past, and make the time error of the clock signal arrive at different positions on the data input buffer 6 within the allowable value, and then reach the overall The circuit clock is consistent and the data input buffer 6 can work synchronously.

2. The data can be transmitted correctly;

In the present invention, the data of the weak signal is first amplified by the sensor amplifier circuit 7 and then transmitted to the multiplexing circuit 8, which is different from the previous method in which the data is directly sent to the long-distance metal wire (bit line) and transmitted to the multiplexer. In the present invention, the data is first amplified into a full-scale signal, so it can avoid the occurrence of wrong signals due to the interference of weak signals by capacitive effects in the past, and achieve the effect that the memory cell array 2 can transmit correct data to the multiplexing circuit 8 .

3. Effective use of area;

In the present invention, based on the idea of effectively utilizing the area, the part (peripheral part 222') of the area decoder 22' is moved to the outer area of the memory cell array 2, so that the area occupied by the area decoder 22' can also be reduced. , so that the memory cell array 2 will not be excessively expanded laterally due to the regional decoder 22, so that the bit lines written into the overall decoding circuit to each memory cell array 2 can be shortened accordingly, so as to reduce the chance of generating error signals due to the RC effect, And the path from the data input buffer 6 to each storage unit can also be shortened thereupon, so in order to amplify the signal and avoid the data input buffer 6 that signal attenuation is useful also shrinks thereupon, so that the overall size can be reduced thereupon, and then reach more effective Utilize the effect of area.

Claims (7)

1, a kind of high speed multiplex first-in first-out storage structure is characterized in that comprising:

At least two memory cell arrays, it is capable with 2n that each memory cell array is aligned to the m row, and each array storage unit has one group of corresponding word lines and and is arranged at regional decoding unit in these row in putting in this array storage unit, makes and forms a regional decoding device in each memory cell array;

One global solution decoding circuit, be positioned at the centre of this at least two memory cell array, and be connected to the regional decoding device of each memory cell array, and this global solution decoding circuit and regional decoding device be in order to decoding to external address group, drives with the unlatching of decision to the word line of array storage unit that should the address group;

One write control circuit is positioned at the top of this global solution decoding circuit and is connected to this global solution decoding circuit, in order to receiving external address group, and produces the required write control signal of write storage unit, is sent to this global solution decoding circuit together with this address group;

One read-out control circuit is positioned at the below of this global solution decoding circuit and is connected to this global solution decoding circuit, in order to receiving external address group, and produce read storage unit required read control signal, be sent to this global solution decoding circuit together with this address group;

Two data input buffers are connected to this at least two memory cell array, wait to import the data of corresponding stored unit in the memory cell array in order to temporary and amplification;

One writes clock buffer, is positioned at the top of this write control circuit, and is connected to data input buffer, inputs to synchronously in the memory cell array in the corresponding stored unit in order to control the data in this two data input buffer of being temporary in;

Two duplex circuits, each duplex circuit connects the 2n line storage unit of this corresponding stored cell array with bit line, and in order to receive data and the selectivity output that the storage unit of this 2n in capable exported;

Two output circuits connect this corresponding duplex circuit respectively, in order to the temporary data of being exported by this duplex circuit with amplification; And

One readout clock impact damper connects this two output circuit, uses so that the data sync in this two output circuit exports external device (ED) to;

Therefore, when writing the address group and import this write control circuit and this data and input to data input buffer, this write control circuit produces this write control signal, with this global solution decoding circuit and this regional decoding device this being write the address group decodes, with drive column of memory cells that should the address group opened and is positioned at write state after, this writes clock buffer and is controlled in that data sync inputs in the storage unit in the data input buffer; On the contrary, when reading the address group when importing this read-out control circuit, this read-out control circuit produces this and reads control signal, and this global solution decoding circuit is read the address group to this and is decoded, to drive column of memory cells that should the address group is opened and is positioned at the state of reading, be stored in the interior data transmission of storage unit to this duplex circuit, read address group selection output data to this correspondence output circuit through this duplex circuit according to this and keep in, and export by the data sync that this readout clock impact damper control is temporary in the output circuit.

2, high speed multiplex first-in first-out storage structure as claimed in claim 1 is characterized in that:

Also comprise two respectively to should at least two memory cell array settings and the sensing amplifying circuit used of amplifying signal, and these two sensing amplifying circuits lay respectively between this corresponding memory cell array and the duplex circuit and are connected both, the data that cause memory cell array output earlier after the sensing amplifying circuit amplifies again to this corresponding duplex circuit.

3, high speed multiplex first-in first-out storage structure as claimed in claim 1 is characterized in that:

Each regional decoding device comprises that a main part and that is arranged in this memory cell array is positioned at the outer periphery of this memory cell array, and wherein this periphery connects this main part and this write control circuit.

4, high speed multiplex first-in first-out storage structure as claimed in claim 3 is characterized in that:

Each regional decoding device comprises a plurality of logic parameters, and each periphery comprises a wherein logic parameter of each regional decoding device at least.

5, as claim 3 or 4 described high speed multiplex first-in first-out storage structures, it is characterized in that:

Each periphery is a phase inverter.

6. high speed multiplex first-in first-out storage structure as claimed in claim 1 is characterized in that:

This global solution decoding circuit is to write whole decoded portion and by one to read whole decoded portion and formed.

7. high speed multiplex first-in first-out storage structure as claimed in claim 1 is characterized in that:

Also comprise a predecode circuit between this global solution decoding circuit and this read-out control circuit, in order to the address group of reception by this read-out control circuit output, and the decoding of going ahead of the rest, be resent to this global solution decoding circuit.

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