CN1378291A - Light emitting diode array with optical isolation structure and manufacturing method thereof - Google Patents

Abstract

A light emitting diode array with an optical isolation structure and a manufacturing method thereof are provided. The light emitting diode array with the optical isolation structure comprises a substrate, a plurality of light emitting diode units and a plurality of deep grooves, wherein the light emitting diode units and the deep grooves are arranged on the substrate. The LED array substrate with the optical isolation structure is a semiconductor material with a lower energy gap, and the plurality of LED units are made of another semiconductor material with a higher energy gap. The plurality of deep grooves are distributed between every two adjacent light emitting diode units and at least comprise a light reflecting metal layer. By using the deep trenches and the substrate with lower bottom energy gap, the cross talk phenomenon of the LED array can be avoided, and the image resolution is improved.

Description

Light-emitting diode array with optical isolation structure and manufacturing method thereof

The invention relates to a light-emitting diode array used in a light-emitting diode instrument panel (LED Display), or a light-emitting diode printer (LED Printer) and a manufacturing method thereof. In particular, the present invention relates to a light-emitting diode array with an optical isolation structure and a manufacturing method that can save the manufacturing cost of the light-emitting diode array.

In recent years, due to the development of light-emitting diode (Light-Emitting diode, LED) blue light technology and the improvement of brightness, as well as its advantages of low power consumption and cold light emission, light-emitting diodes were only used for indication purposes in the past, such as power "ON/OFF" display lights , has now begun to be widely used in lighting and full-color display screens, which are different from traditional purposes.

A light emitting diode array is formed by neatly arranging a plurality of independent light emitting diode units, which can be used as a large display screen or panel. Please refer to US Patent Nos. 4,628,422 and 4,851,824. Generally, such physical arrays of light emitting diodes can be assembled with relatively simple packaging technology. However, when the size of the device is reduced, such as the LED array used in a small LED panel or display, the volume of the internal LED units is quite small, which makes its assembly technology more difficult. This point can be found in US Patent No. 5,014,074. Such a display using a 2D LED array to display an image, for example, may require tens of thousands of LED units to form an image display. Therefore, how to accurately assemble a plurality of independent LED units into a neat array, and the circuit configuration of each LED unit will consume time and money in this packaging process, far exceeding the manufacturing cost of the LED unit itself.

In addition, in the light-emitting diode array as a light source device, for example, a single-row light-emitting diode array for light-scanning light-emitting diode printer (LED Printer), because it does not need high-speed rotating polygonal mirror, it has a higher laser The size of the printer is smaller, and the assembly work is greatly simplified. However, one of the technical bottlenecks of this type of LED printer is that when it is used as a light source LED array, its image resolution will deteriorate due to cross-talk interference between adjacent LED units. The same situation can also be seen in LED displays made of LED arrays.

Based on the above, how to fabricate an LED array with a relatively simple process while avoiding crosstalk between LEDs is an urgent problem.

The object of the present invention is to provide a light emitting diode array with an optical isolation structure, so that the light emitted by each light emitting diode unit does not spread to adjacent light emitting diode units, so that the image resolution is improved.

Another object of the present invention is to provide a method for manufacturing a light-emitting diode array with an optical isolation structure, in which a plurality of light-emitting diode units constituting the light-emitting diode array are manufactured on the same substrate by a semiconductor process, so as to save the production of the light-emitting diode array cost.

According to the present invention, the light-emitting diode array with optical isolation structure includes a substrate composed of low-energy-gap semiconductor chips, and a plurality of light-emitting diode units and a plurality of deep trenches distributed in a network pattern on the substrate. Wherein, each light emitting diode unit is made of a semiconductor material with an energy gap higher than that of the substrate; and each deep groove is between every two adjacent light emitting diode units, and its depth is greater than the height of each light emitting diode unit, And each deep groove contains a reflective metal layer. Meanwhile, the bottom of the substrate has a bottom metal layer.

Using the reflective metal layer in the deep groove, when the light emitted by the light emitting diode unit diffuses to the lateral direction, the laterally emitted light will be reflected by the reflective metal layer; on the other hand, since the energy gap of the substrate is lower than that of the multiple light The diode unit, so when the light emitted by the light emitting diode diffuses downward, the downwardly emitted light will be absorbed by the bottom substrate. Therefore, the light-emitting diode array of the present invention can avoid cross-talk interference between adjacent light-emitting diodes, thereby improving its image resolution.

According to the present invention, the light-emitting diode array with optical isolation structure utilizes a semiconductor process to manufacture a plurality of light-emitting diode units constituting the light-emitting diode array on the same substrate, so the complicated assembly process can be omitted. Moreover, all the structures included in the light emitting diode array can be completed by a semiconductor process. Therefore, according to the manufacturing method of the present invention, the manufacturing cost of the LED array can be reduced.

With regard to the purpose, characteristics and advantages of the present invention, it will become clearer after referring to the following contents and accompanying drawings.

FIG. 1 shows a schematic diagram of the generation path of cross talk in a commonly used LED array. When a light emitting diode unit in a common light emitting diode array emits light, as shown in the figure, there are two ways for crosstalk to occur: one is that the T-type light emitted sideways passes through the boundary and radiates on the surface of the adjacent light emitting diode unit ; The other is that the B-type light emitted downward is reflected by the bottom metal layer, or is absorbed in the middle and then reflected by the bottom metal layer, and radiated on the surface of the adjacent or farther LED unit. Therefore, the other LED units in the LED array will be interfered by the cross-talk formed by the T-type light and the B-type light, affecting their normal lighting effects, thus resulting in a reduction in the overall image resolution of the LED array.

Therefore, the main purpose of the present invention is to fabricate an optical isolation structure between two adjacent light-emitting diode units using a semiconductor process trench technology (Trench Technology), so as to solve the phenomenon of crosstalk between them. Hereinafter, a detailed description will be made on the preferred embodiment of the light emitting diode array of the present invention and its manufacturing method.

Please refer to Figure 2 and Figure 3, Figure 2 shows a plan view of a 2×N-type LED array in a preferred embodiment of the present invention, and Figure 3 shows another N×N matrix LED in a preferred embodiment of the present invention Array floor plan.

Referring to FIG. 4 , it shows a 2×N-type LED array of a preferred embodiment of the present invention, a cross-sectional view drawn in the direction of arrow A in FIG. 2 . At the same time, please refer to FIGS. 5A to 5C , which show a flow chart of manufacturing a light emitting diode array according to a preferred embodiment of the present invention. The structure and manufacturing method of the LED array according to the preferred embodiment of the present invention will be described below with reference to FIGS. 4 and 5A to 5C. In the description of the present invention, if the figures indicate the same number, it means that they are the same part.

According to the present embodiment, the light-emitting diode array uses a gallium arsenide (GaAs) chip as a substrate 201, and then, a layer of aluminum gallium arsenide (AlGaAs) epitaxial layer is grown on the substrate 201 by epitaxy technology (step 1). Afterwards, a PN interface process is performed on the AlGaAs epitaxial layer, so that the AlGaAs epitaxial layer becomes a PN interface layer 202 (see FIG. 5A , step 1). The PN interface layer 202 is the main structure of each LED unit constituting the LED array of this embodiment.

Next, according to this embodiment, the on-chip PN interface layer 202 will be made into a 2×N or N×N matrix pattern with a plurality of light emitting diode units to form a light emitting diode array by using the well-known semiconductor process deep trench technology. At the same time, an optical isolation structure is fabricated between adjacent light-emitting diode units by using well-known semiconductor technology.

Firstly, a layer of positive photoresist is coated on the surface of the PN interface layer 202 by using the well-known etching lithography technology, and then a plurality of light-emitting diode unit areas are defined with the first photomask, followed by exposure and development to make the area to be etched area exposed. Afterwards, anisotropic etching is performed on the exposed area by well-known etching techniques to form trenches with a depth of about several microns to form deep trenches 203 distributed in a network pattern (see FIG. 5A , step 2). Finally, the photoresist on the chip is removed and cleaned. In this way, a plurality of light emitting diode units distributed in 2×N or N×N matrix can be manufactured on one chip at the same time, which saves the complicated assembly process between light emitting diode units. At the same time, another purpose of making the plurality of network-shaped distribution deep trenches 203 is to separate the plurality of LED units and to form an optical isolation structure therebetween. Therefore, the depth of the network-distributed deep trenches needs to be greater than the thickness of the PN interface layer 202 . After this step, a plurality of matrix-type distributed LED units can be produced on the chip, and a plurality of deep grooves 203 distributed between two adjacent LED units are distributed in a network shape.

As mentioned above, according to the present embodiment, the light-emitting diode array has an optical isolation structure capable of blocking light in a plurality of source trenches distributed in a grid pattern. This optical isolation structure can be used to reflect the T-type light of each LED unit, so that it cannot be transmitted into adjacent LED units, so as to avoid crosstalk. Please refer to step 3 of FIG. 5A to step 7 of FIG. 5B for the fabrication method of the optical isolation structure, and the content thereof will be described in detail below.

First, deposit a layer of silicon dioxide or silicon nitride on the surface of the chip by chemical vapor deposition technology as the first insulating layer 204 (see FIG. 5A , step 3). The purpose of making the first insulating layer is to prevent the short circuit between the two ends of the PN interface layer of each light emitting diode unit itself or between the light emitting diode units.

Next, deposit a layer of gold or aluminum-based metal film on the surface of the first insulating layer 204 as the first reflective metal layer 205 (refer to FIG. 5A, step 4).

Afterwards, a layer of glass liquid (SOG, Spin On Glass) is spin-coated on the entire surface of the chip by a planarization process, so as to fill up a plurality of network-shaped distribution deep trenches 203 and form a second insulating layer 206 (see FIG. 5A, step 5). After baking, the chip is fully etched back with well-known etching techniques until the first reflective metal layer 205 on the surface of the plurality of LED units is exposed, so that the surface of the chip has a planarized structure (see FIG. 5B , step 6). Wherein, the above-mentioned spin-on-glass (SOG) can also be replaced by polyimide material to achieve the same planarization and insulation functions.

Afterwards, the chip is fully metal etched to remove the first light-reflective metal layer on the surface of the plurality of LED units, so that the surface of the PN interface layer 202 is exposed (see FIG. 5B , step 7). The first light-reflective metal layer 205 remaining in the network-shaped distribution deep grooves 203 can reflect light from adjacent LED units T, so that it will not be transmitted to another LED unit area.

Fabricating the first insulating layer 204 , the first reflective metal layer 205 and the second insulating layer 206 in the above manner can form an optical isolation structure in the deep trench between two adjacent LED units. The depth of this optical isolation structure will be greater than the height of the PN interface layer 202 of each LED unit, and a reflective metal layer is included therein. Therefore, when each light-emitting diode unit emits light and travels in a lateral manner, it will pass through its adjacent first insulating layer in sequence, irradiate on the first reflective metal layer 205, and then pass through the first reflective metal layer 205. The non-conductive metal layer 205 is reflected back into the original light-emitting area. In addition, the light-emitting diode array substrate material is a gallium arsenide (GaAs) material with an energy gap lower than that of the multiple light-emitting diode unit PN interface layer 202 (note: the PN interface layer 202 is composed of aluminum gallium arsenide, GaAlAs), Therefore, each LED unit radiates downward Class B light, which will be absorbed and attenuated by the GaAs substrate with a lower energy gap at the bottom. Therefore, the light-emitting diode array structure of the present invention can effectively avoid the common cross-talk problem of conventional light-emitting diode arrays.

Next, before making the metal wiring of each light-emitting diode unit, a pad layer 207 is deposited on the entire surface of the chip, so that it covers a plurality of light-emitting diode units and a plurality of deep trenches 203 (see FIG. 5B, Step 8).

Then use the well-known etching and lithography technology to define the area of a plurality of contact windows 208 on the surface pad layers of multiple light-emitting diodes with a second photomask. The surface and the surface of the first insulating layer are etched to expose part of the surface of the PN interface layer of the contact window 208 (see FIG. 5C, step 9).

Remove the photoresist on the chip surface and perform wet cleaning.

On the entire surface of the chip, a layer of aluminum metal layer is deposited, and a third photomask is used to define the area of a plurality of metal connection lines 209 by using the well-known etching and lithography technology. After exposure and development, the exposed aluminum metal layer is removed by well-known etching techniques to produce a plurality of metal interconnections 209 (see FIG. 5C , step 10).

Remove the photoresist on the surface of the chip and perform wet cleaning.

On the backside of the chip, an aluminum metal layer is deposited as the bottom metal layer 210 (see FIG. 5C, step 11).

Finally, the light emitting diode array structure is formed, as shown in FIG. 6 . For convenience of illustration, only a few LED units are drawn in the figure. As shown in the figure, it can be seen that a single light-emitting diode unit is surrounded by network-shaped distribution deep grooves 203 , and below the light-emitting diode unit is a substrate 201 with a lower energy gap and a bottom metal layer 210 . The aluminum metal connection 209 on the surface of the light-emitting diode can introduce a current, so that the PN interface layer 202 constituting the light-emitting diode unit emits a light source. The light emitted by the light-emitting diode will be transmitted outward in a radial manner. As shown in FIG. 1 , in a common light-emitting diode array, emitting T-type light to both sides and downward-radiating B-type light will cause cross talk. However, in the light-emitting diode array of the present invention, as shown in FIG. reflection. The B-type light emitted downward will be absorbed and attenuated by the lower energy gap substrate at the bottom.

Therefore, the light-emitting diode array manufactured according to the method of the present invention can avoid the common cross-talk problem in the commonly-used light-emitting diode array. At the same time, different from the way of assembling a plurality of independent light-emitting diode units with packaging technology in common techniques, the present invention uses semiconductor techniques to fabricate the light-emitting diode array on the same chip. In this way, the process of the light emitting diode array can be simplified, thereby saving the manufacturing cost of the light emitting diode array.

Although the preferred embodiments of the present invention have been described above, various modifications and changes can be made without departing from the spirit and scope of the present invention.

A brief description of the diagram:

Figure 1 is a schematic diagram of a commonly used light-emitting diode array and the way in which crosstalk occurs;

2 is a plan view of a 2×N-type light emitting diode array in a preferred embodiment of the present invention;

FIG. 3 is a plan view of an N×N matrix light-emitting diode array in a preferred embodiment of the present invention;

4 is a cross-sectional view of a 2×N-type light emitting diode array in a preferred embodiment of the present invention;

5A to 5C are flow charts of the fabrication of LED arrays in a preferred embodiment of the present invention;

FIG. 6 is a perspective cross-sectional view of a 2×N-type LED array in a preferred embodiment of the present invention.

Explanation of symbols in the figure:

201 substrate

202PN interface layer

203 deep ditch

204 first insulating layer

205 first reflective metal layer

206 second insulating layer

207 Cushion

208 contact window

209 metal connection

210 bottom metal layer

Claims (12)

1. light emitting diode matrix with optical isoaltion structure comprises:

One substrate, this substrate are a low energy gap semiconductor chip;

A plurality of light emitting diodes are positioned on this substrate, and wherein, each light emitting diode is to comprise a PN interface layer, and are higher than this substrate by an energy gap and can constitute by gap semiconductor material;

A plurality of zanjons are positioned on this substrate, and each zanjon all is between whenever between adjacent in twos this light emitting diode, and in order to separate these a plurality of light emitting diodes, wherein, each zanjon degree of depth is greater than this light emitting diode height;

One first insulating barrier is covered on these a plurality of light emitting diodes and these a plurality of zanjon inner surfaces;

One first reflective metal level is covered on interior this first surface of insulating layer of these a plurality of zanjons;

One second insulating barrier is disposed on interior this first reflective layer on surface of metal of these a plurality of zanjons, in order to fill up this a plurality of zanjons;

One bed course is covered in this a plurality of light emitting diode first insulating barriers, and on the surface of these a plurality of zanjon second insulating barriers;

A plurality of contact holes are positioned on these a plurality of light emitting diodes, in order to penetrate this bed course and this first insulating barrier, make these a plurality of light emitting diode part surfaces expose to the open air out;

A plurality of metal wirings are to be connected to be exposed to these a plurality of LED surfaces in these a plurality of contact holes; And

One bottom metal layers is to be positioned at this base plate bottom.

2. light emitting diode matrix according to claim 1, wherein, constituting this baseplate material is the III-V compound semiconductor.

3. light emitting diode matrix according to claim 1, wherein, constituting these a plurality of light emitting diode PN interface layer materials is that energy gap is higher than this baseplate material III-V compound semiconductor.

4. light emitting diode matrix according to claim 1, wherein, this first insulating layer material is to be silicon nitride or silicon dioxide.

5. light emitting diode matrix according to claim 1, wherein, this second insulating layer material is polyimide or glass metal.

6. light emitting diode matrix according to claim 1, this light emitting diode matrix is used for the printing head luminescence component.

7. light emitting diode matrix according to claim 1, this light emitting diode matrix are used for HUD and use red, blue and green emitting assembly.

8. one kind has optical isoaltion structure light emitting diode matrix manufacture method, and this manufacture method comprises following steps:

With one than low energy gap semiconductor chip as a substrate;

On this substrate with the higher energy gap epitaxial layer of crystal technique growth one deck of heap of stone;

On this epitaxial layer, carry out the PN interface and make, make it become a PN interface layer;

According to design criterion, on this PN interface layer surface, define a plurality of light emitting diode areas with the etching lithographic printing;

Do not carry out etching with etching technique to covering this PN interface layer of photoresistance and this substrate, to produce these a plurality of light emitting diodes and a plurality of zanjon;

On these a plurality of light emitting diodes and these a plurality of zanjon integral surfaces, with plasma auxiliary chemical vapor deposition technology (PECVD) deposition one layer insulating, to constitute first insulating barrier;

On this first surface of insulating layer on these a plurality of light emitting diodes and this zanjon integral surface, deposition layer of metal layer is to constitute the first reflective metal level;

On this first reflective layer on surface of metal on these a plurality of light emitting diodes and this zanjon integral surface, spin coating one layer insulating to fill up this a plurality of zanjons, constitutes second insulating barrier again;

Carry out comprehensive eat-backing with etching technique,, make this substrate upper face planarization to remove this a plurality of zanjons inside this second insulating barrier in addition;

To being exposed to the substrate surface first reflective metal level, carry out comprehensive etching with etching technique;

On these a plurality of light emitting diodes and these a plurality of zanjon integral surfaces, deposition one deck bed course;

According to design criterion, on this this mat surface of a plurality of light emitting diodes, define a plurality of contact hole areas with the etching lithographic printing;

Remove part this a plurality of light emitting diode these first insulating barriers of surface and this bed course with etching technique, to produce this a plurality of contact holes;

On these a plurality of light emitting diodes and these a plurality of zanjon integral surfaces, deposit a metal level;

According to design criterion, on these a plurality of light emitting diodes and this this metal level of a plurality of zanjons surface, define a plurality of metal connecting line areas with the etching lithographic printing;

Remove this metal level on this light emitting diode of part and this a plurality of zanjons surface with etching technique, to produce a plurality of these metal connecting lines; And

On this base plate bottom surface, deposit a metal level again to constitute bottom metal layers.

9. light emitting diode matrix manufacture method according to claim 8, wherein, constituting this baseplate material is the III-V compound semiconductor.

10. light emitting diode matrix manufacture method according to claim 8, wherein, constituting these a plurality of light emitting diode PN interface layer materials is that energy gap is higher than this baseplate material III-V compound semiconductor.

11. the manufacturing of light emitting diode matrix according to claim 8, wherein, this first insulating layer material is to be silicon nitride or silicon dioxide.

12. light emitting diode matrix manufacture method according to claim 8, wherein, this second insulating layer material is polyimide or glass metal.

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