CN1378262A - Manufacturing method of dynamic random access memory capacitor - Google Patents

Abstract

A method for manufacturing DRAM capacitor includes defining active region on a substrate, forming multiple character lines in parallel arrangement on substrate, forming the first and the second plugs at the positions where bit line contact window and node contact window are formed between character lines and filling insulating material in the rest of character lines. Then, a bit line contact window is formed on the first plug, and a plurality of bit lines which are arranged in parallel and are vertically crossed with the character lines are formed on the substrate, wherein the bit lines are electrically connected with the first plug and the substrate through the bit line contact window, the bit lines are electrically insulated from the bit lines, and a hard material layer covers the bit lines. Finally, a node contact is formed on the second plug.

Description

Manufacturing method of dynamic random access memory capacitor

The present invention relates to a semiconductor manufacturing process, in particular to a deep sub-micron (deepsub-micron), dynamic random access memory (Dynamic Random Access Memory, DRAM) capacitor (capacitor) manufacturing method.

DRAM is a widely used integrated circuit component, especially in the information electronics industry is more indispensable. With the development of the industry, the demand for higher-capacity DRAMs has also increased. The related industries have been working hard to meet the requirements of high-capacity density, and how to maintain their original properties while reducing the size of components. One of the common problems faced by people in the industry.

Known stack type dynamic random access memory (stack DRAM) storage cell array generally needs to comprise definition active area (active area, AA) at least, definition word line (word line, WL), definition self-aligned contact window (self-aligned contact, SAC) ), defining the bitline contact (BC), defining the bitline (BL) and the node contact (CN) and other six masks can be completed. 1 is a cross-sectional view of a known stacked capacitor over bit line (COB) DRAM, which uses an isolation structure 102 to define an active region 104 on a substrate 100, including word lines 106, bit lines 108, and capacitors 110. , wherein the bit line 108 and the capacitor 110 are electrically connected to the substrate 100 through the self-alignment contact 112 and the node contact 114 respectively, and the word line, the bit line 108 and the capacitor 110 are insulated by a dielectric material 116 .

The above-mentioned six masks include an island pattern defining the active area 104, two including a line/space pattern defining the word lines 106 and bit lines, and three including an automatic alignment contact contact hole pattern for the window 112, the bit line contact window, and the node contact window 114. With the shrinking of the DRAM chip design rule, the size of the contact window needs to be reduced accordingly, which will be a great challenge for the current lithography process.

In addition, the overlap and alignment between different masks becomes more and more difficult as the device size shrinks, which will limit the process window of the stacked DRAM.

In view of this, the present invention provides a method for manufacturing a DRAM capacitor to improve the process window and overlay margin.

The invention provides a method for manufacturing a DRAM capacitor. After defining the active area on the substrate, a plurality of word lines arranged in parallel are formed on the substrate, and then, between the word lines, a bit line contact window is predetermined to be formed to contact the nodes. The position of the window forms the first plug and the second plug, and insulating material is filled between the rest of the word lines. After that, a bit line contact window is formed on the first plug, and then a plurality of bit lines arranged in parallel and perpendicular to the word line are formed on the substrate, wherein the bit line is connected to the first plug and the substrate through the bit line contact window. The bit lines are electrically connected, and the bit lines are electrically insulated, and the bit lines are covered with a hard material layer. Finally, a node contact window is formed on the second plug.

The present invention further provides a manufacturing method of the DRAM capacitor. After defining the active area on the substrate, a plurality of word lines arranged parallel to each other are formed on the substrate, and the word lines are separated by a gap. Next, filling the first insulating layer in the gap, defining the first insulating layer, forming a first self-aligned contact window opening as a bit line contact window and a second self-aligned contact window opening as a node contact window. Afterwards, filling the openings of the first and second self-alignment contact windows with conductive material to form the first self-alignment contact window and the second self-alignment contact window. Next, a second insulating layer is formed on the word line, and the second insulating layer is defined to form a bit line contact window opening. Next, filling the opening of the bit line contact window with conductive material to form the bit line contact window, so that the bit line contact window can be electrically connected to the substrate through the first self-aligned contact window. Subsequently, a dielectric layer is formed on the second insulating layer, and the dielectric layer is defined to form a plurality of channels perpendicular to the word lines and parallel to each other. Then fill the trench with conductive material to form a bit line, wherein an upper surface of the bit line is lower than the dielectric layer, and the bit line is electrically connected to the first self-aligned contact window through the bit line contact window. Next, a hard material layer is formed on the bit line and the trench is filled. Continue to define the dielectric layer and the second insulating layer, form a node contact window opening, and fill the conductive material in the node contact window opening to form a node contact window, wherein the node contact window is connected to the substrate via the second self-aligning contact window electrical connection.

Both the self-alignment contact window and the node contact window formed by the present invention are carried out by the self-alignment process, which can increase the process window and improve the overlapping range.

In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and understandable, a preferred embodiment is specifically cited, and in conjunction with the accompanying drawings, the detailed description is as follows:

Graphic description:

Fig. 1 is a sectional view of a known stacked DRAM of capacitors on bit lines;

2A-2I are layouts of DRAM capacitors according to a preferred embodiment of the present invention;

3A-3I is a cross-sectional view of the manufacturing process according to the line section of FIG. 2A-2I3-3;

4A-4I is a cross-sectional view of the manufacturing process according to the line section of FIG. 2A-2I4-4;

Figure 5 is a photoresist pattern defining a self-aligning contact window;

Figures 6A-6D are the manufacturing process of a partial section of line 6-6 in Figure 2G; and

Fig. 7-9 is a cross-sectional view of Fig. 2I7-7, 8-8, and 9-9.

Explanation of reference signs:

100, 200 Base 102, 202 Isolation structure

104, 204 active area 106, 206 character line

108, 230 bit line 110 capacitor

112 Automatic Alignment Contact Window 114 Node Contact Window

116 Dielectric material 208 Conductive layer

210 Insulating layer 212 Hard material spacer

214 Clearance 216, 224 Insulation layer

218 Discontinuous T-shaped island photoresist pattern

218a Continuous automatic alignment contact window photoresist pattern

220a, 220b first plug, second plug

226 bit line contact window open 228 bit line contact window

232 dielectric layer 234, 234a channel

236 hard material layers

238 Linear node contact window opening photoresist pattern

240 Node contact window open 242 Node contact window

Please refer to FIG. 2A, FIG. 3A and FIG. 4A at the same time, an isolation structure 202 is formed on the substrate 200 to define and form an active area (active area, AA) 204 including components such as a field effect transistor (field effect transistor, FET) and a capacitor, The definition of the active region 204 is selected to have the largest lithography process window under the condition of meeting the design rule. Wherein, the isolation structure 202 is, for example, a shallow trench isolation (STI), which can be formed by any known technique.

Next, word lines 206 parallel to each other are formed on the substrate 200 . The formation of the word line 206, for example, first forms a gate oxide layer (not shown) on the substrate 200, and then sequentially forms a conductive layer 208 and a cap insulation layer (cap insulation layer) 210 on the gate oxide layer, and then utilizes micro The shadow etching process defines the insulating layer 210, the conductive layer 206 and the gate oxide layer, and forms a hard material spacer 212 on the sidewall of the conductive layer 208, thereby forming the word line 206 shown in FIG. 3A and FIG. 4A, the word line 206 is separated from the word line 206 by a gap 214 .

Wherein, the conductive layer 208 is used as the gate of the field effect transistor and can be made of doped polysilicon or other conductive materials, while the covering insulating layer 210 and the hard material spacer 212 are preferably made of silicon nitride. The source/drain regions (not shown) of the field effect transistors are formed on the substrate 200 beside the word line 206 . The lithographic etching definition process of the word lines 206 is performed using a straight line and constant width photoresist pattern, thus providing the largest process window to meet the process and electrical requirements.

Please refer to FIG. 2B , FIG. 3B and FIG. 4B at the same time, the gap 214 ( FIG. 3A , FIG. 4A ) between the word lines 206 and 206 is filled with an insulating layer 216 . The insulating layer 216 is formed by first forming an insulating material on the substrate 200, such as depositing an oxide by chemical vapor deposition (CVD), covering the word line 206 and extending to the surface of the word line 206, and then ending with the covering insulating layer 210 , planarizing the insulating material by chemical mechanical polishing (CMP) until the upper surface of the insulating coating layer 210 is exposed.

Please refer to FIG. 2C, FIG. 3C and FIG. 4C, and then, utilize a photoresist 218 to define an insulating layer 216, and remove the insulating layer 216 at a predetermined position to form a self-aligned contact (SAC), forming a first The self-aligning contact opening 220a and the second self-aligning contact opening 220b, wherein the first self-aligning contact opening 220a is used for forming a bit line contact later, and the second self-aligning contact opening 220b is used for forming node contact windows later. Afterwards, the photoresist 218 is removed.

The formation of the self-aligning contact window openings 220a, 220b can use a discontinuous T-shaped island PR pattern (T-shape island PR pattern) 218 as shown in FIG. 2C as a photomask, covering part of the character line 206 With the insulating layer 216, under the condition that the silicon nitride layer as the insulating layer 210 and the hard material spacer 212 and the oxide as the insulating layer 216 have a high etching selectivity (etching selectivity), the insulating layer 216 at the predetermined position is etched , forming self-alignment contact openings 220 a , 220 b to expose the substrate 200 . Using the T-shaped island photoresist pattern 218 as a photomask can enlarge the process window defining the self-aligned contact openings 220a, 220b.

In addition, the photomask defining the self-aligning contact window openings 220a, 220b can also be a photoresist pattern 218a as shown in FIG. 5, which is a continuous photoresist pattern. As shown by the photoresist 218a, part of the word line 206 and the insulating layer 216 are covered, and the insulating layer 216 at the position where the self-aligning contact openings 220a, 220b are predetermined to be formed can be removed through the photoresist 218a. Afterwards, the photoresist 218 is removed.

Please refer to FIG. 2D, FIG. 3D and FIG. 4D at the same time, fill the conductive material in the first self-alignment contact window opening 220a and the second self-alignment contact window opening 220b to form the first plug 222a and the second plug 222b , wherein the first plug 222a serves as a first self-aligned contact electrically connected to the substrate 200 for the subsequently formed bit line contact, and the second plug 222b serves as a second contact electrically connected to the substrate 200 as a node contact. Automatic alignment of contact windows. The plugs 222a and 222b are formed by first forming a conductive material on the word line 206, such as forming polycrystalline silicon or tungsten metal by chemical vapor deposition, and then using the chemical mechanical polishing method with the insulating layer 210 as the polishing end point. The conductive material covering the surface of the insulating layer 210 is ground and removed.

Please refer to FIG. 2E, FIG. 3E and FIG. 4E at the same time, an insulating layer 224 is formed on the word line 206, the first plug 222a and the second plug 222b, and then the insulating layer 224 is defined by a lithographic etching method, etched and removed Part of the insulating layer 224 forms a bit line contact hole (CB hole) 226 on the first plug 222a, exposing the first plug. Wherein, the insulating layer 224 forms a thin oxide layer by chemical vapor deposition, for example, and the nitride as the insulating layer 210 and the oxide as the insulating layer 224 have a larger etching selectivity ratio, the etching of the insulating layer 224 The step can stay on the insulating layer 210 without damaging the word line 206 .

Referring to FIG. 2F, FIG. 3F and FIG. 4F, a conductive material is formed on the insulating layer 224, such as polycrystalline silicon or tungsten metal formed by chemical vapor deposition, and filled in the bit line contact window opening 222a, and extends to the insulating layer. 224 surface. Afterwards, the conductive material is polished by a chemical mechanical polishing method to remove the conductive material on the insulating layer 224 and form a bit line contact window 228 on the first plug 222a. Wherein, the bit line contact window 228 is electrically connected to the substrate 200 through the first plug 222a.

Please refer to FIG. 2G , FIG. 3G , FIG. 4G , and FIGS. 6A-6D , wherein FIGS. 6A-6D are part of the manufacturing process of the sectional plane along line 6-6 in FIG. 2G . Next, bit lines 230 parallel to each other are formed on the substrate 200 . The bit line 230 is formed by first forming a blanket dielectric layer 232 on the insulating layer 224 and the bit line contact window 228 to cover the entire wafer, such as forming an oxide layer by chemical vapor deposition. Afterwards, cover the linear bit line photoresist pattern (BLline space pattern) on the dielectric layer 232 again, use the linear bit line photoresist pattern as a mask, define the dielectric layer 232 with the lithographic etching process, and the dielectric layer 232 Form the trench 234 vertically intersecting with the word line, arranged parallel to each other and having the same height as the thickness of the dielectric layer 232, as shown in FIG. The surface of the bit line contact window 228 is exposed.

Next, the bit line 230 is formed in the trench 234. It first fills the trench 234 with a conductive material, such as depositing tungsten metal by chemical vapor deposition, and the conductive material fills the trench 234 and extends to the surface of the dielectric layer 232. . Continue the step of etching back the conductive material in the trench 234. In addition to removing the conductive material on the surface of the dielectric layer 232, etch back the conductive material in the trench 234 to a depth, so that the lower half of the trench 234 The portion has a conductive material to form a bit line 230 as shown in FIG. 6B , and the bit line 230 is electrically connected to the substrate 200 through the bit line contact window 228 and the first plug 222a. Wherein, the surface of the bit line 230 needs to be lower than the surface of the dielectric layer 232, and a barrier layer can be provided between the bit line 230 and the dielectric layer 232 to increase the adhesion between the conductive material and the oxide. Afterwards, an isotropic etching step is performed on the dielectric layer 232, so that the opening of the channel 234 above the bit line 230 is enlarged to form a bowl-shaped opening 234a. Please refer to FIG. 6D, continue to fill the trench 234 with a hard material layer 236, such as a silicon nitride layer. The hard material layer 236 can be formed by chemical vapor deposition, and after filling the trench 234, it extends to the dielectric layer 232. surface, and then use the dielectric layer 232 as the polishing end point, and remove the hard material layer on the surface of the dielectric layer 232 by chemical mechanical polishing, and form a surface not higher than the surface of the dielectric layer 232 as shown in FIG. 3G and FIG. 6D Hard material layer 236 . The enlarged opening 234a allows the filled hard material layer 236 to have a larger surface area, so that the underlying bit line 230 can be avoided from being damaged when the node contact opening is subsequently formed.

Referring to FIG. 2H, FIG. 3H and FIG. 4H, a linear node contact window opening photoresist pattern (space node contact pattern, space CN pattern) 238 as shown in FIG. 2H is formed on the dielectric layer 232 and the hard material layer 236, covering the The dielectric layer 232 and the hard material layer 236 on the first plug 222a need to expose at least the position where the node contact window is to be formed. Next, using the linear node contact opening photoresist pattern 238 as a mask, the dielectric layer 232 and the insulating layer 224 are etched to form a node contact opening 240 to expose the second plug 222b. In the step of defining the node contact window opening 240, since the bit line 230 is covered by the hard material layer 236, when the etching step is performed, the high etching selectivity ratio of the hard material layer 236 to the dielectric layer 232 can make the hard material layer 236 Erosion of the etchant is blocked, so only the exposed dielectric layer 232 can be etched, so that the node contact opening 240 can be automatically aligned on the second plug 222b. Photoresist 238 is then removed.

Next, please refer to FIG. 2I, FIG. 3I and FIG. 4I and FIG. 7, FIG. 8 and FIG. 9, wherein FIG. 7, FIG. 8 and FIG. sectional view. Fill the node contact window opening 240 with a conductive material, such as polysilicon or tungsten metal, fill the node contact window opening 240 and extend to the surface of the dielectric layer 232, and then use chemical mechanical polishing to remove the surface of the dielectric layer 232 The excess conductive material is used to form a node contact hole 242 as shown in FIG. 4I , wherein the node contact hole 242 is electrically connected to the substrate through the second plug 222b. As can be clearly seen from FIG. 9, the hard material layer 236 has a larger surface area than the bit line 230 due to the enlarged bowl-shaped opening 234a (FIG. 6C), so when defining the node contact window 242, damage to Bit line 230 below hard material layer 236 .

So far, the memory cell array is completed, and any known process can be used to fabricate capacitors, such as columnar capacitors, crown capacitors, and the like.

In addition, the preferred embodiment of the present invention uses a process that utilizes self-aligned contacts when forming the self-aligned contacts 222a, 222b and the node contact 242, so that the process window can be increased and the overlapping range can be improved.

Furthermore, in the preferred embodiment of the present invention, the discontinuous T-shaped island-shaped mask pattern 218 is used to define the self-alignment contact window, and the line/space photons are used to define the bit line and node contact windows. Mask pattern, so it can increase the process window.

Although the present invention has been illustrated above with a preferred embodiment, it is not intended to limit the present invention. Any skilled person can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore The scope of protection of the present invention should be defined by the scope of claims.

Claims (28)

1. A method for manufacturing a DRAM capacitor, applicable to a substrate, characterized in that: the method for manufacturing at least includes: defining a plurality of active regions on the substrate; defining a plurality of word lines arranged parallel to each other on the substrate, and the word lines are separated by a gap; filling the gap with a first insulating layer; defining a first insulating layer, forming a first self-aligned contact window opening as a bit line contact window and a second self-aligned contact window opening as a node contact window; filling the openings of the first self-alignment contact window and the second self-alignment contact window with conductive material to form the first self-alignment contact window and the second self-alignment contact window; forming a second insulating layer on these word lines; defining a second insulating layer to form a bit line contact window opening; Filling the opening of the bit line contact window with conductive material to form a bit line contact window, so that the bit line contact window is electrically coupled to the substrate through the first self-aligned contact window; forming a dielectric layer on the second insulating layer; defining a dielectric layer to form a plurality of channels perpendicular to the word lines and parallel to each other; Filling the trenches with conductive material to form a plurality of bit lines, an upper surface of these bit lines is lower than the dielectric layer, and these bit lines are electrically connected to the first self-aligned contact window through the bit line contact window; Form a layer of hard material on the bit line to fill up these trenches; defining a dielectric layer and a second insulating layer to form a node contact opening; and The opening of the node contact window is filled with conductive material to form a node contact window, wherein the node contact window is electrically coupled with the substrate through the second self-aligned contact window. 2. The method for manufacturing a DRAM capacitor according to claim 1, wherein the active regions are defined by a shallow trench isolation structure. 3. The method for manufacturing DRAM capacitors according to claim 1, wherein the word lines are formed by sequentially forming a conductive layer and an insulating layer on the substrate, and then defining the composition of the conductive layer and the insulating layer. A plurality of lines are arranged parallel to each other, and a hard material spacer is formed on the side walls of these lines. 4. The method for manufacturing a DRAM capacitor according to claim 1, further comprising forming a source/drain region on the substrate at the side of the word lines. 5. The method for manufacturing a DRAM capacitor according to claim 1, wherein filling the first insulating layer in the gap comprises: forming an insulating material over the substrate, filling the gap, and extending onto the word lines; and The insulating material is planarized by chemical mechanical polishing to expose the word lines. 6. The method for manufacturing a DRAM capacitor according to claim 1, wherein forming the first self-aligned contact window opening and the second self-aligned contact window opening comprises: forming a discontinuous T-shaped island photoresist pattern on the word line and the first insulating layer; and Using the T-shaped island-shaped photoresist pattern as a mask, etching part of the first insulating layer in the gaps to expose the substrate. 7. The method for manufacturing a DRAM capacitor according to claim 1, wherein the formation of the first self-aligned contact window and the second self-aligned contact window comprises: forming a conductive material on the word line and the first insulating layer, filling the first self-aligned contact opening and the second self-aligning contact opening, and extending to the word line and the first insulating layer; and The conductive material is polished by chemical mechanical polishing to expose the word lines. 8. The method for manufacturing a DRAM capacitor according to claim 1, wherein the forming of the bit line contact window opening comprises: forming a photoresist pattern of a bit line contact window opening on the second insulating layer; and Using the photoresist pattern of the opening of the bit line contact window as a mask, the second insulating layer is etched to expose the first self-aligned contact window. 9. The method for manufacturing a DRAM capacitor according to claim 1, wherein the forming of the bit line contact window comprises: forming a conductive material on the second insulating layer, filling the opening of the bit line contact window, and extending to the second insulating layer; and The conductive material is ground by chemical mechanical polishing to expose the second insulating layer. 10. The method for manufacturing a DRAM capacitor according to claim 1, wherein the formation of the channels comprises: forming a linear bit line photoresist pattern on the dielectric layer; and Using the linear bit line photoresist pattern as a mask, etching the dielectric layer to expose the bit line contact window. 11. The method for manufacturing DRAM capacitors according to claim 1, wherein forming the bit lines comprises: forming a conductive material over the dielectric layer, filling the trenches, and extending over the dielectric layer; and The conductive material filling the trenches is etched back, exposing the dielectric layer, and leaving the trenches with conductive material for only a portion of their depth, serving as bitlines. 12. The method for manufacturing a DRAM capacitor according to claim 1, characterized in that: after forming the bit line, before filling the hard material layer, it includes the step of isotropically etching the trenches, and in these trenches The top half forms a bowl-shaped opening. 13. The method for manufacturing a DRAM capacitor according to claim 1, wherein filling the hard material layer comprises: forming a hard material over the dielectric layer, filling the trenches, and extending over the dielectric layer; and The hard material on the surface of the dielectric layer is removed by chemical mechanical grinding to expose the dielectric layer. 14. The method for manufacturing a DRAM capacitor according to claim 1, wherein forming a node contact window opening comprises: forming a photoresist pattern of a linear node contact window opening on the hard material layer and the dielectric layer; and Using the photoresist pattern of the opening of the node contact window as a mask, etching the dielectric layer and the second insulating layer to expose the base. 15. The method for manufacturing a DRAM capacitor according to claim 1, wherein the formation of the node contact window comprises: forming a conductive material on the dielectric layer and the hard material layer, filling the node contact opening, and extending to the dielectric layer; and The conductive material is ground by chemical mechanical polishing to expose the dielectric layer and the hard material layer. 16. The method for manufacturing a DRAM capacitor according to claim 1, forming the first self-aligned contact window opening and the second self-aligned contact window opening comprises: forming a continuous photoresist pattern of self-aligned contact window openings on the word line and the first insulating layer; and Using the continuous self-aligned contact window opening photoresist pattern as a mask, etching part of the first insulating layer in the gaps to expose the substrate. 17. A method for manufacturing a DRAM capacitor, characterized in that it is suitable for use on a substrate, and characterized in that: the method at least includes: defining a plurality of active regions on the substrate; forming a plurality of character lines arranged in parallel on the substrate; Forming a first plug and a second plug between the word lines at predetermined positions where the bit line contact window and the node contact window are formed, and filling an insulating material between the remaining word lines; forming a bit line contact window on the first plug; A plurality of bit lines arranged in parallel and vertically intersecting these word lines are formed on the substrate, and these bit lines are electrically connected to the first plug and the substrate through a bit line contact window, and the feature is that these bit lines are electrically insulated , and these bit lines are covered with a layer of hard material; and A node contact is formed on the second plug. 18. The method of manufacturing a DRAM capacitor according to claim 17, wherein the active regions are defined by an isolation structure. 19. The method for manufacturing a DRAM capacitor according to claim 17, wherein a conductive layer and an insulating layer are sequentially formed on the base for the word lines, and then the conductive layer and the insulating layer are defined as plural word lines arranged in parallel, and hard material spacers are formed on the side walls of these word lines. 20. The method of manufacturing a DRAM capacitor according to claim 19, wherein the insulating layer and the hard material spacer comprise nitride. 21. The method of manufacturing a DRAM capacitor according to claim 17, further comprising forming a source/drain region on the substrate at the side of the word line. 22. The method for manufacturing a DRAM capacitor according to claim 17, wherein the formation of the first plug and the second plug comprises: Filling conductive material between the word lines, exposing an upper surface of the word lines; and The conductive material located outside the predetermined positions of the bit line contact window and the node contact window is removed to form a first plug and a second plug, respectively serving as a part of the bit line contact window and a part of the node contact window. 23. The method for manufacturing a DRAM capacitor according to claim 17, wherein forming a bit line contact window comprises forming an insulating layer on these word lines, removing the insulating layer on the first plug, exposing the The first plug is then filled with conductive material to form. 24. The method for manufacturing DRAM capacitors according to claim 17, wherein the step of forming these bit lines comprises: forming a blanket dielectric layer on the substrate; Remove part of the blanket dielectric layer to form a plurality of trenches perpendicular to these word lines, exposing the bit line contact window; Filling the trenches with a conductive layer and etching back so that the surface of the conductive layer is lower than the dielectric layer, the conductive layer serves as the bit lines; and A layer of hard material is filled in the trenches. 25. The method for manufacturing a DRAM capacitor according to claim 24, characterized in that: after forming the bit line, before filling the hard material layer, it further includes a step of isotropically etching these trenches, and in these trenches The upper half of the channel forms a plurality of bowl-shaped openings. 26. The method for manufacturing a DRAM capacitor according to claim 24, wherein filling the hard material layer comprises: forming a hard material over the dielectric layer, filling the trenches, and extending over the dielectric layer; and The hard material on the surface of the dielectric layer is removed by chemical mechanical grinding to expose the dielectric layer. 27. The method of manufacturing a DRAM capacitor according to claim 24, wherein the bit line contact window is formed in the insulating layer above the word line, the first plug and the second plug, and wherein The formation of the node contact window includes: forming a node contact opening in the dielectric layer and the insulating layer to expose the second plug; forming a conductive material on the dielectric layer and the hard material layer, filling the node contact opening, and extending to the dielectric layer; and The conductive material is ground by chemical mechanical polishing to expose the dielectric layer and the hard material layer. 28. The method for manufacturing a DRAM capacitor according to claim 27, wherein forming a node contact window opening comprises: forming a photoresist pattern of a linear node contact window opening on the dielectric layer and the hard material layer; and Using the photoresist pattern of the opening of the node contact window as a mask, etching the exposed dielectric layer and insulating layer to expose the second plug.

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