CN1375773A - Buffer control device and management method thereof - Google Patents

Abstract

The invention provides a buffer control device and its management method, so that the buffer control device can be faster in processing packet access and managing the allocation and release actions of buffer memory, the linking structure directly points the linking node of the first buffer register to the last buffer register, then the linking node of the last buffer register points back to the second buffer register, then the second buffer register sequentially serially points to the last buffer register, so that the buffer register with the linking structure can be released back, and the serially linked buffer registers can be quickly released to the unused serial.

Description

Buffer control device and management method thereof

technical field

The present invention is related to a buffer control device (Buffer controller) and its management method. It is further explained that the present invention is a kind of configuration and management of buffer temporary registers (Buffers) using a novel link structure (Linked Structure). A released buffer control device and a buffer register management method thereof.

Background technique

Please refer to Figure 1, which is a block diagram of the connection between the buffer memory and the controller. Usually, a buffer memory 30 is provided between the controller and the device for buffering and management during data access. The buffer memory 30 can be a synchronous dynamic random access memory (Synchronous Dynamic Random Access Memory; SDMM), a A static random access memory (Static Random Access Memory; SMM) or a dynamic random access memory (Dynamic Random Access Memory; DMM); a buffer control device 20 is still connected between the controller 10 and the buffer memory 30, It is used to assist the management of data access between the controller 10 and the buffer memory 30, so as to improve the efficiency of data processing.

Please refer to FIG. 1 , which is a schematic diagram of a conventional buffer management using a Linked List. When starting initialization, a pointer 40 points to the first unused buffer register 30.0001 in the buffer memory 30, and the unused buffer registers 30.0001 to 30.2048 form a linked serial structure, that is, the buffer register 30.0001 Utilize its connection node 30.0002, and the connection node of the buffer register 30.0002 then points to 30.0003, so; continue to point to the buffer register 30.2048, and the connection node of the last buffer register 30.2048 then points to invalid (Null), representing this string The end of the column. Please refer to FIG. 3 , which shows a hardware diagram of the buffer control device implemented by the buffer management in FIG. 2 . The buffer control device 20 is provided with a pointer 40 for recording the address 30.0001 of the first unused buffer register. When initially, the pointer 40 points to the buffer register 30.0001, if the buffer register 30.0001 to 30.0003 is continuously stored in data, then the pointer 40 needs to read the link node of the buffer register 30.0003 to change it The content value points to 30.0004; afterward, if the buffer registers 30.0001 to 30.0003 are used up, the buffer control device 20 should release the buffer registers 30.0001 to 30.0003 that have been used one by one (free) to the last link in the series The front end means that the connection node of the buffer register 30.0003 must change the record and point to the unused buffer register 30.0004 recorded in the original pointer 40, and then the pointer 40 will point to the released buffer register 30.0003, and then Release the buffer registers 30.0002 to 30.0001 one by one to complete the link. It can be seen that, although it is simply to release the buffer register, it involves complex hardware operations, and it needs to report back to the buffer control device 20 to know the first address (First address) and the second address of the release buffer register. Information such as the second address and the segment counter is used for positioning by the pointer 40, but these information all need to occupy memory space. If a large amount of data is transmitted, the load of the SRAM will increase. Moreover, the buffer control device 20 only has one pointer 40, so that the allocation action and the release action are all performed from the front end of the sequence, which will seize the pointer 40, and affect the buffer control device 20's management of the buffer register. efficiency.

Taking the switching controller as an example, the buffer memory system usually allocates memory in units of buffer registers, and the size of each buffer register can be determined according to different applications. The general capacity of the buffer register is mainly 128bytes; for Ethernet packets, the maximum packet length can reach 1522bytes, and the minimum length is 64bytes, so it may be configured to 12 bytes in a segment. A buffer register is used as a storage for packet transmission and reception, and the high-speed transmission characteristics of its static random access memory are used as a communication bridge between the central processing unit and dynamic random access memory to speed up the transmission rate. , but if the switch controller receives the largest Ethernet packets continuously, it needs to use the cache memory to effectively alleviate the load of the serial link, but due to the limited amount of cache memory, in this case the serial link The load of the link is still heavy, and the return speed of the buffer register is very slow, so another more effective management method needs to be found to cope with the current Internet society that is increasingly pursuing speed.

Contents of the invention

The main purpose of the present invention is to provide a buffer control device, which manages the allocation and release of buffer registers with a novel link structure, so as to improve buffer memory access efficiency and simplify the design of hardware architecture.

In view of the fact that the conventional buffer management technology only releases the buffer registers one by one according to the used link sequence when releasing the used segment, it involves complex hardware operations, and the execution efficiency is also low and the SDRAM load Shortcomings such as very heavy, a kind of embodiment of the present invention then arranges a head pointer and a tail pointer in the buffer control device, pointing to the first buffer register address and the last of an unused serial (free lise) respectively A buffer register address, and the buffer control device includes a cache memory for storing the first address of the used partition segment, and the buffer control device configures (allocate) a partition segment first from the cache memory First configure the body first, and then link the buffer registers of the fetching sequence pointed to by the head pointer one by one to form a segment of the serial structure, and point the head pointer to the next buffer register bit of the fetching sequence Address: The buffer control device preferably returns the information of the first address, the second address, the last address (Last address) and the length of the segment of the link segment in the release action (release). The first address is stored in the cache memory, and the buffer register pointed to by the tail pointer points to the second address, and then the last address is directly stored in the tail pointer, so that the segments of the serial structure can be used together String at the end of the unused string.

In another preferred embodiment of the present invention, a novel linking structure is applied to the configuration of the buffer control device, so that the information of the second address can be quickly obtained when the used segment is released. , without having to record in the segment and report back to the buffer control device, the novel link structure is to point the first buffer directly to the last buffer, and then point back to the second buffer After the register, it points to the last buffer register in sequence. Therefore, the release action can quickly obtain the second address through the connection node of the last buffer register, and store the second address in the end The link node of the buffer temporary register pointed to by the pointer, and then store the last address in the tail pointer, so that the segments with the aforementioned link structure can be strung together at the end of the unused sequence without releasing them one by one Node, not only saves memory space to record the second address, but also maintains the original hardware design structure so that the buffer memory can be used efficiently.

The present invention provides a novel link serial structure applied to the buffer control device, so that the buffer control device can process the memory configuration and release action of packet access more quickly, and can effectively save memory space. This enables the buffer memory to be used and managed more efficiently.

Description of drawings

Fig. 1 is the connection block diagram of conventional buffer memory and controller;

FIG. 2 is a schematic diagram of conventional buffer management using a Linked List;

FIG. 3 is a hardware schematic diagram of a conventional buffer control device implemented according to the buffer management of FIG. 2;

Fig. 4 is a schematic diagram of the hardware implemented by the buffer control device of the present invention;

Fig. 5 is a schematic diagram of the buffer control device of the present invention releasing the used string;

FIG. 6 is a schematic diagram of the link structure used in the present invention.

Explanation of the schematic label list:

10 controller; 20 buffer control device, 30 buffer memory; 31 link node; 40 pointer; 50 head pointer; 51 tail pointer; 52 cache memory.

Detailed ways

Please refer to FIG. 4 , which is a schematic diagram of the hardware implemented by the buffer control device of the present invention. The buffer memory 30 includes an unused series (free list), which is formed by a chain of buffer registers, each buffer register has its corresponding link node 31, and this link node 31 has a column The bit acts as a link pointer for the link. In the first embodiment of the present invention, the switch controller manages a buffer memory by a buffer control device to temporarily store the transmission data of the packet. The buffer control device 20 is provided with a header pointer 50 and a tail pointer 51. At the beginning of initialization, it points to the first buffer address 30.0001 and the last buffer address 30.2048 of the unused string respectively. The buffer control device 20 preferably includes a cache memory 52 for pointing to available buffer registers. This unused sequence is pointed to 30.0002 by its connection node of the buffer register 30.0001, and the connection node of the buffer register 30.0002 then points to 30.0003, and thus continues to point to the buffer register 30.2048, and finally the buffer register 30.2048 The link node points to Null, representing the end of this unused sequence.

In the second embodiment of the present invention, it is assumed that the cache memory 52 embedded in the buffer control device of the swap controller has three cache units, and its specific implementation may be an embedded SRAM unit, a flip-flop or a temporary memory and so on. When the switch controller starts to initialize, it will fill the buffer address 30.0001, 30.0002, 30.0003 into the cache memory 52, and the head pointer 50 points to the buffer address 30.0004. When it is required to configure the temporary storage space, the priority is given to the cache memory 52 to request the allocation of memory addresses that can be stored. As in the previous plan, the size of each buffer to be accessed is 128 bytes. It can be found that when the incoming packets are all small packets (minimum 64 bytes), it is only necessary to require the cache memory 52 to configure a buffer It is enough to store, and after use, the address of the buffer register will be returned to the cache memory 52, so it is rarely necessary to use the operation of the head indicator 50, which represents the number of access operations of the SRAM is effectively reduced.

It should be noted that in actual implementation, since the size of each buffer register is planned to be 128 bytes, it is not necessary to actually record the physical address of the buffer register, but only need to record its corresponding buffer register The buffer number (Buffer_ID) is enough. By adding a physical address converter module, the buffer register number can be easily converted into the corresponding physical address, which can effectively speed up the access speed and reduce the correlation Gate counts for hardware design.

In addition, it should be noted that the buffer control device of the present invention can be applied to all situations related to buffer register management, and the embodiment here is described by a switch controller.

In the above-mentioned embodiment, if when the switching controller is required to configure a segment (segment) after initial initialization, the example shows that the length of the required segment segment is 10, and the cache memory 52 will release the buffer first. The temporary register address 30.0001, 30.0002, 30.0003, and it is suitably compiled string (stitch); The next seven buffer temporary registers then go to the buffer temporary register address 30.0004 earlier by the head pointer device 50, and it is compiled string (stitch) to the buffer register address 30.0003, and according to the corresponding link node (link node) of the buffer register address 30.0004, the head pointer 50 is updated to point to 30.0005; then, according to the head pointer 50 to Go to buffer register address 30.0005, and update the head pointer 50 to point to 30.0006. After such configuration one by one, the head pointer 50 finally points to 30.0011, wherein the partition segment has the structure of a linked list (Linked list) , and the buffer registers used by the same packet are also properly serialized, so that these buffer registers can be returned together after the segment segment is used up (after the packet is successfully sent). Afterwards, in this embodiment, if the segments 30.0001 to 30.0010 are used up, it is necessary to report information such as the first address 30.0001, the second address 30.0002, the last address 30.0010 and the length of the segment, The buffer control device 20 stores the first address 30.0001 into the temporary register of the cache memory 52, and then strings the partition segments of the series together at the end of the unused series, that is, stores the second address 30.0002 into the end The pointer 51 points to the link node of the buffer register, and then directly stores the last address 30.0010 into the tail pointer 51 . Therefore, the buffer control device of the switch controller can execute the allocation operation and the release operation at the front end and the end of the unused queue respectively, so as to improve the management efficiency of the buffer control device 20 on the buffer register.

Please continue to refer to FIG. 4, since the number of cache units of the cache memory 52 is limited, preferably, each cache unit includes a mask bit (Full bit) to record whether the corresponding cache unit points to an applicable buffer scratchpad. A Cache_full signal can be generated by passing all mask bits through an AND operation, and a Cache_empty signal can be generated by passing all mask bits through an NOR operation. The Cache_full signal indicates whether the cache memory 52 is full, and the Cache_empty signal indicates whether the available cache addresses in the cache memory 52 have been allocated. Therefore, when the cache control device 20 configures a segment, the cache control device 20 can find out whether there is an available cache address for configuration by checking Cache_emPty, and if so, it will preferentially configure the cache memory from the cache memory 52. if check the Cache_empty signal and find that the cache memory 52 has been configured, then continue to configure the buffer register by the head pointer device 50; in the process of configuring the buffer register, simultaneously link it into a desired The partition section of the used link list structure.

And when releasing the partition segment that has been used up, the buffer control device 20 checks the Cache_full signal to determine whether the cache memory 52 is full. If there is still space, it can be preferentially released back to the cache memory 52. It can be flexibly changed according to the defined structure of the used sequence, and the remaining segments of the used sequence to be released are stringed together at the end of the unused sequence. For example, it can be Store the first address of the used serial partition segment that will be released back into the connection node of the buffer register pointed to by the tail pointer 51, and then directly store the last address into the tail Indicator 51.

In the embodiment of the present invention, all the information reported above can preferably be obtained from the first buffer register used by the packet, and a lot of important information must be recorded, including the total number of buffer registers in this series ( total buffer count), port mask (port mask), priority (priority) and other information; so when the returned information increases, for example: the last address information, the capacity of the first buffer register may be insufficient changes in application usage or hardware design. Therefore, the present invention further discloses a novel link structure applied to the buffer control device.

According to the aforementioned second embodiment of the present invention, in FIG. 5, the cache memory 52 embedded in the switch controller has three cache units. When initializing, the buffer register addresses 30.0001, 30.0002, 30.0003 (or corresponding Buffer_ID) is filled in the cache memory 52; the buffer control device 20 is provided with a head pointer 50 and a tail pointer 51, respectively pointing to the unused serial buffer address 30.0004 With the last buffer register 30.2048, its buffer register management method includes:

If the switch controller is required to configure a segment (segment) with a length of 10 after initial initialization, preferably the cache memory 52 will release buffer register addresses 30.0001, 30.0002, and 30.0003 first. , and properly serialize it, and in order to form the aforementioned special series, the first and second released buffer register addresses 30.0001 and 30.0002 will be temporarily reserved in the exchange controller; the next seven The buffer register then goes to the buffer register address 30.0004 earlier by the head indicator 50, it is compiled into the buffer register address 30.0003, and according to the corresponding link node (link node) of the buffer register address 30.0004 ), update the head pointer 50 to point to 30.0005: then, according to the head pointer 50, go to the buffer temporary storage 30.0005, and update the head pointer 50 to point to 30.0005, after configuring one by one, the last configured buffer temporary storage The register address is 30.0010, and further, fill the previously held second released buffer register address 30.0002 into the corresponding connection node of the last configured buffer register; and, the configured last Address, according to the first released buffer register address 30.0001 previously held, fill in the last address 30.0010 in its corresponding connection node; then the released series, as shown in Figure 6, its first A freed buffer string points to the last buffer; and, the last freed buffer string points to the second buffer, and the rest are in the process of freeing Sequentially compile and link, so that all released partitions have the structure of the aforementioned special linked list (Linked list) of the present invention, so that these buffers can be temporarily buffered after the partitions are used (after the packet is successfully sent) Memory is returned more efficiently.

When releasing a partition with the aforementioned special link sequence of the present invention, preferably the buffer control device 20 will obtain the first address including the first buffer register, the second buffer register information such as the second address of the last buffer register, the last address of the last buffer register, and the segment length; please refer to FIG. The first address of the buffer register is stored in the cache memory 52, then, the second address is stored in the tail pointer device 51, and the last address is stored in the tail pointer device 51, so it can be quickly Release the used buffer back to the unused list (freelist) on the right without releasing it one by one; of course, if unfortunately, when checking the aforementioned Cache_full signal, it is found that the cache memory 52 is full, then In order to string the first buffer register back to the unused list (free list) on the right, one more stringing operation must be done, that is, fill the second address into the corresponding link of the first buffer register Among the nodes, follow the above-mentioned actions and return the entire list to the unused list (free list) on the right; among them, the content of the link node of the last buffer register can be ignored (don 't care), because the next use of the last buffer register will cover the content of its connection node; and the buffer control device 20 can prepare a counter to count the number of available buffer controllers remaining at present, so when the packet flow exceeds When all unused strings are exhausted, the temporarily stored data will not be overwritten.

It should be noted that the aforesaid release action can have many possible changes. For example, the first address of the first buffer register, the last address of the last buffer register, and segment segment length and other information without reporting the second address, it can store the first address in the cache memory 52, and obtain the second address from the link node of the last buffer register to store the tail pointer The link node of the buffer register pointed to by device 51, and then store the last address in the tail pointer device 51, wherein, the content of the link node of the last buffer register can be ignored, because the last buffer register is used next time will overwrite the content of its linked node.

Please refer to FIG. 5 , which shows that five buffer registers are directly configured by the header pointer 50 . Assuming that the original head pointer 50 points to the buffer register 30.0001, if the buffer control device 20 checks the Chche_empty signal and finds that the cache memory 52 has been configured, the first address 30.0001 is directly released by the head pointer 50, and then one by one by the head pointer The address pointed to by 50 takes out the serial buffer register, and finally the head pointer 50 points to 30.0006 at last. Similarly, the chaining operation of the buffer control device 20 directly points the connection node of the first buffer register to this fetching The last buffer address of the sequence is 30.0005, and the link node of the last buffer points back to the second buffer address 30.0002 of the fetched sequence.

If when the space is released, the buffer control device 20 checks the Cache_full signal and finds that the cache memory 52 is full, then the release action of the buffer management method includes: storing the first address into the tail pointer 51 to point to The link node of the first buffer register, and the second address is stored in the link node of the first buffer register, and the last address is stored in the tail pointer 51, so that the released partition segment is normally The list structure is compiled at the end of the unused list.

This preferred embodiment of the present invention not only saves memory space to record the second address, but also maintains the original hardware design structure so that the buffer memory can be used efficiently.

In yet another embodiment of the present invention, when the segment using the link structure of the present invention does not need to report the second address and the last address when releasing the action, only the first address of the used segment is reported. , and the buffer control device 20 can sequentially obtain the last address and the second address from the connection of the first buffer register of the first address, then the release action of the buffer control device 20 includes: temporarily storing the first address The last address obtained from the link node of the first buffer, and then the first address is stored in the cache memory; the second address is obtained from the link node of the last buffer of the last address to store the tail The pointer 51 points to the link node of the buffer register, and then stores the last address in the tail pointer 51 .

Please refer to FIG. 6 , which shows a schematic diagram of the link structure of the present invention. The link structure of the present invention points to a chain of circular links from the first buffer link node, and the series of circular links points to the last buffer link node sequentially from the second buffer link node, and then from the last The buffer link node points back to the second buffer link node, and the first buffer link node points to the last buffer link node. The link structure of the present invention is applied to the aforementioned packet switching controller to store packet data, so that when the buffer control device 20 cooperates with the cache memory to store the first address of the segment in use, it can obtain it from the last buffer register. The address of the second buffer register is known, and the buffer registers of the chain are returned to the end of the unused chain.

It should be noted that the previous embodiment is preferably provided with two indicators, the head and the tail, which can avoid the shortcoming of using the same indicator for the action and the release action in terms of hardware operation; The serial link structure can quickly obtain the first and last addresses; therefore, if the hardware is designed to have only one head pointer, when releasing the used serial link structure, it can be simultaneously Compile strings back to the front of unused strings, but performance will be slightly worse.

The link structure used in the present invention, for example, directs the link node of the first buffer register 30.0001 to the last buffer register 30.0010, and then the link node of the last buffer register 30.0010 points back After the second buffer register 30.0002, the second buffer register 30.0002 points to the last buffer register 30.0010 in sequence, so that the buffer control device releases the partition with the chained serial structure During the period, the second address 30.0002 is quickly obtained from the connection node of the last buffer register 30.0010, and the second buffer register and the last buffer register can be serially returned to the unused string, It is not necessary to release them one by one.

After describing the preferred embodiments of the present invention in detail, those skilled in the art can clearly understand that various changes and changes can be made without departing from the scope and spirit of the claims, and the present invention is not limited to the description The implementation of the example. While the present invention will be fully described with reference to the accompanying drawings of preferred embodiments, it should be understood that those skilled in the art may modify the invention described herein while still obtaining the benefits of the present invention. Therefore, it should be understood that the above description is a broad disclosure for those skilled in the art, and its content is not intended to limit the present invention.

Claims (13)

1, a kind of buffering control device, in order to manage a buffer memory, this buffer memory has one and does not use tandem, and the aforementioned tandem of not using comprises a plurality of buffer registers, and this buffering control device comprises:

A pointer is in order to point to aforementioned first buffer register that does not use tandem;

One tail pointer is in order to point to an aforementioned final buffer working storage that does not use tandem; And

One memory cache body, in order to get the address of a plurality of untapped buffer registers soon:

Wherein, when this buffering control device is required to configure the section of separating, be preferentially to configure a plurality of buffer registers for use by aforementioned memory cache body.

2, buffering control device as claimed in claim 1, it is characterized in that: if the buffer register of aforementioned preferential configuration is less than the size of this section of separating, this buffering control device takes out the buffer register that is pointed to by aforementioned pointer one by one, to form the aforementioned zones compartment together.

3, buffering control device as claimed in claim 1 is characterized in that: when the aforementioned section of separating in desiring to release back, preferentially releases being back to aforementioned memory cache body with finishing.

4, buffering control device as claimed in claim 3 is characterized in that: the tandem that this buffering control device is used the aforementioned zones compartment of desiring to release back formed, directly go here and there back that this does not use the end of tandem.

5, buffering control device as claimed in claim 1 is characterized in that: when the aforementioned section of separating with finishing and in desiring to release back, aforementioned buffering control device is with first buffer register of aforementioned memory cache body sensing aforementioned zones compartment; The buffer register that aforementioned buffering control device points to aforementioned tail pointer again points to second buffer register of aforementioned zones compartment; Aforementioned buffering control device points to this tail pointer the final buffer working storage of aforementioned zones compartment again, so that the aforementioned zones compartment is gone here and there the least significant end that does not use tandem in aforementioned together.

6, a kind of buffering control device, in order to manage a buffer memory, this buffer memory has one and does not use tandem, and the aforementioned tandem of not using comprises a plurality of buffer registers, and this buffering control device comprises:

A pointer, this pointer is pointed to aforementioned first buffer register that does not use tandem;

Wherein, when this buffering control device is required to configure one when having the section of separating of a plurality of buffer registers, one first buffer register of aforementioned zones compartment is compiled the final buffer working storage that string points to the aforementioned zones compartment.

7, a kind of buffering control device, in order to manage a buffer memory, this buffer memory has one and does not use tandem (free list), and the aforementioned tandem of not using comprises a plurality of buffer registers, and this buffering control device comprises:

A pointer is in order to point to aforementioned first buffer register that does not use tandem; And

One tail pointer is in order to point to an aforementioned final buffer working storage that does not use tandem; Wherein, when this buffering control device desire one tandem that is used (used linked list) being released back this does not use in the tandem, this buffering control device does not use this tandem directly compile to go here and there back that this does not use the end of tandem, and this tail pointer is pointed to the end of this tandem of releasing go back to that is used.

8, buffering control device as claimed in claim 7, it is characterized in that: this tandem that is used comprises a plurality of buffer registers, and the final buffer working storage that string points to this tandem that is used is compiled by one first buffer register of the tandem that this is used system, and one second buffer register that string points to this tandem that is used is compiled by the final buffer working storage of this tandem that is used system.

9, buffering control device as claimed in claim 7 is characterized in that: this buffering control device more comprises a memory cache body, in order to get a plurality of address that do not use the buffer register of (unused) soon.

10, buffering control device as claimed in claim 7 is characterized in that: when this buffering control device is required to configure the section of separating, be preferentially to configure a plurality of buffer registers for use by aforementioned memory cache body.

11, a kind of buffer register management method, in order to manage a buffer memory, this buffer memory has one and does not use tandem, and this does not use tandem to comprise a plurality of buffer registers, and this buffer register management method comprises the following step at least:

Requirement does not use tandem configuration one to have the tandem that is used of a plurality of buffer registers from aforementioned;

One first buffer register of this tandem that is used is compiled the final buffer working storage that string points to this tandem that is used;

This final buffer working storage of this tandem that is used is compiled one second buffer register that string points to this tandem that is used; And

Compile the final buffer working storage of string sensing in regular turn from second buffer register of this tandem that is used until this tandem that is used.

12, buffer register management method as claimed in claim 11, it is characterized in that further comprising: give aforementionedly when not using tandem releasing back the tandem that is used, need repay the last address of one first address and the final buffer working storage of the tandem that is used of first buffer register of the tandem that is used at least.

13, buffer register management method as claimed in claim 12 is characterized in that more comprising the following step:

Deposit aforementioned first address in one and get the unit soon: and

Obtain one second buffer register of the tandem that is used via the final buffer working storage of the tandem that is used, be connected to the aforementioned least significant end that does not use tandem to compile polyphone.

Images