CN1371131A - The Structure of Double-Bit Non-Volatile Storage Unit and Its Reading and Writing Method - Google Patents

Abstract

A double-bit non-volatile memory unit structure and its read-write method, the memory unit includes two stacked grid structures, a doped region between the two stacked grid structures, and two source/drain regions outside the two stacked grid structures, the doping type of the source/drain regions is the same as the doped region. During writing, the channel below the two stacked gate structures is opened at the same time, and the floating gate to be written is selected in the direction of channel current. When reading data, applying reading bias voltage and transfer bias voltage on the first and second control gates above the first floating gate, and determining whether data is written by whether the two source/drain regions are conducted or not, wherein the reading bias voltage is greater than the channel starting voltage in the erasing state and less than the starting voltage in the writing state, and the transfer bias voltage is greater than the starting voltage in the writing state.

Description

The structure of double-bit non-volatile storage unit and its reading and writing method

The present invention relates to a semiconductor device (Semiconductor Device) structure and its operating method, and in particular to a double-bit non-volatile memory unit (Double-Bit Non-VolatileMemory (NVM) Unit) structure and its reading and writing method.

Non-volatile memory (NVM) is a permanent storage medium with fast access speed, small size, power saving and vibration resistance, so it is widely used. The most important type of non-volatile memory is flash memory (Flash Memory), which is characterized by erasing data block by block, which can save the time required for erasing operations.

Please refer to Figure 1 for the structure of a traditional non-volatile storage unit (Memory Cell). As shown in FIG. 1 , there is a stacked gate structure 110 on the substrate 100 , and there are source/drain regions 120 in the substrate 100 on both sides thereof. The stacked gate structure 110 includes a tunnel oxide layer (Tunnel Oxide) 112, a floating gate (Floating Gate) 114, an inter-gate dielectric layer 116 and a control gate (Control Gate) 118 stacked from bottom to top. When programming this memory cell, electrons are injected into the floating gate 114 , and when erasing, a high negative bias is applied to the control gate 118 to exclude electrons from the floating gate 114 .

However, in order to ensure that the electrons are completely erased from the floating gate 114, the above-mentioned conventional non-volatile memory cells are prone to the problem of over-erase, that is, the electrons are excluded from the floating gate 114. There are too many electrons, so that the floating gate 114 is positively charged. When the amount of positive charges is too large, the channel area under the floating gate 114 will be reversed, and the channel will be continuously opened, thereby causing misjudgment when reading data.

For this reason, the solution in the prior art is to form a split-gate structure (Split-Gate Structure) as shown in FIG. 2 . As shown in FIG. 2 , there is a split gate structure 210 on the substrate 200 , and there are source/drain regions 220 in the substrate 200 on both sides thereof. The split gate structure 210 includes a tunnel oxide layer 212, a floating gate 214, an inter-gate dielectric layer 216, a control gate 218 stacked from bottom to top, and the side extending from the control gate 218 to the floating gate 214. The transfer gate (Transfer Gate) 218a, wherein the transfer gate 218a is also separated from the floating gate 214 and the substrate 200 by an inter-gate dielectric layer 216. In this design, because the channel under the transfer gate 218a can only be opened when a voltage is applied to the control gate 218/transfer gate 218a, even if the channel under the floating gate 214 is continuously opened due to excessive erasing, The two source/drain regions 220 of the memory cell can still maintain a non-conductive state, thereby preventing misjudgment when reading data.

However, although the split gate structure 210 can prevent the misjudgment problem caused by excessive erasing, it is not conducive to the miniaturization of the device because the transfer gate 218a needs to occupy an extra area. In addition, as shown in FIG. 2, since the combined width of the control gate 218 and the transfer gate 218a in the split gate structure 210 is different from that of the floating gate 214, the floating gate 214 and the control gate 218/transfer The gate 218a must be defined by two photolithographic etching processes respectively. Therefore, there will be an alignment problem between the floating gate 214 and the control gate 218/transfer gate 218a, so that the width of the transfer gate 218a and the relationship between the control gate 218/transfer gate 218a and the floating Errors are likely to occur in the overlapping areas of the gates 214, making the electrical properties of each memory cell inconsistent and increasing the difficulty of operating the memory.

The object of the present invention is to propose a dual-bit non-volatile memory cell structure, which can be used to prevent problems caused by over-erasing.

Another object of the present invention is to provide a programming method and a reading method for a double-bit non-volatile memory cell, so as to avoid writing or reading errors.

To achieve the above object, the present invention provides a double-bit non-volatile memory cell structure, which includes a substrate, two stacked gate structures, a doped region, and two source/drain regions. Wherein, each stacked gate structure includes a tunnel layer, a floating gate, an inter-gate dielectric layer and a control gate stacked from bottom to top; the doping region is located in the substrate between the two stacked gate structures ; The source/drain region is located in the substrate outside the two stacked gate structures, and the doping type of the two source/drain regions is the same as that of the aforementioned doped region.

The invention also proposes a programming method for a double-bit non-volatile storage unit, which is applied to the above-mentioned double-bit non-volatile storage unit of the present invention. In this method, when the first floating gate of the first stacked gate structure is to be written, a bias voltage is simultaneously applied to the first and second control gates of the first and second stacked gate structures to turn on Channels under the first and second floating gates; and applying different bias voltages on the two source/drain regions, so that electrons flow from the channel under the second floating gate to the channel under the first floating gate , and obtain enough energy here to generate hot electrons and enter into the first floating gate.

The present invention further proposes a programming method for a double-bit non-volatile memory cell, which is applied to the above-mentioned double-bit non-volatile memory cell of the present invention. In this method, when writing to the first floating gate in the first stacked gate structure, a higher bias voltage is applied to the first control gate of the first stacked gate structure, and the first stacked gate structure A lower bias voltage is applied to the source/drain region on one side of the gate structure, so that electrons enter the first floating gate through the source/drain region.

The present invention also proposes a method for reading a double-bit non-volatile memory cell, which is applied to the above-mentioned double-bit non-volatile memory cell of the present invention. When any stacked gate structure in this memory cell is in an erased state The starting voltage of the channel below it (the bias voltage required to be applied to the control gate of the stacked gate structure when the channel is turned on) is the first starting voltage, and it is higher than the first starting voltage in the writing state. the second starting voltage. In this reading method, if the data stored in the first floating gate of the first stacked gate structure is to be read, a read bias voltage is applied to the first control gate of the first stacked gate structure. The read bias is higher than the first start voltage and lower than the second start voltage; at the same time, a transfer bias is applied to the second control gate of the second stacked gate structure, and the transfer bias is higher than the second start voltage voltage, which necessarily opens the channel under the second floating gate. Then judge whether the first floating gate is in the writing state according to whether the two source/drain regions are conducting or not: when the two source/drain regions are conducting, it means that the first floating gate is not written, Otherwise, it means that it has been written.

As mentioned above, since the non-volatile memory of the present invention shares a pair of source/drain regions in units of two stacked gate structures, only when the channels under the first and second floating gates are simultaneously opened, There is conduction between the two source/drain regions. Since the probability of over-erasing the two floating gates at the same time is extremely low, the probability of continuous conduction between the two source/drain regions is also very low, thereby greatly reducing the chance of data misjudgment. At this time, please refer to the description of the aforementioned split gate structure and FIG. 2. Since one stacked gate structure in the memory cell of the present invention can prevent the misjudgment problem caused when the other stacked gate structure is over-erased, the stacked gate structure also It can be called a transfer gate, and its function is similar to the transfer gate 218a in FIG. 2 .

In addition, since two bits can be stored in the double-bit memory cell of the present invention, one stacked gate structure is used as the transfer gate of the other stacked gate structure instead of the existing unit cell separation gate designer. The transfer gate is added on the side of the control gate, so the area required to store each bit (Bit) can be reduced. Furthermore, the present invention uses one stacked gate structure as the transfer gate of another stacked gate structure, instead of first defining the floating gate as in the existing split gate structure, and then defining the control gate and the transfer gate at the same time. Therefore, the floating gate and the control gate of the present invention can be formed in a self-aligned manner without causing the problem of electrical inconsistency of the components.

In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, preferred embodiments are specifically cited below and described in detail with accompanying drawings. In the attached picture:

Figure 1 shows a non-volatile memory cell in a conventional stacked gate design;

FIG. 2 shows a non-volatile memory cell with a conventional split-gate design;

FIG. 3 shows the structure of a double-bit non-volatile memory unit in a preferred embodiment of the present invention;

FIG. 4 shows the first programming method of the double-bit non-volatile memory cell according to the preferred embodiment of the present invention;

FIG. 5 shows the second programming method of the double-bit non-volatile memory cell according to the preferred embodiment of the present invention; and

FIG. 6 illustrates a reading method of a dual-bit non-volatile memory cell according to a preferred embodiment of the present invention.

Explanation of reference numbers:

100, 200, 300: Base

110, 310a, 310b: Stacked Gate Structure

112, 212, 312a, 312b: Tunnel Oxide

114, 214, 314a, 314b: floating gate (Floating Gate)

116, 216, 316a, 316b: inter-gate dielectric layer

118, 218, 318a, 318b: Control Gate

120, 220, 320a, 320b: source/drain region (S/D Region)

210: Split-Gate Structure

218a: Transfer Gate

333: doped area

a, b: width label

Description of preferred embodiments

The structure of the double-bit non-volatile memory cell of the preferred embodiment of the present invention, two programming methods, and its reading method will be described in turn below, and this kind of double-bit non-volatile memory cell can be used in a flash memory, for example. In the memory (Flash Memory). Structure of a dual-bit non-volatile memory cell

Please refer to FIG. 3 , which shows the structure of a dual-bit non-volatile memory unit according to a preferred embodiment of the present invention. As shown in FIG. 3 , the memory cell includes a substrate 300 , two stacked gate structures 310 a and 310 b , source/drain regions 320 a and 320 b , and a doped region 333 . Wherein, the stacked gate structure 310a/b includes tunnel oxide layer 312a/b, floating gate 314a/b, inter-gate dielectric layer 316a/b and control gate 318a/b stacked from bottom to top; doped region 333 Located in the substrate 300 between the stacked gate structures 310a and 310b; the source/drain regions 320a/b are located in the substrate 300 outside the stacked gate structures 310a/b, and the doping type of the source/drain regions 320a/b The state is the same as that of the doped region 333, for example, both are n-type. In addition, the material of the floating gate 314a/b and the control gate 318a/b is, for example, polysilicon, and the inter-gate dielectric layer 316a/b is, for example, a silicon monoxide/silicon nitride/silicon oxide (ONO) composite layer.

In addition, in the above structure, the doped region 333 is only used to connect the two channels under the tunnel oxide layers 312a and 312b, so the width a of the doped region 333 can be smaller than the width b of the source/drain region 320a/b to save this The area of a two-bit non-volatile memory cell. Of course, the width of the doped region 333 can also be equal to the width of the source/drain region 320a/b, depending on the requirement. programming method

Next, when the doping type of the source/drain region 320a/b and the doped region 333 is n-type, two methods for programming the above-mentioned double-bit non-volatile memory cell according to the preferred embodiment of the present invention will be explained. method, which are explained with Fig. 4 and Fig. 5 respectively.

Please refer to the programming method shown in FIG. 4 , which is a Channel Hot Electron (CHE) injection method. The method is to apply bias voltages V ₁ and V ₂ greater than 0 on the control gates 318 a and 318 b respectively, so as to simultaneously open the channels in the substrate 300 below the floating gates 314 a and 314 b. If the object to be written is the floating gate 314b, a bias voltage V ₃ is applied to the source/drain region 320a on the side of the control gate 318a, which is, for example, the ground voltage (Ground Voltage); A bias voltage V ₄ greater than V ₃ is applied to the source/drain region 320b on the side of 318b, so that electrons flow from the source/drain region 320a to the source/drain region 320b, as shown by the arrow in FIG. 4 . Here, the difference between _V4 and _V3 is large enough, so that electrons can get enough energy to generate hot electrons when they travel below the floating gate 314b, and inject them into the floating gate 314b; but it can't be too large to avoid heat Electrons are generated below the floating gate 314a.

By analogy, if you want to write to the floating gate 314a, you only need to reverse the polarity of the two source/drain regions 320a and 320b under the condition that the channels below the floating gates 314a and 314b are simultaneously open, and then the Hot electrons are only channeled under the floating gate 314a and injected into the floating gate 314a. In addition, it can be seen from the above-mentioned writing method that as long as the bias voltage on the floating gate 314b is sufficient to open the channel under the floating gate 314b, no matter whether the floating gate 314b has been written or not, it will have a negative impact on the floating gate 314a. The write operation has no effect. That is to say, the writing operation of the floating gate 314a can be performed after writing the floating gate 314b.

Please refer to the second programming method shown in FIG. 5 , which takes the writing process of the floating gate 314 b as an example. As shown in FIG. 5 , the method is to apply a bias voltage _V5 greater than 0 on the control gate 318b, and apply a bias voltage _V6 lower than _V5 to the source/drain region 320b on one side of the control gate 318b. , which is, for example, the ground voltage. Here, the difference between V ₅ and V ₆ is large enough so that electrons can flow from the source/drain region 320b to the floating gate 314b by FN tunneling effect (Fowler-Norheim Tunneling Effect).

By analogy, if the person who wants to write is the floating gate 314a, as long as the bias voltage of the control gate 318a is higher than the bias voltage of the source/drain region 320a on the same side, and the difference between the two bias voltages is sufficient Big enough. In addition, it can be seen from the above-mentioned writing method that since the writing operation of the floating gate 314a has nothing to do with the floating gate 314b and the control gate 318b, no matter whether the floating gate 314b has been written or not, the floating gate The write operation of 314a has no effect. That is to say, the writing operation of the floating gate 314a can be performed after writing the floating gate 314b. read method

Next, when the doping type of the source/drain region 320a/b and the doped region 333 is n-type, the method for reading the above-mentioned dual-bit non-volatile memory cell according to the preferred embodiment of the present invention will be described. As known to those skilled in the art, due to the presence of negative charges, the initial voltage of the channel below the floating gate 314a (314b) in the writing state (that is, the required voltage on the control gate 318a (318b) when the channel is turned on) Applied bias voltage) is greater than the initial voltage in the erasing state, here the initial voltage in the writing state is abbreviated as V _Twirte , and the initial voltage in the erasing state is abbreviated as V _Terase , and V _Twirte > V _Terase .

Please refer to FIG. 6 , which illustrates a reading method of a dual-bit non-volatile memory cell according to a preferred embodiment of the present invention. Here, the reading process of data in the floating gate 314 a is taken as an example. As shown in FIG. 6, this process is to apply a positive bias voltage _V8 greater than V _Twirte on the control gate 318b to determine to open the channel in the substrate 300 below the floating gate 314b; The positive bias voltage V ₇ has a magnitude relationship with V _Twirte and V _Terase as V _Twirte >V ₇ >V _Terase . Next, apply different bias voltages V ₉ and V ₁₀ on the source/drain regions 320a and 320b, and judge whether the floating gate 314a is conducting or not by whether the two source/drain regions 320a and 320b are conducting or not. There is data. Please refer to the next paragraph for the phenomenon that occurs at this time and the method of data interpretation.

As shown in FIG. 6, since the voltage V ₈ >V _Twirte >V _Terase of the control gate 318b at this time, no matter whether there is data written in the floating gate 314b, the channel in the substrate 300 below it will be opened; another On the one hand, since the magnitude relationship of the voltage V ₇ of the control gate 318a is V _Twirte > V ₇ >V _Terase , so when the floating gate 314a is in the erasing state, the channel below it will be opened, but in the writing state it will not. . Since the doping type of the doped region 333 is the same as that of the source/drain region 320a/b, when the conduction between the two source/drain regions 320a and 320b is possible, it means that the floating gate 314a is in the erasing state. When the two source/drain regions 320a and 320b cannot be conducted, it means that the floating gate 314a is in the write state.

By analogy, if the data stored in the floating gate 314b is to be read, the bias voltage V ₇ of the control gate 318a >V _Twirte must be set, and the bias voltage V ₈ of the control gate 318b must be greater than V _Terase and If it is less than V _Twirte , whether the floating gate 314b is written is judged by whether the two source/drain regions 320a and 320b are turned on or not.

As mentioned above, in the dual-bit non-volatile memory cell of the preferred embodiment of the present invention, two stacked gate structures 310a and 310b share a pair of source/drain regions 320a and 320b, so the floating gate 314a and The channel below 314b must be opened at the same time, so that the two source/drain regions 320a and 320b can conduct. Since the probability of over-erasing of the two floating gates 314a and 314b at the same time is extremely low, the probability of continuous conduction between the two source/drain regions 320a and 320b is also extremely low, so it is different from the existing single stacked gate structure. 110 (Fig. 1) designers, by comparison, their chances of data misjudgment can be greatly reduced. At this time, please refer to the description of the aforementioned split gate structure and FIG. 2, since the stacked gate structure 310a (310b) in the memory cell of the present invention can prevent the misjudgment problem caused when the stacked gate structure 310b (310a) is excessively erased, Therefore, the stacked gate structure 310 a ( 310 b ) can be called a transfer gate, and its function is similar to that of the transfer gate 218 a in FIG. 2 .

In addition, since the double-bit memory cell of the present invention can store two bits, the stacked gate structure 310a (310b) is used as the transfer gate of the stacked gate structure 310b (310a), instead of the existing unit cell separation gate The designer generally adds the transfer gate 218a (FIG. 2) on the side of the control gate 218, so compared with the designer of the split gate structure 210, the area required to store each bit can be greatly reduced when using the present invention .

Moreover, as shown in FIG. 3, the present invention uses a stacked gate structure 310a (or b) in the same memory cell as the transfer gate of another floating gate 310b (or a), wherein the stacked gate structure 310a/ The formation of b requires only one photolithography process, instead of two photolithography processes to define the floating gate 214 and the control gate 218/transfer gate 218a ( FIG. 2 ) as in the existing split gate structure process. Therefore, the present invention is a self-alignment process without the problem of electrical inconsistency of components.

In addition, please refer to FIG. 3, since the doped region 333 in the double-bit non-volatile memory cell of the present invention is only used as a path for current, so it only needs to have the same doping as the source/drain region 320a/b The width a can be smaller than the width b of the source/drain region 320a/b. Therefore, the area required for storing each bit of the double-bit non-volatile memory cell of the present invention can not only be smaller than the designer of the unit cell separation gate shown in FIG. 2, but also smaller than the existing unit cell shown in FIG. 1 Stacked Gate Designer.

Although the present invention has been disclosed above in conjunction with a preferred embodiment, it is not intended to limit the present invention. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection should be defined by the appended claims.

Claims (16)

1. A structure of a double-bit non-volatile storage unit, comprising: a base; Two stacked gate structures on the substrate, wherein each stacked gate structure includes a tunnel layer, a floating gate, an inter-gate dielectric layer and a control gate stacked from bottom to top; a doped region in the substrate between the two stacked gate structures; and Two source/drain regions, the two source/drain regions are respectively located in the substrate outside the two stacked structures, and the doping type of the two source/drain regions is the same as the doping region. 2. The structure of claim 1, the dual-bit non-volatile memory cell is applied in a flash memory. 3. The structure of claim 1, wherein the tunnel layer is a tunnel oxide layer. 4. The structure as claimed in claim 1, wherein the material of the floating gate comprises polysilicon. 5. The structure of claim 1, wherein the inter-gate dielectric layer comprises a silicon monoxide/silicon nitride/silicon oxide composite layer. 6. The structure of claim 1, wherein a material of the control gate comprises polysilicon. 7. The structure of claim 1, wherein a width of the doped region is smaller than a width of one of the source/drain regions. 8. The structure of claim 1, wherein the doped region has the same width as one of the source/drain regions. 9. The structure of claim 1, wherein the doping type of the doped region and the two source/drain regions comprises n-type. 10. A programming method for a double-bit non-volatile memory cell, wherein the structure of the double-bit non-volatile memory cell comprises: a base; A first stacked gate structure and a second stacked gate structure on the substrate, wherein the first stacked gate structure includes a first floating gate and a first control gate, and the second stacked gate structure includes a second floating gate and a second control gate; a doped region in the substrate between the first stacked gate structure and the second stacked gate structure; and Two source/drain regions are respectively located in the substrate outside the two stacked gate structures, and the doping types of the two source/drain regions and the doped region are both n-type; and When the first floating gate is to be written, the programming method includes the following steps: Applying a first voltage to the first control gate and applying a second voltage to the second control gate to open channels under the first floating gate and the second floating gate ;as well as Different bias voltages are applied to the two source/drain regions, so that electrons flow from the channel under the second floating gate to the channel under the first floating gate, and electrons flow in the channel under the first floating gate. Enough energy is obtained in the channel to generate hot electrons, which enter into the first floating gate. 11. The programming method according to claim 10, wherein after writing the first floating gate, further comprising the following steps: Applying a third voltage on the first control gate and applying a fourth voltage on the second control gate to open the channels under the first floating gate and the second floating gate ;as well as Different bias voltages are applied to the two source/drain regions, so that electrons flow from the channel under the first floating gate to the channel under the second floating gate, and electrons flow in the channel under the second floating gate. Enough energy is obtained in the channel to generate hot electrons, which enter into the second floating gate. 12. The programming method as claimed in claim 10, wherein the bias voltage applied to the source/drain region on one side of the second stacked gate structure is a ground voltage. 13. A programming method for a double-bit non-volatile memory cell, wherein The structure of the dual-bit non-volatile memory cell includes: a base; A first stacked gate structure and a second stacked gate structure on the substrate, wherein the first stacked gate structure includes a first floating gate and a first control gate, and the second stacked gate structure includes a second floating gate and a second control gate; a doped region in the substrate between the two stacked gate structures; and Two source/drain regions are located in the substrate outside the two stacked gate structures, and the doping types of the two source/drain regions and the doped region are both n-type; and In the programming method, when the first floating gate is to be written, a higher bias voltage is applied to the first control gate, and the source/drain on the side of the first stacked gate structure A lower bias voltage is applied to the region, so that electrons tunnel into the first floating gate from the source/drain region on one side of the first stacked gate structure. 14. The programming method according to claim 13, further comprising the following steps after writing the first floating gate: applying a higher bias voltage on the second control gate; Applying a lower bias voltage on the source/drain region on one side of the second stacked gate structure, so that electrons tunnel into the second floating gate from the source/drain region on the side of the second stacked gate structure extreme. 15. The programming method as claimed in claim 13, wherein the bias voltage applied to the source/drain region on one side of the first stacked gate structure is a ground voltage. 16. A method for reading a double-bit non-volatile storage unit, wherein The structure of the dual-bit non-volatile memory cell includes: a base; A first stacked gate structure and a second stacked gate structure on the substrate, wherein the first stacked gate structure includes a first floating gate and a first control gate, and the second stacked gate structure includes A second floating gate and a second control gate, wherein when the first/second floating gate is in the erasing state, the starting voltage of the channel below the first/second floating gate is one a first starting voltage, and in the writing state, the starting voltage of the channel below the first/second floating gate is a second starting voltage greater than the first starting voltage; a doped region in the substrate between the two stacked gate structures; and Two source/drain regions are located in the substrate outside the two stacked gate structures, and the doping types of the two source/drain regions and the doped region are both n-type; and When the data stored in the first floating gate is to be read, the reading method includes the following steps: Applying a read bias voltage on the first control gate, the read bias voltage is greater than the first start voltage and less than the second start voltage; Applying a transfer bias voltage on the second control gate, the transfer bias voltage is greater than the second start voltage, and the channel under the second floating gate must be opened; and Judging whether the first floating gate is in the writing state by whether the two source/drain regions are conducting or not, wherein when the two source/drain regions are conducting, it means that the first floating gate Extremely unwritten, otherwise it means written.

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