CN1357890A - Structure and operation method of dynamic random access memory - Google Patents

Abstract

A dynamic random access memory structure and an operation method thereof suitable for a static random access memory compatible transistor. The static random access memory structure using a single transistor can effectively save the data stored in the dynamic random access memory storage unit without losing it. The structure can operate under low voltage conditions, still maintain the data stored in the dynamic random access memory storage unit, and reduce the power consumed by the operation of the entire dynamic random access memory structure. The structure can still maintain the data stored in the dynamic random access memory storage unit in standby mode or sleep mode, and reduce the power consumed by the entire operation.

Description

Dynamic random access memory structure and operation method

The present invention relates to a dynamic random access memory (Dynamic Random Access Memory, hereinafter referred to as DRAM) structure and its operation method, in particular to a storage unit suitable for static random access memory (Static Random Access Memory, hereinafter referred to as SRAM) Dynamic Random Access Memory (Dynamic Random Access Memory, hereinafter referred to as DRAM) structure and its operation method, and this dynamic random access memory is regarded as a transistor compatible with static random access memory, that is, static random access memory with a single transistor memory.

A traditional DRAM memory unit (Cell) includes a transistor and a capacitor, and its area and manufacturing cost are far smaller than those of an SRAM. Because of the traditional SRAM structure, with 4 to 6 transistors. Therefore, using DRAM memory cells with lower cost as SRAMs has always been the direction of the industry's efforts.

However, if the data is stored in the storage unit of the DRAM, it must be refreshed periodically, but the data stored in the SRAM does not need to be refreshed regularly. The refresh operation in the DRAM storage unit will waste the bandwidth of the memory (Bandwidth). For example, a DRAM operating at one hundred million frequencies (100 MHz) has a time per clock of 10 nanoseconds (nsec). Under such a DRAM structure, the time for each external access to data is 10 nanoseconds, and the time for each re-update is also 10 nanoseconds. Of course, this depends on the designed circuit and memory size. It may also be from 16 to 500 ns. Because the access time and re-update time may be at the same time, this DRAM may have to stop waiting (Idle) once every 500 nanoseconds in order to perform re-update actions, so its performance may be lower Reduced to 50-90%. Because of this consideration, the bandwidth of the entire operation will be reduced.

In the known technology, once tried to use the DRAM storage unit in the SRAM application structure, but can not effectively achieve the feature of SRAM with long-term data storage, because such a DRAM storage unit needs an external signal to control the update operation, and Such an SRAM structure will be delayed due to the update operation. As a result, such DRAM memory cells are not fully compatible with SRAM structures.

In addition, it has been proposed that a high-speed SRAM cache (Cache) be used together with a relatively low-speed DRAM to speed up the average access time of the memory (US Patent No. 5,559,750). The real access time of such a structure must take into account the SRAM cache hit rate (Hit Rate). And additionally there is a circuit to provide refresh operation of the DRAM memory cell. However, such a structure still affects external access operations and cannot meet the overall random access time.

Another structure is to use a DRAM with many rows of memory cells to reduce the access time of the DRAM, but this structure cannot allow the delay of updating time of one row of memory cells.

In addition, in US Pat. No. 6,028,804, a device using DRAM memory cells in an SRAM structure is proposed. However, its structure is to use an access arbiter (Access Arbiter) to arbitrate the external access request clock and the internally generated update clock, and give priority to the operation of the external access clock to avoid conflicts. However, under this structure, part of the operating frequency must be lost.

In view of this, the purpose of the present invention is to provide a SRAM structure using DRAM storage unit and its operation method, which can effectively save the data stored in the DRAM storage unit without affecting the normal operation of the SRAM.

Another object of the present invention is to provide a SRAM structure using a DRAM memory unit and its operation method, especially when the SRAM has a low-voltage operation, the data stored in the DRAM memory unit can still be maintained, and the entire SRAM structure can be reduced. The power consumed by the operation.

Yet another object of the present invention is to provide a SRAM structure using a DRAM storage unit and its operation method, especially the SRAM can still be maintained in the standby (Stand-by) mode or in the sleep mode (Sleep Mode). The data stored in the DRAM storage unit can reduce the power consumed by the operation of the entire SRAM structure.

To achieve the above object, the present invention provides a DRAM structure suitable for SRAM compatible transistors, wherein the DRAM structure is operated in a normal operation mode and a low voltage operation mode . The DRAM structure uses a reference clock signal as the basis for operation. The above dynamic random access memory structure includes a storage unit for storing data; a detection and amplification device has a detection unit, a first transistor and a second transistor, wherein the detection unit is connected to the first transistor and the first transistor. Two transistors, a bit line and a complementary bit line are connected, wherein the bit line and the complementary bit line are used for reading and updating the data stored in the memory unit, and the frequency of updating the data stored in the memory unit is based on the reference clock signal; and a switching device for receiving a first voltage and a second voltage, and for switching one of the two outputs to be an operating voltage, wherein the level of the first voltage is higher than that of the second voltage Two voltage levels. When the dynamic random access memory structure is in the normal operation mode, the operating voltage is the second voltage to supply the dynamic random access memory structure for operation, so as to save operating power consumption, when the dynamic random access memory structure When operating in the low-voltage operation mode, the operating voltage is the first voltage for supplying the DRAM structure to maintain the data stored in the storage unit of the DRAM.

The above-mentioned dynamic random access memory structure, wherein the storage unit is composed of a third transistor and a capacitor, wherein one end of the capacitor is connected to a source/drain end of the third transistor, and the other end of the capacitor is connected to a third Voltage. The other source/drain terminal of the third transistor is connected to the bit line, and one gate terminal thereof is connected to the word line, wherein when the dynamic random access memory structure is in the normal operation mode, the third voltage is a ratio of the operating voltage, but The third voltage is lower than the operating voltage. When the DRAM structure is in the low-voltage operation mode, the third voltage is reduced to zero voltage according to the reference clock signal when the reference clock signal is at a low level of logic 0, so as to reduce maintenance The voltage value required by the data stored in the memory cell of the DRAM.

In the aforementioned DRAM structure, a substrate of the third transistor is connected to a substrate bias, and the substrate bias is provided with reference to a reference clock signal.

The above-mentioned DRAM structure further includes a voltage drop device connected to the switching device and the first voltage, and outputs the second voltage to the switching device.

To achieve the above object, the present invention provides a DRAM structure suitable for SRAM compatible transistors, wherein the DRAM structure is in a normal operation mode, a standby mode and a sleep mode operate in one of the modes. The DRAM structure uses a reference clock signal as the basis for operation. The dynamic random access memory structure includes a storage unit for storing data; a detection and amplification device has a detection device, a first transistor and a second transistor, wherein the detection unit is connected to the first transistor, the second transistor, A bit line is connected to a complementary bit line, wherein the bit line and the complementary bit line are used for reading and updating the data stored in the memory unit, and the frequency of updating the data stored in the memory unit is based on the reference clock signal; and a The switching device is used to receive a first voltage and a second voltage, and to switch one of the two outputs to be an operating voltage, wherein the level of the first voltage is higher than the level of the second voltage, wherein when the dynamic When the random access memory structure is in the normal operation mode, the operating voltage is the above-mentioned second voltage to supply the operation of the dynamic random access memory structure to save the power consumption of the operation. When the dynamic random access memory structure is operating in the standby mode , the operating voltage will be adjusted to the first voltage or the second voltage according to the reference clock signal; when the DRAM structure is operating in sleep mode, the operating voltage will be fixed at the above-mentioned first voltage to supply the DRAM The structural operation is used to maintain the above-mentioned data stored in the storage unit of the DRAM.

The above-mentioned dynamic random access memory structure, wherein the storage unit is composed of a third transistor and a capacitor, wherein one end of the capacitor is connected to a source/drain end of the third transistor, and the other end of the capacitor is connected to a third The other source/drain terminal of the third transistor is connected to the above-mentioned bit line, and one gate terminal of the third transistor is connected to the word line, wherein when the dynamic random access memory structure is in the normal operation mode, the third voltage is the operating voltage A ratio, but the third voltage is less than the above-mentioned operating voltage. When the DRAM structure is operating in sleep mode, the third voltage drops to zero according to the reference clock signal when the reference clock signal is at a low level of logic 0. voltage to reduce the voltage value required to maintain the data stored in the memory cells of the DRAM.

In the aforementioned DRAM structure, a substrate of the transistor is connected to a substrate bias, and the substrate bias is provided with reference to a reference clock signal.

In order to achieve the above-mentioned purpose, the present invention provides a method for operating a DRAM structure suitable for SRAM compatible transistors, wherein the above-mentioned DRAM structure includes a storage unit, a detection amplifier and A switching device, the DRAM structure operates in a normal operation mode and a low voltage operation mode. This operation method includes the following steps: providing a first voltage and a second voltage, and switching one of the two outputs to be an operation voltage of the above operation method, wherein the above first voltage is higher than the above second voltage; providing a reference The clock signal is the operation signal of the above-mentioned operation method; store a data in the above-mentioned storage unit; update the data stored in the above-mentioned storage unit according to the timing frequency of the above-mentioned reference clock signal; in the above-mentioned normal operation mode, provide the above-mentioned second voltage for the above-mentioned operation The voltage is used to supply the operation of the above-mentioned dynamic random access memory structure, and the power consumption of the operation is saved. When operating in the above-mentioned low-voltage operation mode, the above-mentioned first voltage is provided as the above-mentioned operating voltage to supply the operation of the above-mentioned dynamic random access memory structure. , to maintain the data stored in the storage unit of the DRAM.

The above operation method, wherein the storage unit is composed of a third transistor and a capacitor, wherein one end of the capacitor is connected to a source/drain terminal of the third transistor, and the other end of the capacitor is connected to a third voltage, and the third The other source/drain terminal of the transistor is connected to the bit line, and one gate terminal of the transistor is connected to the above-mentioned word line, wherein when in the normal operation mode, the above-mentioned third voltage is a ratio of the operating voltage, but the third voltage is smaller than the above-mentioned operation voltage Voltage, when in the low-voltage operation mode, the above-mentioned third voltage is reduced to zero voltage according to the above-mentioned reference clock signal when the reference clock signal is at a low level of logic 0, so as to reduce the maintenance of the above-mentioned storage unit of the dynamic random access memory The voltage value required for the stored data.

The above-mentioned operation method of the DRAM structure applicable to the static random access memory compatible transistor, wherein the DRAM structure includes a storage unit, a detection amplification device and a switching device, and the DRAM structure Operates in a normal operation mode, a standby mode and a sleep mode, wherein the above operation method includes the following steps of providing a first voltage and a second voltage, and switching one of the two outputs to be an operating voltage of the above operation method , wherein the above-mentioned first voltage is higher than the above-mentioned second voltage; provide a reference clock signal as the operation signal of the above-mentioned operation method; store a data in the above-mentioned storage unit; update the data stored in the above-mentioned storage unit according to the timing frequency of the above-mentioned reference clock signal ; When the dynamic random access memory structure is in the normal operation mode, the above-mentioned second voltage is provided as the above-mentioned operating voltage to supply the operation of the above-mentioned dynamic random access memory structure, so as to save operating power consumption, when the dynamic random access memory structure is in When operating in the standby mode, the first voltage or the second voltage is determined as the operating voltage according to the clock of the reference clock signal; when the DRAM structure is operating in the sleep mode, the fixed output of the first voltage is The above-mentioned operating voltage is used for the operation of the above-mentioned DRAM structure, so as to maintain the above-mentioned data stored in the above-mentioned storage unit of the above-mentioned DRAM.

In the above operation method, the storage unit is composed of a third transistor and a capacitor, wherein one end of the capacitor is connected to a source/drain terminal of the third transistor, and the other end of the capacitor is connected to a third voltage, The other source/drain terminal of the above-mentioned third transistor is connected to the above-mentioned bit line, and one gate terminal thereof is connected to the word line, wherein when the dynamic random access memory structure is in the normal operation mode, the above-mentioned third voltage is the operating voltage A ratio, but the above-mentioned third voltage is less than the operating voltage, when the DRAM structure operates in the above-mentioned sleep mode, the above-mentioned third voltage is based on the above-mentioned reference clock signal, when the above-mentioned reference clock signal is a low level of logic 0 , reducing to zero voltage, so as to reduce the voltage value required to maintain the data stored in the storage unit of the dynamic random access memory.

In order to make the above and other objects, features, and advantages of the present invention more comprehensible, preferred embodiments are specifically described below together with accompanying drawings for a detailed description.

A brief description of the attached drawings:

FIG. 1 is a structural diagram of a DRAM memory cell used as an SRAM storage element in a preferred embodiment of the present invention;

FIG. 2 is a timing diagram of data reading and storage unit update in FIG. 1;

3 is a structural diagram of a DRAM memory cell used as an SRAM storage element according to a preferred embodiment of the present invention, which has a timing diagram of a low-voltage operation mode;

4 is a structural diagram of a DRAM storage unit used as an SRAM storage element according to a preferred embodiment of the present invention, which has a timing diagram of a standby mode of operation and a sleep mode of operation; and

FIG. 5 is a comparison diagram of charges stored in the normal operation mode and the sleep operation mode in the DRAM memory cell structure of the memory cell capacitor in FIG. 1 in the preferred embodiment of the present invention.

Brief description of the reference numbers

storage unit 110

Transistor 112

Capacitor C

Detection amplification device 120

Switching device 130

Pressure reducing device 140

First-class device 150

PMOS transistor SAP

NMOS transistor SAN

PMOS transistors P1 and P2

NMOS transistors N1 and N2

Example

A preferred embodiment of the present invention provides a Static Random Access Memory (SRAM), and is especially designed for the structure and operation method of the SRAM required in the currently widely used mobile electronic devices.

In this structure and operation method, the static random access memory (SRAM) of this embodiment uses a dynamic random access memory (Dynamic Random Access Memory, hereinafter referred to as DRAM) storage unit as a source of storing data. Because the area and manufacturing cost of a DRAM memory unit (Cell) using a single transistor and a capacitor are much smaller than that of an SRAM with 4 to 6 transistors. And as long as the problem that DRAM must be constantly refreshed (Refresh) can be overcome, and the stored content can be determined not to be lost, the manufacturing cost of the entire SRAM must be greatly reduced.

However, the static random access memory (1-TSRAM) structure using a single transistor in this embodiment can effectively preserve the data stored in the DRAM memory unit without loss. In addition, according to the SRAM structure of the present invention, it can operate under low voltage conditions, still maintain the data stored in the DRAM memory unit, and reduce the power consumed by the operation of the entire SRAM structure.

If the system adopts this SRAM structure, it can still maintain the data stored in the DRAM storage unit in the standby (Stand-by) mode or in the sleep mode (Sleep Mode), and can reduce the consumption of the entire SRAM structure operation. power. The so-called standby mode means that the power supplied by the entire system is still sufficient, just because the system is not currently in use, and in order to reduce power consumption, it enters a low power consumption standby state. The sleep mode means that the power of the entire system is not enough, but it is still higher than the operable specification. This mode is to protect the data currently being processed. It can last for a long time in the limited power, allowing users to Have time to restore the data it was originally using without losing it.

These two modes are most commonly used in electronic devices that use batteries and have a certain usage time limit, such as mobile phones, portable computers, personal data assistant devices (PDAs), and so on. Since SRAM has the characteristic of storing data for a long time, if a DRAM storage unit (Cell) with a single transistor and a capacitor is used as an SRAM, many factors must be considered, among which, for example, under low voltage operation (such as standby mode or sleep mode) Mode), how to re-update (Refresh) the storage content of the DRAM storage unit and how to maintain the stored data are issues that must be considered.

Please refer to FIG. 1 , which shows the structure of a DRAM memory cell used as an SRAM memory element in the present invention. For the convenience of explanation, only a single storage unit and a single detection unit (SenseAmplifier) are used here. Those skilled in the art know that there are multiple storage units and multiple detection units in the DRAM structure, and the operation method is the same as that described in this figure. , not redundant.

First, define the normal operating voltage of the SRAM structure as Vcca. Under normal operation, Vcca is equal to the external voltage Vccext. In this embodiment, if entering the standby mode, in order to save power consumption, the value of the operating voltage Vcca will be lowered from the external voltage Vccext by a predetermined value, for example, as shown in FIG. After the voltage drop, it is converted to Vccsa as the output operating voltage Vcca.

For the structure of this 1-T SRAM, it includes a storage unit 110 , a detection amplifier 120 , a switching device 130 , a step-down device 140 and an equalization device 150 .

The storage unit 110 is composed of a transistor 112 and a capacitor C. One end of the capacitor C is connected to a source/drain terminal of the transistor 112, and the other end of the capacitor is connected to a voltage source V _PL . The voltage value of the voltage source V _PL is about half of the operating voltage Vcca in normal operation. . In addition to connecting one source/drain terminal of the transistor 112 to the capacitor C, in addition, the other source/drain terminal of the transistor 112 is connected to a bit line (Bit Line, referred to as BL below), and its gate is Receive a word line (Word Line, hereinafter referred to as WL). In addition, the substrate of the transistor 112 is connected to the substrate bias (Substrate Bias) Vbb. During normal operation, the voltage of the substrate bias Vbb is -1V, which is beneficial for the transistor 112 to operate at a low voltage. voltage operation. In addition, the voltage used to turn on the transistor 112 is defined as Vpp, and Vpp comes from the word line WL.

The detection amplifier 120 includes a detection unit, a PMOS transistor SAP and an NMOS transistor SAN, and the detection unit is composed of two PMOS transistors P1 and P2 and two NMOS transistors N1 and N2. Its connection mode is the same as that of a general detection amplifier, that is, the gate of the PMOS transistor P2 and the gate of the NMOS transistor N2 are commonly connected to the bit line BL, and in addition, the gate of the PMOS transistor P1 and the gate of the NMOS transistor N1 are commonly connected to a Complementary Bit Line (Complementary Bit Line, referred to as CBL below). The bit line BL and the complementary bit line CBL are used as lines for reading data stored in the memory unit 110 .

One source/drain terminal of the PMOS transistors P1 and P2 is commonly connected to a source plate/drain terminal of another PMOS transistor SAP, and in addition, the other source/drain terminals of the PMOS transistors P1 and P2 are respectively connected to the NMOS transistor. A source/drain terminal of N1 and N2. The other source/drain terminals of the NMOS transistors N1 and N2 are commonly connected to a source/drain terminal of another NMOS transistor SAN. The other source/drain terminal of the PMOS transistor SAP is connected to the switching device 130, and the other source/drain terminal of the NMOS transistor SAN is connected to the ground.

The switching device 130 receives two voltage sources Vccext and Vccsa, and is used to switch and output one of the voltage sources. As mentioned above, Vccsa is smaller than Vccext by a predetermined level. In this embodiment, Vccext can be converted to Vccsa via, for example, the step-down device 140, and its actual implementation method can be completed, for example, via the threshold voltage (Threshold Voltage) Vtn of a transistor 142, and the value of Vccsa is equal to the reduction of Vccext. Vtn. The switching action of the switching device 130 can be controlled by a control signal CTL.

Firstly, an explanation will be made regarding the read operation of the DRAM memory cell structure as the SRAM memory element in FIG. 1 in the normal operation mode.

First, in the normal operation mode, the external voltage used will use Vccext as the value of the operation voltage Vcca. The voltage V _PL connected to the capacitor C of the storage unit 110 is set at half of the operating voltage Vcca to speed up the operation of the storage unit, and the voltage of the substrate bias Vbb is set to -1V to lower the threshold voltage .

In the pre-charge stage (Pre-charge stage) of the unread memory cell 110, the equalization device 150 will charge the two-bit lines BL and CBL to a certain voltage through the control of the voltage Vg, generally speaking, the operating voltage Vcca Half, and the equalization device 150 is composed of, for example, two MOS transistors, and the signal EQ of the control gate has a voltage value V _EQ of a high level (logic "1") at this stage, which is used to charge the two lines to a predetermined level.

Then, after the word line WL is selected, charges are shared between the memory cell 110 and the bit line BL. If the data stored in the memory cell 110 is "1", the potential of the bit line BL increases to more than half of the operating voltage Vcca, and the voltage of the bit line CBL decreases slightly below half of the operating voltage Vcca.

Then, after the NMOS transistor SAN of the detection amplifier 120 is turned on, that is, after the node 122 is grounded, the detection amplifier 120 starts to operate, that is, the NMOS transistor N2 is turned on and the voltage of the bit line CBL is pulled to the ground, and because the CBL The voltage of grounding will simultaneously turn on the PMOS transistor P1. At this time, the PMOS transistor SAP will be turned on to charge the operating voltage Vcca to the capacitor of the storage unit 110 through the bit line BL to Vcca, and then update to the original predetermined level.

The reading process is shown in Figure 2. For example, after the EQ stops precharging, after the word line WL turns to logic 1, the bit line BL will first rise partly, and then after the NMOS transistor SAN is turned on, the bit line The line BL will be turned high and recharge the capacitor C of the memory unit 110 to a predetermined value.

If the data stored in the storage unit 110 is "0", the operation process is similar. The potential of the bit line BL decreases to less than half of the operating voltage Vcca when the word line WL turns to a high level (logic 1), and the voltage of the bit line CBL is slightly higher than or slightly lower than half of the operating voltage Vcca.

Then, after the NMOS transistor SAN of the detection amplifier 120 is turned on, that is, after the node 122 is grounded, the detection amplifier 120 starts to operate, that is, the NMOS transistor N1 is turned on to connect the voltage of the bit line BL to the ground, and because BL The voltage of grounding will simultaneously turn on the PMOS transistor P2. At this time, the PMOS transistor SAP will be turned on, and the bit line CBL will be pulled up to the operating voltage Vcca, and the voltage of the bit line BL will be reduced to the lowest level, and the capacitor of the storage unit 110 will be discharged, and the value stored in the storage unit 110 will be updated again. "0".

Next, for the DRAM memory cell structure of this embodiment, how to effectively save the stored data in the low-voltage operation mode (such as standby mode or sleep mode) will be described in detail.

In the system using this DRAM memory cell structure, if there is no distinction between the standby mode to reduce power consumption and the sleep mode to further reduce power consumption, but only the general low-voltage operation, that is, only one low-voltage operation mode, please refer to Figure 1 and Figure 3 for description. Through the control of the switching device 130 by CS, the value of the operating voltage Vcca is converted from the original Vccext to the reduced value of Vccsa. The values of V _PL and V _EQ are reduced from half of Vccext to half of Vccsa. In the embodiment of the present invention, the added switching device 130 can be used to control the operating voltage of the entire system, thereby achieving the purpose of reducing power consumption.

In addition, if the system using the DRAM memory cell structure according to the embodiment of the present invention has a standby mode for reducing power consumption or a sleep mode for further reducing power consumption, please refer to FIG. 1 and FIG. 4 for illustrating timing. In order to reduce the power consumption of the entire system, the DRAM storage unit structure of the present embodiment only uses an external clock signal CLKref as the source of the clock, and all operations are all based on the external clock signal CLKref, without adding a clock generator, and separately Generates the internal clock signal.

In normal standby mode, the inverting value of the pass signal CS is controlled, and the operating voltage used can be switched between Vccext and Vccsa. At this time, the values of V _PL and V _EQ are also switched to half of Vccext or half of Vccsa to save power consumption.

But if it is in the sleep mode, because the remaining power is too low, it must be kept at a low voltage and the data stored in the DRAM memory unit should be saved. Therefore, many factors must be considered.

As shown in FIG. 4 , a sleep enable signal (Sleep) is provided, and the sleep enable signal is used as an enable signal for the system to enter the sleep mode. After the Sleep signal is enabled (Enabled), that is, when it is at a high level (logic 1), the operating voltage Vcca is converted to Vccext, and no step-down is required. This can be achieved by controlling the switching device 130 in FIG. 1 through the signal Sleep. And at this time, in order to save power consumption, all the word lines will be switched off in accordance with the low voltage and low level of a reference clock CLKref, that is, all the word lines are at 0V voltage. In addition, the substrate bias voltage Vbb of the transistor 112 of the memory unit 110 is also provided as a clock source according to the above-mentioned reference clock signal CLKref.

In addition, in this embodiment, it is also proposed that all DRAM storage unit structures refer to the same clock signal, that is, the above-mentioned reference clock CLKref, and this reference clock is provided by the entire external system instead of being additionally added by the DRAM storage unit structure. Produced by a clock generator (Clock Generator), this is different from the general DRAM structure that requires three internal clocks, and because of this, the power consumption required to generate the clock can be reduced, so as to reduce the power consumption that this embodiment intends to solve The problem.

The charge stored in the capacitor C of the memory unit 110 depends on the voltage difference across the capacitor C. Assuming that the external voltage Vccext is 3V, the Vccsa voltage after the voltage drop is 2V, or the external voltage Vccext is 2V, and the Vccsa voltage after the voltage drop is 1.5V. Under these circumstances, the data of the storage unit 110 can still be effectively stored in the sleep mode.

In addition, if the external voltage drops to a lower level, this is the current trend of portable electronic devices. For example, when Vccext=1.5V, because the operating voltage of this embodiment is switched to Vcca=Vccext, it is only 1.5V, and the storage unit 110 If the voltage V _PL at the other end of the capacitor C is still half of Vcca, that is, about 0.7V, in this case, the charge stored in the capacitor C is Q1=C×(1.5V-0.7V)×k(k is the charge sharing effect parameter, Charge Sharing Effect)=C×0.8×k. If the stored charge value is too low, the detection amplifier 120 may not be able to effectively detect the stored charge value, and there may be a possibility of data loss.

At this time, for the storage unit 110, it can be selectively changed, for example, the voltage V _PL connected to one end of the capacitor is changed from a fixed value of half of the operating voltage Vcca in the normal operation mode to a value that varies with the clock signal CLKref Change, that is, the voltage V _PL will switch from 0V to half of Vcca (actually half of Vccext at this time) according to the clock signal CLKref. Because in the sleep mode, the main purpose is to save power consumption, and there is no need to improve the operation efficiency by providing V _PL . The _VEQ value used to charge the bit line is also switched to one of 0V or half the value of Vcca following the clock signal CLKref.

Such a structure, if operated at low voltage, will have a significant effect. For example, suppose that when the system switches to sleep mode at time t1, the charge stored in capacitor C is Q1=C×(1.5V-0V)×k=C×1.5×k, which is higher than the original C×0.8×k Many, then there is no doubt that the sense amplifier 120 cannot detect the stored data. In addition, as shown in FIG. 5 , at the same time t1 , there is a significant difference in the charge stored in the normal mode and the Sleep mode of this embodiment.

Of course, the value of the voltage V _PL connected to one end of the adjustment capacitor and the _VEQ value of charging the bit line in this embodiment are also used in the case of non-low voltage operation, but the effect is not as significant as that of low voltage operation.

The static random access memory (1-T SRAM) structure using a single transistor of the present invention can effectively preserve the data stored in the DRAM memory unit without loss. In addition, according to the SRAM structure of the present invention, it can operate under low voltage conditions, still maintain the data stored in the DRAM memory unit, and reduce the power consumed by the operation of the entire SRAM structure.

Although the present invention has been disclosed above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore The protection scope of the present invention should be defined by the appended claims.

Claims (21)

1. one kind is applicable to the compatible transistorized DRAM structure of static RAM, wherein this DRAM structure is to operate under a normal manipulation mode and a low voltage operating pattern, wherein this DRAM structure is used the foundation of a reference clock signal as operation, and wherein this DRAM structure comprises:

One storage unit is in order to storage data;

One detects multiplying arrangement, have a detecting unit, a first transistor and a transistor seconds, wherein this detecting unit is connected with a paratope line with this first transistor, this transistor seconds, a bit line, wherein this bit line and this paratope line read in order to conduct and upgrade the stored data of this storage unit, and upgrade the stored data frequency of this storage unit according to this reference clock signal; And

One switching device shifter, in order to receiving one first voltage and one second voltage, and in order to switch output both one of and be an operating voltage, wherein the level of this first voltage is higher than the level of this second voltage, wherein

When this DRAM structure during at this normal manipulation mode, this operating voltage is this second voltage, for should DRAM structure manipulating, and saving the operation consumed power,

When this DRAM structure is operated under this low voltage operating pattern, this operating voltage is this first voltage, for should DRAM structure manipulating, with these stored data of this storage unit of keeping this dynamic RAM.

2. DRAM structure as claimed in claim 1, wherein this storage unit is made up of one the 3rd transistor AND gate, one capacitor, wherein one of this capacitor terminate to the 3rd transistorized source end, the other end of this capacitor is then received a tertiary voltage, the 3rd transistorized another source/drain terminates to this bit line, the one gate terminal is then received this word line, wherein

When this DRAM structure during at normal manipulation mode, this tertiary voltage is a ratio of this operating voltage, but this tertiary voltage is less than this operating voltage,

When this DRAM structure during in this low voltage operating pattern, this tertiary voltage is then according to this reference clock signal, when this reference clock signal is the low level of logical zero, reduce to no-voltage, keep the stored required magnitude of voltage of these data of this storage unit of this dynamic RAM with reduction.

3. DRAM structure as claimed in claim 2, when wherein operating when this normal manipulation mode, this tertiary voltage is half of this operating voltage.

4. DRAM structure as claimed in claim 1, wherein this transistorized base lining (Substrate) connects a base lining bias voltage (Substrate Bias).

5. DRAM structure as claimed in claim 4 wherein should provide with reference to this reference clock signal by base lining bias voltage.

6. DRAM structure as claimed in claim 1 wherein also comprises a dropping equipment, is connected to this switching device shifter and this first voltage, and exports this second voltage to this switching device shifter.

7. DRAM structure as claimed in claim 6, wherein this dropping equipment is made up of one the 4th transistor, and wherein this first voltage and this second voltage phase difference are the 4th a transistorized threshold voltage.

8. DRAM structure as claimed in claim 1, wherein this switching operation of switching device can be controlled by a control signal and select this first voltage of output or this second voltage.

9. one kind is applicable to the compatible transistorized DRAM structure of static RAM, wherein this DRAM structure is to operate under a normal manipulation mode, a standby mode and a sleep pattern pattern wherein, wherein this DRAM structure is used the foundation of a reference clock signal as operation, and wherein this DRAM structure comprises:

One storage unit is in order to storage data;

One detects multiplying arrangement, have a detecting unit, a first transistor and a transistor seconds, wherein this detecting unit is connected with a paratope line with this first transistor, this transistor seconds, a bit line, wherein this bit line and this paratope line are according to this reference clock signal in order to as reading and upgrading the stored data of this storage unit and upgrade the stored data frequency of this storage unit; And

One switching device shifter, in order to receiving one first voltage and one second voltage, and in order to switch output both one of and be an operating voltage, wherein the level of this first voltage is higher than the level of this second voltage, wherein

When this DRAM structure during at this normal manipulation mode, this operating voltage is this second voltage, for should DRAM structure manipulating, and saving the operation consumed power,

When this DRAM structure was operated under this standby mode, this operating voltage can be adjusted into this first voltage or this second voltage according to this reference clock signal;

When this DRAM structure is operated under this sleep pattern, this operating voltage can be fixed as this first voltage, for should DRAM structure manipulating, with these stored data of this storage unit of keeping this dynamic RAM.

10. DRAM structure as claimed in claim 9, wherein this storage unit is made up of one the 3rd transistor AND gate, one capacitor, wherein one of this capacitor terminate to the 3rd transistorized source end, the other end of this capacitor is then received a tertiary voltage, the 3rd transistorized another source/drain terminates to this bit line, the one gate terminal is then received this word line, wherein

When this DRAM structure during at this normal manipulation mode, this tertiary voltage is a ratio of this operating voltage, but this tertiary voltage is less than this operating voltage,

When this DRAM structure is operated under this sleep pattern, this tertiary voltage is then according to this reference clock signal, when this reference clock signal is the low level of logical zero, reduce to no-voltage, keep the stored required magnitude of voltage of these data of this storage unit of this dynamic RAM with reduction.

11. DRAM structure as claimed in claim 10, when wherein operating when this normal manipulation mode, this tertiary voltage is half of this operating voltage.

12. DRAM structure as claimed in claim 9, wherein this transistorized base lining (Substrate) connects a base lining bias voltage (Substrate Bias).

13. DRAM structure as claimed in claim 12 wherein should provide with reference to this reference clock signal by base lining bias voltage.

14. DRAM structure as claimed in claim 9 wherein more comprises a dropping equipment, is connected to this switching device shifter and this first voltage, and exports this second voltage to this switching device shifter.

15. DRAM structure as claimed in claim 14, wherein this dropping equipment is made up of one the 4th transistor, and wherein this first voltage and this second voltage phase difference are the 4th a transistorized threshold voltage.

16. DRAM structure as claimed in claim 9, wherein this switching operation of switching device can be controlled by a control signal and select this first voltage of output or this second voltage.

17. DRAM structure as claimed in claim 9, wherein this switching device shifter can be controlled and fixing this first voltage of output by a sleep enable signal when entering this sleep pattern.

18. method of operating that is applicable to the compatible transistorized DRAM structure of static RAM, wherein this DRAM structure comprises that a storage unit, detects a multiplying arrangement and a switching device shifter, this DRAM structure is operated under a normal manipulation mode and a low voltage operating pattern, and wherein this method of operating comprises the following steps:

One first voltage and one second voltage are provided, and switch output both one of and be an operating voltage of this method of operating, wherein this first voltage is higher than this second voltage;

The operation signal of one reference clock signal for this method of operating is provided;

Store data in said memory cells;

Time sequence frequency according to this reference clock signal upgrades the stored data of this storage unit;

When this normal manipulation mode, it is this operating voltage that this second voltage is provided, and for should DRAM structure manipulating, saves the operation consumed power,

When operating under this low voltage operating pattern, it is this operating voltage that this first voltage is provided, for should DRAM structure manipulating, with these stored data of this storage unit of keeping this dynamic RAM.

19. method of operating as claimed in claim 18, wherein this storage unit is made up of one the 3rd transistor AND gate, one capacitor, wherein one of this capacitor terminate to the 3rd transistorized source end, the other end of this capacitor is then received a tertiary voltage, the 3rd transistorized another source/drain terminates to this bit line, the one gate terminal is then received this word line, wherein

When at this normal manipulation mode, this tertiary voltage is a ratio of this operating voltage, but this tertiary voltage is less than this operating voltage,

When in this low voltage operating pattern, this tertiary voltage is then according to this reference clock signal, when this reference clock signal is the low level of logical zero, reduce to no-voltage, keep the stored required magnitude of voltage of these data of this storage unit of this dynamic RAM with reduction.

20. method of operating that is applicable to the compatible transistorized DRAM structure of static RAM, wherein this DRAM structure comprises that a storage unit, detects a multiplying arrangement and a switching device shifter, this DRAM structure is operated under a normal manipulation mode, a standby mode and a sleep pattern, and wherein this method of operating comprises the following steps:

One first voltage and one second voltage are provided, and switch output both one of and be an operating voltage of this method of operating, wherein this first voltage is higher than this second voltage;

The operation signal of one reference clock signal for this method of operating is provided;

Store data in said memory cells;

Time sequence frequency according to this reference clock signal upgrades the stored data of this storage unit;

When this DRAM structure during at this normal manipulation mode, it is this operating voltage that this second voltage is provided, for should DRAM structure manipulating, and saving the operation consumed power,

When this DRAM structure is operated, determine this first voltage or this second voltage is this operating voltage according to the clock of this reference clock signal under this standby mode;

When this DRAM structure is operated under this sleep pattern, fixing this first voltage of output is this operating voltage, for should DRAM structure manipulating, with these stored data of this storage unit of keeping this dynamic RAM.

21. method of operating as claimed in claim 20, wherein this storage unit is made up of one the 3rd transistor AND gate, one capacitor, wherein one of this capacitor terminate to the 3rd transistorized source end, the other end of this capacitor is then received a tertiary voltage, the 3rd transistorized another source/drain terminates to this bit line, the one gate terminal is then received this word line, wherein

When this DRAM structure during at this normal manipulation mode, this tertiary voltage is a ratio of this operating voltage, but this tertiary voltage is less than this operating voltage,

When this DRAM structure is when operating under this sleep pattern, this tertiary voltage is then according to this reference clock signal, when this reference clock signal is the low level of logical zero, reduce to no-voltage, keep the stored required magnitude of voltage of these data of this storage unit of this dynamic RAM with reduction.

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