CN1354494A - Lithographic Fabrication Method That Reduces Proximity Effects - Google Patents
Lithographic Fabrication Method That Reduces Proximity Effects Download PDFInfo
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Abstract
Description
本发明涉及一种光刻制作方法,且特别是涉及一种可以降低邻近效应的一种光刻制作工艺。The invention relates to a photolithography manufacturing method, and in particular to a photolithography manufacturing process capable of reducing the proximity effect.
在要求电路集成化越来越高的情况下,整个电路元件大小的设计也被迫往尺寸不停缩小的方向前进。而整个半导体制作工艺中最举足轻重的可说是光刻(Photolithography)制作工艺,凡是与金氧半导体(Metal-Oxide-Semiconduetor;MOS)元件结构相关的,例如:备层薄膜的图案(Pattern),及掺有杂质(Dopants)的区域,都是由光刻这个步骤来决定的。此外,整个半导体工业的元件集成度,是否能继续的往0.18μm以下更小的线宽进行,也决定于光刻制作工艺技术的发展。为了满足此需求,一些提高光掩模解析度的方法被不断地提出来,如光学邻近校正法(Opcical Proximity Correction,OPC)以及相移式光掩模(Phase ShiftMask,PSM)等等。Under the condition that circuit integration is required to be higher and higher, the design of the size of the entire circuit element is also forced to advance in the direction of continuous reduction in size. The most important part of the entire semiconductor manufacturing process is the photolithography (Photolithography) manufacturing process, which is related to the structure of Metal-Oxide-Semiconductor (MOS) components, such as: the pattern of the prepared film (Pattern), And the regions doped with impurities (Dopants) are determined by the step of photolithography. In addition, whether the component integration level of the entire semiconductor industry can continue to be smaller than 0.18μm is also determined by the development of photolithography manufacturing technology. In order to meet this requirement, some methods for improving the resolution of photomasks have been continuously proposed, such as Optical Proximity Correction (Opcical Proximity Correction, OPC) and Phase Shift Mask (Phase ShiftMask, PSM) and so on.
其中OPC的目的是用以消除因邻近效应所造成的关键尺寸偏差现象。邻近效应(Proximity Effect)是当光束透过光掩模上的图案投影在晶片上时,一方面由于光束会产生散射现象而使得光束被扩大。另一方面,光束会透过晶片表面的光致抗蚀剂层经由晶片的半导体基底再反射回来,产生干涉的现象,因此会重复曝光,而改变在光致抗蚀剂层上实际的曝光量。The purpose of OPC is to eliminate the critical dimension deviation caused by the proximity effect. Proximity Effect is that when the light beam passes through the pattern on the photomask and projects on the wafer, on the one hand, the beam will be enlarged due to the phenomenon of scattering of the light beam. On the other hand, the light beam will pass through the photoresist layer on the surface of the wafer and reflect back through the semiconductor substrate of the wafer, resulting in interference phenomenon, so the exposure will be repeated, and the actual exposure amount on the photoresist layer will be changed. .
由于在曝光图案的边缘,光线强度较弱,曝光量不足,因此容易造成光致抗蚀剂上所形成的图案边缘的图形相较于实际光掩模上图案有所扭曲或变短(shorting),并且影响曝光图案边缘的关键尺寸的精确度,而造成线宽或是图案转移上的误差。Due to the weak light intensity and insufficient exposure at the edge of the exposure pattern, it is easy to cause the pattern edge pattern formed on the photoresist to be distorted or shortened compared with the pattern on the actual photomask , and affect the accuracy of the key dimension of the edge of the exposure pattern, resulting in errors in line width or pattern transfer.
因此,一般而言,为了降低邻近效应对于曝光图案边缘的影响,通常会在光掩模上的曝光图案边缘形成形成一辅助图案。图1A与图1B所绘示为现有具有辅助图案的光掩模上视简图。其中,图1A为光掩模100上图案密度较高区域的上视简图,而图1B为光掩模100上单一图案区域的光掩模上视简图。Therefore, in general, in order to reduce the influence of the proximity effect on the edge of the exposure pattern, an auxiliary pattern is usually formed on the edge of the exposure pattern on the photomask. 1A and 1B are schematic top views of a conventional photomask with auxiliary patterns. 1A is a schematic top view of a region with a higher pattern density on the
请参照图1A,由于图案密度较高区域102的边缘图案102a,在进行图案转移的曝光步骤时,相较于中央密集图案102b所受光的光强度较弱,因此会在边缘图案102a旁,外加辅助图案106。Please refer to FIG. 1A , because the edge pattern 102a of the region 102 with a higher pattern density is weaker than the light intensity received by the central dense pattern 102b during the pattern transfer exposure step, so an additional light will be added beside the edge pattern 102a.
同样的,请参照图1B,在同一光掩模100上,单一图案104相较于密集图案区102,在进行图案转移的曝光步骤时,由于需要曝光的光强度相较于密集图案区102所需要的曝光的光强度较强,为了使在同一光掩模的所有图案所需的曝光光强度相当,因此在单一图案104的两侧分别外加一辅助图案106,以使单一图案104的图案密度与密集图案区102的密度相当。Similarly, please refer to FIG. 1B , on the
为了使辅助图案106不会在图案转移时一并转移至光致抗蚀剂上,因此一般辅助图案106的线宽b比元件图案(包括密集图案区102以及单一图案104)的线宽a还小(也就是a>b),且为了使边缘图案102a或是单一图案104的轮廓更加明显,所以辅助图案106与边缘图案102a以及单一图案104的距离D约需与曝光的波长()相同或较小,以达辅助效果。In order to prevent the
但是随着元件集成度越来越高,线宽做越来越小,元件图案也越显复杂,光掩模上的元件图案线宽也随之缩小,同时辅助图案的线宽也更加狭小,因此提高了光掩模的制造困难。此外,由于辅助图案106边缘图案102a以及单一图案104的距离约需与曝光的波长相同,因此当元件图案越来越复杂与密集,要在光掩模上预留与曝光光波长同宽的空间以形成辅助图案,更加提高光掩模的制造的困难与制造成本。除了制造光掩模上具有极大的困难外,在光掩模制造完成之后,进行辅助图案的缺陷改良(debug)也极为不易。However, as the integration of components becomes higher and higher, the line width becomes smaller and smaller, and the component patterns become more complex, the line width of the component patterns on the photomask is also reduced, and the line width of the auxiliary pattern is also narrower. The manufacturing difficulty of the photomask is thus increased. In addition, since the distance between the edge pattern 102a of the
因此本发明的目的,就是在于提供一种可降低邻近效应的光刻制作方法。Therefore, the object of the present invention is to provide a photolithographic fabrication method which can reduce the proximity effect.
为实现上述目的,本发明提供一种光刻制作方法,包括:提供一晶片,其上方形成有一第一光致抗蚀剂,之后以一光掩模,进行第一曝光显影制作工艺,图案化第一光致抗蚀剂,其中此光掩模上形成有第一元件图案与第一虚拟图案,且第一虚拟图案位于第一元件图案的周边,而将光掩模上的第一元件图案与第一虚拟图案转移至第一光致抗蚀剂,并相对应于第一光致抗蚀剂上形成第二元件图案与第二虚拟图案。接着,于图案化的第一光致抗蚀剂上形成第二光致抗蚀剂。最后,进行第二曝光显影制作工艺,移除部分第二光致抗蚀剂,并仅裸露出该第一光致抗蚀剂的该第二元件图案。In order to achieve the above object, the present invention provides a photolithographic manufacturing method, comprising: providing a wafer, forming a first photoresist on it, and then using a photomask to perform the first exposure and development manufacturing process, patterning The first photoresist, wherein the first element pattern and the first dummy pattern are formed on the photomask, and the first dummy pattern is located at the periphery of the first element pattern, and the first element pattern on the photomask The first dummy pattern is transferred to the first photoresist, and the second device pattern and the second dummy pattern are formed corresponding to the first photoresist. Next, a second photoresist is formed on the patterned first photoresist. Finally, a second exposure and development process is performed to remove part of the second photoresist and only expose the second element pattern of the first photoresist.
依照本发明的一优选实施例,其中第一元件图案的线宽与第一虚拟图案的线宽相同,且第一元件图案的一密度与第一虚拟图案与第一元件图案之间的一密度相同。According to a preferred embodiment of the present invention, wherein the line width of the first element pattern is the same as the line width of the first dummy pattern, and a density of the first element pattern is the same as a density between the first dummy pattern and the first element pattern same.
由于在光掩模上的第一元件图案的线宽与第一虚拟图案的线宽相同,因此可降低随着元件线宽越来越小,光掩模制造的困难度,而且光掩模形成后的检验以及修补也较现有的辅助光掩模容易,此外更可以改善光刻制作工艺的制作工艺裕度。Since the line width of the first element pattern on the photomask is the same as the line width of the first dummy pattern, it is possible to reduce the difficulty of making the photomask as the line width of the element becomes smaller and smaller, and the formation of the photomask The subsequent inspection and repair are also easier than the existing auxiliary photomask, and in addition, the manufacturing process margin of the photolithography manufacturing process can be improved.
为使本发明的上述和其他目的、特征、和优点能更明显易懂,下文特举一优选实施例,并配合附图作详细说明。附图中:In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is specifically cited below and described in detail with accompanying drawings. In the attached picture:
图1A所绘示为现有具有辅助图案的光掩模上视简图;FIG. 1A is a schematic top view of a conventional photomask with auxiliary patterns;
图1B所绘示为现有具有辅助图案的光掩模上视简图;FIG. 1B is a schematic top view of a conventional photomask with auxiliary patterns;
图2A所示为根据本发明一优选实施例的可降低邻近效应光刻制作工艺的光掩模上视简图;FIG. 2A is a schematic top view of a photomask that can reduce the proximity effect photolithography process according to a preferred embodiment of the present invention;
图2B为图2A的光掩模200沿线2B-2B′的剖面图;以及2B is a cross-sectional view of the
图3A至图3C为根据本发明一优选实施例以图2A的光掩模所进行的降低邻近效应光刻制作工艺流程的剖面简图。3A to 3C are schematic cross-sectional views of a process flow for reducing proximity effect lithography with the photomask shown in FIG. 2A according to a preferred embodiment of the present invention.
其中,各图标号与构件名称的关系如下:Among them, the relationship between each icon number and component name is as follows:
100、200:光掩模100, 200: Photomask
102、202、302:图案密集区102, 202, 302: pattern dense area
102a:边缘图案102a: Edge pattern
102b:中央密集图案102b: central dense pattern
104、204、304:单一图案104, 204, 304: single pattern
106:辅助图案106: auxiliary pattern
206a、206b、306a、306b:虚拟图案206a, 206b, 306a, 306b: dummy patterns
300:晶片300: chip
308:图案化光致抗蚀剂308: Patterned photoresist
309:缓冲层309: buffer layer
310:光致抗蚀剂310: Photoresist
实施例Example
图2A所示,为根据本发明一优选实施例的可降低邻近效应光刻制作方法的光掩模上视简图。图2B为图2A的光掩模200沿线2B-2B′的剖面图。图3A至图3C为根据本发明一优选实施例以图2A的光掩模所进行的降低邻近效应光刻制作工艺流程的剖面简图。FIG. 2A is a schematic top view of a photomask of a photolithographic fabrication method capable of reducing proximity effects according to a preferred embodiment of the present invention. FIG. 2B is a cross-sectional view of the
请参照图2A与图2B,首先提供一光掩模200,此光掩模200可以是一明场光掩模(clear field mask)或是一暗场光掩模(dark field mask),而于本实施例中以明场光掩模为例。光掩模200上形成有元件图案,包括一图案密集区202以及一单一图案204。分别在图案密集区202以及单一图案204的周边形成有虚拟图案(dummy pattem)206a与206b。Please refer to FIG. 2A and FIG. 2B. First, a
位于图案密集区202周边的虚拟图案206a的线宽b′不小于图案密集区202的图案线宽a′,优选的虚拟图案206a线宽b′相等于图案密集区202的图案线宽a′。同样的,单一图案204周边的虚拟图案206b的线宽d′不小于单一图案204的线宽c′,优选的虚拟图案206b线宽d′相等于单一图案204的图案线宽c′。此外,虚拟图案206a与图案密集区202的距离D′相等于图案密集区202中图案之间的距离D",也就是虚拟图案206a的线距宽以及图案密度,分别与图案密集区202的图案线距宽以及图案密度相同。除此之外,单一图案204与其周围的虚拟图案206b所组成的图案密度与图案密集区202的密度相同。The line width b' of the
接着,请参照图3A,提供一晶片300,此晶片300上形成有一图案化的光致抗蚀剂308。其中图案化光致抗蚀剂308例如是一正光致抗蚀剂或是一负光致抗蚀剂。以图2A所提供的明场光掩模做为图案化晶片300上的光致抗蚀剂为例,则图案化光致抗蚀剂308为一负光致抗蚀剂,而于晶片300上形成图案化光致抗蚀剂308的方法包括,先于晶片300上形成一光致抗蚀剂层(未绘示),之后进行一软烤(Soff Bake)制作工艺。软烤制作工艺的作用在于去除光致抗蚀剂中的溶剂、增加光致抗蚀剂的附着力以及增加后续步骤中所使用的显影剂对曝光与未曝光的光致抗蚀剂的选择性等等。Next, referring to FIG. 3A , a
接着,以图2A所提供的明场光掩模进行一曝光制作工艺,以将光掩模200上的密集图案区202、虚拟图案206a与206b以及单一图案204转移至晶片300上的光致抗蚀剂(未绘示)中。继之,进行一曝光后烘烤制作工艺(Post ExposureBake),继之进行一显影制作工艺,以形成具有密集图案区302、虚拟图案306a与306b以及单一图案304的图案化光致抗蚀剂308。其中密集图案区302、虚拟图案306a与306b以及单一图案304相对应于光掩模200上的密集图案区202、虚拟图案206a与206b以及单一图案204。Next, an exposure fabrication process is performed with the bright field photomask provided in FIG. etchant (not shown). Then, a post-exposure baking process (Post Exposure Bake) is performed, followed by a development process to form a
本实施例以一明场光掩模200以及于一负光致抗蚀剂上形成图案为例,然而其于实际应用上可以一暗场光掩模搭配于正光致抗蚀剂上进行本发明的所提供的光刻制作工艺。此外,与光掩模200相同的是,图案化光致抗蚀剂308中,位于图案密集区302周边的虚拟图案306a的线宽f不小于图案密集区302的图案线宽e,优选的虚拟图案306a线宽f相等于图案密集区302的图案线宽e。同样的,图案化光致抗蚀剂308中的单一图案304周边的虚拟图案306b的线宽h不小于单一图案304的线宽g,优选的虚拟图案306b线宽h相等于单一图案304的图案线宽g。此外,虚拟图案306a与图案密集区302的距离E相等于图案密集区302中图案之间的距离E′,也就是虚拟图案306a的线距宽以及图案密度,分别与图案密集区302的图案线距宽以及图案密度相同。This embodiment takes a bright-
由于光掩模上的虚拟图案206a的图案密度与图案密集区202的图案密度相同,而且,虚拟图案206a与206b的线宽b′与d′分别与图案密集区202的图案线宽a′以及单一图案204的线宽c′相同,因此在形成晶片300上的图案化光致抗蚀剂308时,图案密集区202的边缘图案以及单一图案204的边缘,则因为有虚拟图案206a与206b的辅助,而相对提高图案密集区202的边缘图案以及单一图案204的边缘的光强度以及曝光量,因此在光致抗蚀剂上形成的图案(图案化光致抗蚀剂308)相较于光掩模200上的元件图案不会失真太多,所以不会像现有因为曝光光强度弱,曝光量不足,而产生邻近效应,导致图形变形。Since the pattern density of the
再者,由于光掩模200上的虚拟图案206a与206b的线宽与图案密集区202的图案以及单一图案204的线宽相同,且虚拟图案206a至图案密集区202的边缘的距离以及虚拟图案206b至单一图案204的距离,并不像现有的辅助图案与元件图案的距离受限于曝光波长的长度的限制,因此,在制造光掩模上,大大降低了光掩模制造困难度。Furthermore, since the line widths of the
此外,现有辅助图案必须很小,而造成辅助图案于光掩模上形成的困难,而本发明的虚拟图案的线宽大小与元件图案的线宽大小相当,因此可以降低在光掩模上形成虚拟图案的困难,并且同时降低光掩模制造后的测试以及修正的困难度。同样的,本发明的虚拟图案也可以更加轻易的加入客户所设计的原始布局图中。另外,由于虚拟图案206a与206b可以拉近图案密集区202与单一图案204的图案密度差异,因此可以大幅改善制作工艺裕度。In addition, the existing auxiliary pattern must be very small, which causes the difficulty of forming the auxiliary pattern on the photomask, while the line width of the dummy pattern of the present invention is equivalent to the line width of the device pattern, so it can reduce the size of the line width on the photomask. Difficulty in forming dummy patterns, and at the same time reduce the difficulty of testing and correction after photomask manufacturing. Similarly, the virtual pattern of the present invention can also be more easily added to the original layout diagram designed by the customer. In addition, since the
继之,请参照图3B,于图案化光致抗蚀剂308上形成一层光致抗蚀剂310,并且填满图案密集区302、虚拟图案306a与306b以及单一图案304。其中,此光致抗蚀剂310可以是一正光致抗蚀剂或是一负光致抗蚀剂。Next, please refer to FIG. 3B , a layer of
继之,请参照图3C,进行光致抗蚀剂310的软烤制作工艺。接着,依序进行一曝光制作工艺与一曝光后烘烤制作工艺,继之进行一显影制作工艺,以移除部分光致抗蚀剂310,形成仅裸露出图案化光致抗蚀剂308的图案密集区302以及单一图案304的光致抗蚀剂310a。Next, referring to FIG. 3C , the soft-baking process of the
其中,在形成光致抗蚀剂310之前,可于晶片300上方形成一层缓冲层309。此缓冲层309例如是具有亲水性的抗反射涂布(Hydrophilic anti-reflectioncoating)或是具有亲水性化学结构的材质。由于缓冲层309为具有亲水性的材质所组成,因此在进行第二光致抗蚀剂310的显影步骤时,未被光致抗蚀剂310a覆盖的部分缓冲层309可以随着显影继之清洗一同移除。因为在图案化光致抗蚀剂308与光致抗蚀剂层310之间形成有一缓冲层309,因此可以避免于形成光致抗蚀剂310的过程中,图案化光致抗蚀剂308与光致抗蚀剂310产生混合作用(intermixing process)。Wherein, before forming the
由于在图案化光致抗蚀剂308上,直接形成另一层光致抗蚀剂310,并且图案化光致抗蚀剂310以形成覆盖图案化光致抗蚀剂308中的虚拟图案306a与306b,仅使得所需要的元件图案(也就是图案密集区302与单一图案304)裸露出,因此后续将元件图案由光致抗蚀剂转移至晶片300上时,不会同时将虚拟图案306a与306b一并转移。而光致抗蚀剂310a所裸露的图案化光致抗蚀剂308的元件图案亦由于经由上述具有虚拟图案206a与206b的光掩模200转移形成,因此图案密集区302的边缘以及单一图案304的边缘不会产生邻近效应。Since on the patterned
综上所述,本发明具有下列优点:In summary, the present invention has the following advantages:
1.本发明中由于光掩模上的虚拟图案的图案密度与元件图案密度相同,而且,虚拟图案的线宽分别与元件图案的线宽相同,因此在形成晶片上的图案化光致抗蚀剂时,元件图的边缘,则因为有虚拟图案的辅助,而相对提高元件图案边缘的光强度以及曝光量,因此在光致抗蚀剂上形成的图案相较于光掩模200上的元件图案不会失真,而可降低邻近效应。1. In the present invention, because the pattern density of the dummy pattern on photomask is identical with element pattern density, and, the line width of dummy pattern is identical with the line width of element pattern respectively, therefore patterned photoresist on formation wafer When the agent is used, the edge of the element pattern is relatively improved due to the assistance of the dummy pattern, and the light intensity and exposure amount of the edge of the element pattern are relatively increased. Patterns are not distorted, and proximity effects are reduced.
2.本发明中,因为光掩模上的虚拟图案线宽与元件图案的线宽相同,且虚拟图案至元件图案边缘的距离,并不像现有的辅助图案与元件图案的距离受限于曝光波长的长度的限制,因此,大大降低了光掩模制造困难度。2. In the present invention, because the line width of the dummy pattern on the photomask is the same as that of the component pattern, and the distance from the dummy pattern to the edge of the component pattern is not limited as the distance between the existing auxiliary pattern and the component pattern The limitation of the length of the exposure wavelength, therefore, greatly reduces the difficulty of photomask fabrication.
3.现有辅助图案必须很小,以防止辅助图案在曝光显影过程中,转移至光致抗蚀剂上,但却造成辅助图案于光掩模上形成的困难,然而本发明的虚拟图案线宽大小与元件图案线宽大小相同,因此可以降低在光掩模上形成虚拟图案的困难,并且同时降低光掩模制造后的测试以及修正的困难度。3. The existing auxiliary pattern must be very small to prevent the auxiliary pattern from being transferred to the photoresist during the exposure and development process, but it causes difficulties in forming the auxiliary pattern on the photomask. However, the virtual pattern line of the present invention The width is the same as the element pattern line width, so the difficulty of forming a dummy pattern on the photomask can be reduced, and at the same time, the difficulty of testing and correction after the photomask is manufactured can be reduced.
4.本发明的虚拟图案也可以更加轻易的加入客户所设计的复杂原始布局图中。另外,由于虚拟图案可以拉近件图案中,图案密集区与单一图案的图案密度差异,因此可以大幅改善制作工艺裕度。4. The virtual pattern of the present invention can also be more easily added to the complex original layout diagram designed by the customer. In addition, since the dummy pattern can shorten the pattern density difference between the pattern-dense area and the single pattern in the part pattern, the manufacturing process margin can be greatly improved.
5.本发明中,利用依序形成两层图案化光致抗蚀剂,以第二层图案化光致抗蚀剂覆盖第一层图案化光致抗蚀剂的虚拟图案,因此不会将虚拟图案由光致抗蚀剂转移至下层晶片。5. In the present invention, by forming two layers of patterned photoresist in sequence, the dummy pattern of the first layer of patterned photoresist is covered with the second layer of patterned photoresist, so it will not be The dummy pattern is transferred from the photoresist to the underlying wafer.
虽然本发明已结合一优选实施例揭露如上,然而其并非用以限定本发明,本领域的技术人员在不脱离本发明的精神和范围内,可作出各种的更动与润饰,因此本发明的保护范围应当由后附的权利要求所界定。Although the present invention has been disclosed above in conjunction with a preferred embodiment, it is not intended to limit the present invention. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection should be defined by the appended claims.
Claims (23)
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| CNB001309218A CN1174468C (en) | 2000-11-21 | 2000-11-21 | Photoetching making method capable of reducing proximity effect |
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| CNB001309218A CN1174468C (en) | 2000-11-21 | 2000-11-21 | Photoetching making method capable of reducing proximity effect |
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| CN1354494A true CN1354494A (en) | 2002-06-19 |
| CN1174468C CN1174468C (en) | 2004-11-03 |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1326203C (en) * | 2004-01-05 | 2007-07-11 | 旺宏电子股份有限公司 | Method and device for improving critical dimension consistency among different patterns of semiconductor elements |
| CN100403166C (en) * | 2003-10-06 | 2008-07-16 | 松下电器产业株式会社 | Photomask and method for forming pattern |
| CN101241302B (en) * | 2007-02-06 | 2011-03-23 | 中芯国际集成电路制造(上海)有限公司 | Preparation method for improving mask critical size trend |
| CN104808435A (en) * | 2014-01-24 | 2015-07-29 | 中芯国际集成电路制造(上海)有限公司 | Detection method for double masks in OPC |
| CN107664916A (en) * | 2017-09-30 | 2018-02-06 | 德淮半导体有限公司 | Semiconductor device and its manufacture method |
| CN111638625A (en) * | 2020-06-04 | 2020-09-08 | 厦门通富微电子有限公司 | Mask, method for preparing semiconductor device and semiconductor device |
| CN111638624A (en) * | 2020-06-04 | 2020-09-08 | 厦门通富微电子有限公司 | Mask, method for preparing semiconductor device and semiconductor device |
-
2000
- 2000-11-21 CN CNB001309218A patent/CN1174468C/en not_active Expired - Lifetime
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100403166C (en) * | 2003-10-06 | 2008-07-16 | 松下电器产业株式会社 | Photomask and method for forming pattern |
| CN1326203C (en) * | 2004-01-05 | 2007-07-11 | 旺宏电子股份有限公司 | Method and device for improving critical dimension consistency among different patterns of semiconductor elements |
| CN101241302B (en) * | 2007-02-06 | 2011-03-23 | 中芯国际集成电路制造(上海)有限公司 | Preparation method for improving mask critical size trend |
| CN104808435A (en) * | 2014-01-24 | 2015-07-29 | 中芯国际集成电路制造(上海)有限公司 | Detection method for double masks in OPC |
| CN104808435B (en) * | 2014-01-24 | 2019-05-17 | 中芯国际集成电路制造(上海)有限公司 | The detection method of double mask plates in a kind of OPC |
| CN107664916A (en) * | 2017-09-30 | 2018-02-06 | 德淮半导体有限公司 | Semiconductor device and its manufacture method |
| CN111638625A (en) * | 2020-06-04 | 2020-09-08 | 厦门通富微电子有限公司 | Mask, method for preparing semiconductor device and semiconductor device |
| CN111638624A (en) * | 2020-06-04 | 2020-09-08 | 厦门通富微电子有限公司 | Mask, method for preparing semiconductor device and semiconductor device |
| CN111638625B (en) * | 2020-06-04 | 2023-03-14 | 厦门通富微电子有限公司 | Mask, method for preparing semiconductor device and semiconductor device |
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|---|---|
| CN1174468C (en) | 2004-11-03 |
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