CN1347591A - Improved frequency synthesisers - Google Patents

Abstract

A fractional-N frequency synthesiser having an increased range of fractional control values outside the usual range {0,1}. The synthesiser is based on a PLL having a frequency divider controlled by an improved modulator system. Noise and fractional spurs in the output of the PLL are reduced. The modulator includes a multi-level quantiser with additional logic operations in output and feedback stages. A cascade of modulators may be used. A dither signal may be added as required within one or more of the modulators.

Description

Improved Frequency Synthesizer

field of invention

The present invention relates to sigma-delta modulators, in particular to radio frequency synthesizers which use such modulators in fractions, but the invention is not limited thereto. More specifically, the present invention relates to modulator systems that extend the range of fractional frequencies and reduce spurious frequency emissions.

Background of the invention

Radio communication devices employ various forms of frequency synthesizers to control the transmission and reception of signals. A synthesizer typically includes a reference oscillator that generates a stable reference frequency signal and is used to determine the output value of the frequency controllable oscillator, which in turn generates a variable RF output signal. This output signal is typically coupled to the communication device's antenna via one or more mixers, which modulate or demodulate received or transmitted signals, respectively. The synthesizer can be programmed by a control unit, such as a digital processor, to generate a controlled oscillator signal in the frequency range required by the device. Frequency synthesizers are also frequently used in power amplification systems for transmitters of radio broadcast transmitters.

An indirect frequency synthesizer uses one or more phase-locked loops (PLLs) to generate a variable output signal from a frequency-controlled oscillator. The phase locked loop includes a phase detector, which generates an output according to the phase difference between the reference signal and the feedback signal. The feedback signal is typically generated by frequency dividing the output of a controlled oscillator. The output of the phase detector is applied to a loop filter which provides a control signal to the controlled oscillator. Typically voltage rather than current controlled oscillators are used. In general, this type of feedback loop attempts to match the frequency of the controlled oscillator to a plurality of reference frequencies and to stabilize a predetermined phase difference between the reference signal and the feedback signal.

The frequency division of the output of the frequency controlled oscillator can be implemented in various ways to allow relatively low frequency parameters to determine a wide range of RF output frequencies. In many cases, integer frequency division techniques are acceptable. However, fractional division techniques became commonplace and allowed synthesizers to achieve the finest possible frequency resolution. These techniques modulate the instantaneous integer fractional frequency fed back to the phase detector to produce an averaged non-integer fractional frequency. The non-integer value includes an integer part N having a value N and a fractional part FP having a value generally in the range {0, 1}. Cyclic changes in the divider value typically produce spurious frequencies and additional phase disturbances in the synthesized output signal. Various cancellation schemes, such as phase interpolation, have been employed to reduce fractional traces and interference, but generally increase the complexity and cost of the synthesizer to achieve significant reductions in trace magnitude.

Fractional-N synthesizers using sigma-delta modulators to reduce phase interference and trace numbers produced by non-integer division values are known, as described in US Patent 4,609,881. This modulation technique emerged as a development of analog-to-digital conversion and is widely used in electronic communication devices for a variety of purposes. It includes feedback to improve the effective resolution of the coarse quantizer and to allow interference shaping resulting from quantization. Generally, the input is fed to the quantizer through an integrator, and the quantized output is fed back and subtracted from the input. The output of the modulator thus comprises the original signal plus a first difference of the quantization error. The first sequential process therein may be implemented in whole or in part using digital signals. A detailed description of the sigma technique can be found in "Sigma-delta Data Converters", IEEE Press, 1997.

Higher order sigma-delta generally use two or more integrators, each integrator receiving a feedback signal from the output value, to improve the overall jamming performance. A cascade is also sometimes used, where the outputs of two or more modulators are combined in a way that cancels the interference they individually create. For example in a cascade with two modulators of a first order, the output of the first modulator is fed into the second modulator. The output of the second modulator is differentiated from and subtracted from the output of the first modulator to provide a net signal. This leaves the interference as a second difference in the quantization error of the second modulator, a form similar to that of a second order modulator. Multi-level quantizers are also used to improve the stability of higher order and cascaded modulators.

Summary of the invention

The object of the present invention is to improve the performance of fractional-N frequency synthesizers. This improvement is directed, inter alia, to increased flexibility in the selection of divider values and reduced output of spurious frequencies or disturbances. Generally, these improvements can be achieved by a sigma-delta modulator with a quantizer with logic control in the output and/or feedback stages.

According to one aspect, the invention relates broadly to a frequency synthesizer comprising: a synthesizer loop including programmable frequency dividers, and a controller which determines the average minimum frequency of the frequency dividers Numeric values, where each division value includes selected integer and fractional parts, and the selected fractional part varies in a range different from {0, 1}.

In a second aspect of the invention, the invention relates to a frequency synthesizer comprising: a synthesizer loop including a programmable frequency divider, a frequency divider control device which provides a signal to the frequency divider for fractional frequency division and thereby generate the desired output frequency from the loop, wherein the control means includes at least one digital modulator, the modulator has an adder, a connected to the output of the adder and latches between the inputs, and an output logic stage that performs logic operations on one or more bits output by the adder.

In a third aspect of the present invention, the present invention also relates to a frequency synthesizer comprising: a synthesizer loop including a programmable frequency divider, a frequency divider control device, the frequency divider The control means provides a signal to the frequency divider for fractional frequency division thereby generating the desired output frequency from the loop, wherein the control means includes at least one digital modulator having an adder connected to A latch between the output and input of the adder and a feedback logic stage that performs logic operations on one or more bits output by the adder.

In a fourth aspect of the present invention, the present invention relates to a digital modulator comprising: an adder receiving a control signal and an error signal as input values and generating a multi-bit output value by adding the inputs, an output logic stage, which receives an input derived from at least one bit of the output value of the adder and performs logic operations on the input to produce a modulator output signal, and a feedback path comprising a latch, It combines at least two sets of bits in the output of the adder and produces an error signal.

In a fifth aspect of the invention, the invention relates to a modulator arrangement comprising, two or more modulators, each having an adder, a latch connected between the input and the output of the adder and an output logic stage in which the modulators are connected such that the output of the latch in each modulator is coupled to the input of the adder in the next modulator, if any, and the logic in each modulator The outputs of the stages are connected to a common combining stage to produce the output of the device.

Detailed description of the drawings

Preferred embodiments of the present invention will be described below with reference to the accompanying drawings, in which

Figure 1 schematically shows a frequency synthesizer with frequency dividers that can be programmed with integer values;

Figure 2 shows a frequency synthesizer where the frequency divider is modulated for fractional frequency division;

Figures 3a, 3b illustrate conventional accumulators performing the transfer function of a sigma-delta modulator and a corresponding quantizer, respectively;

Figures 4a, 4b show the ideal σ-δ modulator and the Z variation pattern corresponding to the transfer function of an ideal two-stage quantizer, respectively;

Figure 4c shows a Z-transform pattern equivalent to Figure 4a for comparison with Figure 6;

Figure 4d is another mode showing how a dither signal can be added to a sigma-delta modulator to reduce the limit period;

Figure 5 shows a three-level sigma-delta modulator formed by cascading the first order modulators shown in Figure 3;

Figure 6 is an accumulator circuit with logic stages forming an improved first order sigma-delta modulator according to the present invention;

Figures 7a, 7b, 7c show two-, four-, and eight-level transfer functions that can be implemented by the quantizer of Figure 6,

Figure 8 is a table showing how the logic stages of the modulator in Figure 6 are implemented to form a two-stage quantizer;

Figures 9a, 9b are tables showing how the logic stages of the modulator in Figure 6 are implemented to form a four-stage quantizer;

Figure 10 shows the fractional values produced by a modulator with a quantizer having the four-level transfer function of Figures 9a, 9b;

Figure 11 shows a three-level modulator formed by cascading the first order modulators shown in Figure 6, most likely with different quantizer stages;

Figure 12 is a table showing the required scaling factors for the input and output of a single modulator in Figure 11 when the quantizer has different output stages;

Figure 13 is a table summarizing the performance of modulators for a range of possible multilevel quantizers;

Fig. 14a, 14b show the sampling output of the multipole modulator system of Fig. 5, 11 respectively;

Fig. 15 is another modulator according to Fig. 6, wherein the feedback from the quantizer is dithered;

Figure 16 is a table showing possible implementations of a quantizer.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

As will be understood with reference to the accompanying drawings, the frequency synthesizer or more specifically a sigma-delta modulator of the present invention can be constructed in various forms within the scope of the claims. Preferred embodiments of the invention are described below, by way of example only. Known components of synthesizers and modulators are understood by those skilled in the art, so a detailed description of the functions of these components is not required.

Figure 1 shows a simple frequency synthesizer utilizing a phase locked loop (PLL) 10 as a feedback control system. The loop includes a phase detector 11 , a filter 12 , a reference oscillator 13 and a voltage controlled oscillator (VCO) 14 . A programmable frequency divider 15 is included in the feedback loop 16 from the VCO to the phase detector. The phase detector is used to compare the frequency f ₁ of the signal from the reference oscillator with the frequency f ₀ of the signal from the VCO after dividing by an integer N in the frequency divider. If the phase of the reference signal leads the phase of the divided VCO signal, then the output value of the phase detector is effectively a frequency down signal, which is used to reduce the frequency of the VCO. If the phase of the reference signal lags the frequency of the divided VCO signal, then the output of the phase detector is a frequency up signal that increases the frequency of the VCO. Under normal operating conditions, the phase locked loop is stable such that the signal input to the phase detector has zero phase difference and the output of the VCO forms the output of the synthesizer with f ₀ =Nf ₁ . A controller 17 sets the value of N within a range of discrete integer values.

Figure 2 shows a conventional fractional-N frequency synthesizer in which controller 17 varies the instantaneous value of N via modulator 20. This results in a range of non-integer division values obtainable from the dual analog-to-digital divider 25 in the feedback loop 10 . The frequency division value changes periodically from N to N+1 in one cycle determined by the controller 27 . In this embodiment, the modulator simply consists of a K-bit accumulator which receives the control word k from the controller on line 21 . The output pulse from each divider is clocked to an accumulator on line 22 and the input word is added to the accumulator content. If the content of the accumulator exceeds 2 ^k , then an overflow signal is generated on line 23 and a single divide by N+1 instead of N is performed in the frequency divider. For a constant input word, the accumulator overflows every ^2k /k pulse clocks. This produces an average frequency division value with an integer part IP=N and a fractional part FP=k/2 ^k <1, which are determined by the controller. Under normal operating conditions, the PLL is stable such that the signals input into the phase detector have an average phase difference equal to zero, and the output of the VCO forms a synthesizer with f ₀ =(N+k/2 ^k )f ₁ Output.

Figure 3a shows the accumulator of Figure 2 in more detail. An adder 30 has two inputs, one of which receives the control word k from the controller 27 on line 21 . The second input receives the output signal c of the adder through the latch 31 . The overflow signal from the adder is passed to the divider on line 23, and the latch is clocked by the output value of the divider on line 22. The accumulator acts as a first order sigma-delta modulator, where the overflow signal represents the quantized Q of the adder's output signal c. Figure 3b shows the quantized transfer function Q(c) which is not symmetric about the zero point.

Fig. 4a shows the Z transmission mode of an ideal first order sigma-delta modulator compared with the modulator of Fig. 3a. The input value k is fed to a two-stage quantizer 40 via an integrator and delay 42 represented by a summation function 41 . The output Y of the modulator is fed back through a delay 43 and subtracted from the input value by a summing function 33 . The output of the integrator is represented by a signal u which is approximately equal to the second input signal c of the accumulator of Fig. 3a. Figure 4b shows an ideal two-level quantized transfer function Q(u), which is symmetric about zero. Fig. 4c is the same pattern as that of Fig. 4b, which pattern will be described later in the description in relation to Fig. 6 .

Figure 4d shows how a dither signal can be added to the modulator arrangement. Dithering is a known process in which typically a random or at least quasi-random sequence of numbers is added to a digital data stream to reduce the likelihood of any cyclic patterns occurring. The mean of the sequence is zero so there is no overflow effect on the output. In this embodiment, the cyclic output from the modulator is passed to a frequency divider and spurious frequencies are generated on the output value of the synthesizer. If desired, in a particular embodiment a dither sequence d . This can effectively randomize the quantized interference signal e more effectively. The sequence d has to be pre-filtered to pass through a modulator, preferably a transformer (1-Z ^-1 ) to preserve the interference shape.

Fig. 5 shows a three-level modulator 50 formed by cascading conventional first order modulators 51, 52, 53 such as accumulators as shown in Fig. 3a. A control word X generates a relatively complex signal Y, which can be provided to the divider 25 shown in FIG. 2 to determine the average division value of the feedback loop 10 . The content of each modulator stage forms an error signal which is used as input to the next stage, while each output value is passed through a corresponding pair of delay elements 54 . The selection of output values of the modulator and delay elements is then passed to a combining stage 55 . These outputs are chosen and combined such that signal Y includes high order corrections for quantization errors. Each modulator and each delay circuit is clocked by the output of the frequency divider.

With the accumulator overflow setup as shown in Figure 2, fractional-N division results in spurious frequencies in the output value of VCO 14. These spurs are offset from the output frequency f ₀ by nf ₁ k/2 ^k , where n=0, 1, 2, 3 . . . . For larger values of n the traces fall outside the bandwidth of the loop 10 and are attenuated by the filter 12 . Additional circuitry is generally required to reduce the number of traces within the bandwidth, which increases the complexity and cost of the synthesizer. The divided frequency modulated by the output of the cascade in Fig. 5 has no fractional trace for most of the control word X. However, signal Y is a range of integer values, and frequency divider 25 must be able to perform multiple modulo divisions in the loop. In both cases, the fractional part FP of the average frequency division value is bounded in the range {0, 1} for any given integer part IP.

Fig. 6 shows a preferred modulator 60 according to the present invention, which can be used to extend the range of the fractional part FP of the average frequency division value in a frequency synthesizer. A control word X generates output Y which can be used to modulate the frequency divider in FIG. 2 . All signals in this figure are digital and in 2=S format. An n-bit adder 61 has two outputs, one of which receives the control word. The second input receives the error signal e derived from the output value of the adder after various feedback processes have been applied to the most and least significant bits. An output logic stage 62 receives the set t of most significant bits from adder 61 and operates on the bits during quantization, which produces the modulator output. A feedback logic stage 63 also receives the set t from adder 61 and operates on the bits during the feedback stage to determine the overload and smoothing performance of the modulator. An m-bit adder receives a set of m most significant bits from adder 61 and a set of m bits from feedback logic stage 63 . A latch 65 receives a set of n-m least significant bits from adder 61 and a set of m bits from adder 64 to form the error signal. Latch 65 receives a clock pulse signal that moves the modulator from one state to the next through the addition process in adder 61 or adder 64 .

The output and feedback logic stages 62 and 63 in FIG. 6 can be provided in various ways. Dedicated boolean operations on the bit groups are one way. Or one of the two stages could be a multiplexer from which the output is selected by the value of bit group t. The output value of the multiplexer can be set in hardware or stored, for example, in a register.

If desired, a dither signal can be added to the modulator at any time, either at the input of adder 61 with control word X, or at the output of adder 61, or as a feedback logic stage as described below. part. A dither signal typically increases the amplitude of the signal to which it is applied. If the fractional range of the present modulator is increased, an additional adder equivalent to summation function 48 of Fig. 4d is necessary to add a dither signal before the input of adder 61. At the output of adder 61 an additional adder equivalent to function 49 is required for the addition.

Figures 7a, 7b, 7c show idealized transfer functions Q(u) for two-level, four-level and eight-level quantizers respectively, each of which can be implemented by the modulator 60 of Figure 6 . Each function produces a multipole output signal f based on the position of the input signal u in one of a series of decision regions defined by point d. In general, the range of possible decision regions and corresponding stages in the output signal is determined by the number of bits in group t from adder 61 . One, two and three bits provide eg two-level, four-level and eight-level quantization respectively. All of the above embodiments are possible, as shown by a comparison of modulators with an ideal sigma-delta modulator pattern in Fig. 4c. The adder 61 executes the addition function 44 . An output stage 62 forms the quantizer 40 . A digital-to-analog function implicit in the feedback of Fig. 4c is performed by the feedback logic stage 63 to allow the above comparison. Adder 64 executes add function 46 . L65 executes deferred function 47. The performance of quantizer 40 is determined by proper selection of parameters within output logic stage 62 .

FIG. 8 is a table outlining the selection of parameters for the output and feedback logic stages that will implement an ideal two-stage quantizer in the modulator in FIG. 6 . In this table B=2 ⁿ , where n is the length of adder 61, group t contains a single bit. Column (I) contains the possible values of t required to generate two levels. Columns (ii) and (iii) give the corresponding decision fields in alternative decimal and binary form. Columns (iv) and (v) give the function of the output logic stage 62 . The output logic stage 62 acts in this simple case as an inverter. For higher stages, more complex matching of multibit t to quantizer output is required. Columns (vi), (vii), (viii) give the functionality of the feedback logic level. Column (vi) includes bits that determine the feedback rate, and said bits can be chosen with some degree of freedom.

Figures 9a, 9b are tables summarizing alternative options for the parameters of the output and feedback logic stages implementing an ideal four-stage quantizer in the modulator of Figure 6 . In this embodiment, the fractional part of the frequency division value is within the range {-1.5, 1.5} shown in FIG. 10 . Figure 9a is a diagram illustrating an embodiment of decision region selection to give optimum interference performance. Figure 9b shows an embodiment of a selection scheme with fewer bits for optimal hardware efficiency. In each table, the left-hand part represents the decision part of the input of the quantizer, the middle part represents the n-bit output of the adder 61, and the right-hand part represents the feedback rate and the output signal Y. In general, for any implementation, the choice of feedback rate affects the overload performance and thus the disturbance shaping performance of the modulator for a particular value of control word X . A high overload point allows a wider range of control values, but degrades the performance required for equalization considerations.

Figure 10 shows the range of fractional frequency values that can be generated in a synthesizer by the modulator outlined in Figures 9a, 9b when implementing a four-level quantizer. In this embodiment, the fractional part values are in the range of {-1.5, 1.5}, while the integer part is shown as three consecutive values: N-1, N, N+1. The corresponding values for the fractional part are 1.25, 0.25 and -1.25, so that the sum of the fractional and integer parts equals N+0.25 in each case. It can be seen that in three different ways, by appropriate selection of the fractional part for the three different integer part values, an average frequency division value can be achieved. Of course it is also possible to use other parameters in the output logic stage 62 of the modulator to make the fractional part wider. The values of IP and FP can be chosen with greater flexibility than in normal synthesizers, where FP values are preferably limited to the range {0, 1}. The extended range of FP provides an advantage where changes in synthesizer frequency typically require changes in both the integer and fractional parts of the averaging frequency. Frequency changes over a wide range of FP values can be achieved by individual changes in the fractional part. Less information about the frequency variation is required to be programmed in the controller 17 of the frequency synthesizer including the preferred modulator.

FIG. 11 shows a three-level modulator 110 formed from the first sequential modulators 111 , 112 , 113 shown in FIG. 6 . All control words k generate a complex signal Y which can be used in the frequency divider 25 in FIG. 2 to determine the fractional part FP of the average frequency division value in the feedback loop 10 . Each modulator can have a different quantization function, in this embodiment they have 1, 2, 3 bit outputs respectively. This arrangement is generally similar to the setup of Figure 5, except that a scaling function must be included so that the output levels of the corresponding quantizers are correctly combined. The described embodiment can be simplified by assuming n-bit adders 61 per modulator. The outputs of the modulators 111, 112, 113 are scaled by S12, S22, S32 respectively before passing through the delay element 114 to the channel of the combining stage 115. The inputs of the modulators 112, 113 can be scaled by S21, S31. In general, the scaling ratio depends on the capability of the adder 61, the first quantization step and the overload point of each modulator.

Figure 12 is a table summarizing the selection of scaling factors for a possible implementation of the modulator of Figure 1, assuming that the adders 61 shown in Figure 6 have the same length. All scenarios for this setup are determined by the first level which must have a sufficiently high capacity. The capacity of the latter stage can be reduced without significant loss of interference shaping capacity. A preferred arrangement is shown in the fourth row of the table, where a modulator with a four-level quantizer is followed by two two-level quantizers. In binary signals, scaling by powers of 2 is straightforward, and with careful design, such scaling can be implemented without additional hardware.

FIG. 13 is a table summarizing some features of the few multipole modulators shown in FIG. 6 . The table includes a representation of the range of possible output stages in a third order modulator as shown in FIG. 11 when formed from an arrangement of first order modulators having the same characteristics. This figure shows by way of example the range up to {-3.5~3.5} of the fractional part of the division frequency that can be obtained in a frequency synthesizer. Of course with other embodiments higher ranges are possible. This table includes modulators with odd and even quantization stages, and modulators that have a linear relationship between the decision region and the feedback stage. Non-linear relationships can also be established if desired to avoid the output of specific traces.

Figures 14a, 14b are output samples of the modulator devices shown in Figure 5 and Figure 11, respectively. Rows I, II, III in each case represent the output of each of the three first order modulators 51 , 52 , 53 and 111 , 112 , 113 before being input to the corresponding delay element 54 , 114 . Row IV in each example represents the output of the combining stage 55,115. A limit cycle in the output of the first modulator stage is marked and causes fractional traces.

FIG. 15 shows another preferred modulator 150 formed from the modulator 60 of FIG. 6 by adding a dither signal in the feedback process. The dither signal is preferably pre-filtered as described with reference to Figure 4d to avoid interference. The logic stage 63 produces only limited feedback signals, and a new stage 153 is easily formed by combining the dither signal as an additional input. Before the adder 61 receives a set of t most significant bits, m bits of logic levels are selected from a predetermined set of coefficients according to the values S and D for output. The output of the adder updates the quantization error signal with the dither signal to reduce the likelihood of extreme cycles occurring for a particular control word X.

Figure 16 shows a table showing the possible range of feedback logic stage 153 coefficients when modulator 150 implements a two-stage quantization function. F is the coefficient value that can be fed into adder 64 in the absence of a dither signal. L represents a numerical value corresponding to the dither signal d to be added. The value of L is limited to avoid overload and increase of background interference.

Modulators according to the invention may also be implemented in various electronic systems other than frequency synthesizers. For example digital-to-analog conversion. It is also possible to use modulators in various cascaded arrangements as shown in Figure 11. Higher order systems are possible by nesting multiple modulators and providing appropriate feedback.

Claims (22)

1. frequency synthesizer, it comprises

One phase-locked loop, described phase-locked loop comprise programmable frequency divider and

One controller, described controller are determined the average fractional frequency division value of frequency divider,

Wherein each frequency division value comprises selected integer and fractional part, and

Selected fractional part then is different from scope at one, and { 0, the scope of 1} is interior to be changed.

2. synthesizer as claimed in claim 1, wherein the scope of fractional part is roughly about { 0} symmetry.

3. synthesizer as claimed in claim 1, the scope of wherein selected fractional part greater than 0.5,0.5}.

4. frequency synthesizer comprises:

One phase-locked loop, described phase-locked loop comprise a programmable frequency divider and

One frequency divider control device, it provides a signal to carry out fractional frequency division to frequency divider, therefore produces a needed output frequency from ring;

Wherein control device comprises at least one digital modulator, it has an adder, a latch and an output logic level between input and output that are connected adder, described output logic level one or more by the position of adder output on the actuating logic operation.

5. synthesizer according to claim 4, wherein,

From the signal of control device comprise the decimal control signal that produces by a digital modulator and an integer control signal and

Corresponding to the decimal control signal, described frequency divider is carried out a scaling-down process, and its generation has the branch frequency of fractional part, described fractional part be selected from and be different from 0, in the scope of 1}.

6. synthesizer as claimed in claim 4, wherein

Described digital modulator comprises a feedback logic level, actuating logic operation on its one or more in the output of adder.

7. synthesizer as claimed in claim 6, wherein:

Described latch is connected in the output and feedback logic level of adder, to produce the input of adder.

8. frequency synthesizer, it comprises

One phase locking unit, described phase locking unit comprise a programmable frequency divider and

One frequency divider control device, it provides a signal to frequency divider, carrying out fractional frequency division, and produces a required output frequency from loop thus,

Wherein said control device comprises at least one digital modulator, and described modulator has an adder, latch and feedback logic level between the output of adder and input, its actuating logic operation on adder output one or more.

9. synthesizer according to claim 8, wherein

The operation of being carried out by the feedback logic level comprises the signal that dither is drawn by standard-random sequence by the one or more adder outputs of multiplexing.

10. synthesizer according to Claim 8, wherein:

Described digital modulator comprises an output logic level, and they are the actuating logic operation in the one or more outputs of adder.

11. synthesizer according to claim 9, wherein

Described output logic level provides a decimal control signal to frequency divider, producing a frequency division value that fractional part arranged, described fractional part be selected from and be different from 0, the scope of 1}.

12. synthesizer according to claim 8, wherein

Described latch is connected in the output and feedback logic level of adder, to produce the input signal of adder.

13. a digital modulator, it comprises:

One adder, it receives control signal and feedback signal as input, and by adding output, produces multidigit output

One output logic level, it receives the input that at least one position draws from the output of adder, and carries out logical operation in described input, with produce the modulator output signal and

One feedback path, it comprises from the output of adder and receives at least one group of position to produce the latch of feedback signal.

14. modulator as claimed in claim 13, wherein,

Described feedback path comprises a feedback logic level, and it receives at least one input that draws from the output of adder, and actuating logic operation in described input, and to produce an output, described output is used to draw to the small part feedback signal.

15. modulator as claimed in claim 13, wherein,

Described feedback path comprises a second adder, and it receives at least one input and from the input of at least one corresponding positions of feedback logic level from output of first adder, and produces an output, and described output forms the part of feedback signal.

16. modulator as claimed in claim 13, wherein

Described latch receive adder output at least one position and the input that draws from the output of feedback logic level, and produce the feedback signal of adder input.

17. modulator as claimed in claim 13, wherein, described output logic level is as multi-level quantiser.

18. modulator as claimed in claim 14, wherein

Described feedback logic level combines a high-frequency vibration signal and the output signal that receives from adder.

19. a modem devices, it comprises:

Two or more modulators, each modulator all has an adder, and one is connected a latch and the output logic level between the input and output of adder,

Wherein said modulator connects like this, and the output of the latch in each modulator is coupled to next modulator, if having, the input of adder on, and

The output of the logic level in each modulator is coupled to a public combination stage, to produce an output that is used for modem devices.

20. modem devices according to claim 19, wherein

At least two output logic levels have the digital output stage of varying number, and the passing ratio element is connected on the combination stage.

21. modem devices according to claim 19, wherein

The adder of at least two continuous modulators has different length, and the latch passing ratio element of first modulator connects in the input of second modulator.

22. modem devices according to claim 19, wherein

The output of the logic level of each modulator is connected on the described combination stage by one or more delay elements.

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