CN1238893C - Method for proving program with fast program - Google Patents

Abstract

The present invention describes a novel method of program-to-program verification, namely that the critical voltage of memory units is converted and is measured by charging and discharging a minimum bit line and a control gate line. A capacitor from the bit line to the control gate line can also be used for lowering a required reference voltage, and a programming current is lowered by coupling a load assembly to a source diffusion region. Thus, program frequency bandwidth is increased, and the current consumption of a high voltage charging pump is reduced to increase programming.

Description

Method for programming and programs device

Technical field

The present invention is relevant for a kind of semiconductor non-volatility memorizer, and particularly relevant for the sequencing and the proving program operation of a kind of pair of MONOS flash memory.

Background technology

In the MONOS flash memory component, data is that the form with electronics is stored in the nitride region of oxide/nitride/oxide (ONO) composite bed under the control grid, there is the critical value that can increase assembly in electronics in nitride region, clearing cell that stores logical one has several in nitride region or does not have the electronics that stores, the unit of sequencing that stores logical zero then has fixed range in nitride region a electronics.In the MONOS memory of commonly using, in order to control the electron number in the nitride region, the operation meeting of program is interrupted because of the program verification circulation, the view of the procedure operation with program verification is commonly used in demonstration as Fig. 1, in first program is set up, 101 beginning activating charge pumps and the required voltage of creation facilities program (CFP) operation; During program pulse step 102, the memory cell of having chosen is subjected to programm voltage; After a certain hour, in program verification step 103, the critical value of test memory cells; If when the critical value of memory cell was higher than the critical reference value, then memory cell was considered as finishing sequencing, and program is finished 104 steps; Otherwise if chosen memory cell when enough not high, then memory cell is got back to program state 102.

Fig. 2 a proposes a kind of MONOS memory cell of commonly using program and knows the voltage status case, and the program verification that Fig. 2 b proposition is commonly used, memory cell is by a control grid 202, an one source pole 201 and a drain 203 are formed, in the nitride region 204 of electron storage under control grid 202, it should be noted that, wherein shown voltage is only for signal, actual voltage is different according to specification, such as program speed, oxide thickness, and the size of memory cell, because channel hot electron (channel hot electron, CHE) ejaculation program, the voltage of an about 10V puts on the control grid 202, and the high voltage of another about 5V puts on the drain 203 and with source electrode 201 ground connection.

Consult Fig. 2 b, proving programization is very similar to a read operation, because will measure diffusion region,, control grid 202 bias voltages are become about 2V, drain 201 bias voltages are become about 1V, reach source electrode 203 bias voltages are become 0V with the state of decision memory relevant for a reference voltage.

When having a transition region between program is to the program verification program state, must exchange source electrode and drain, and the voltage of drain 203 dropped to 0V by 5V, if need to carry out another program cycle, then drain 203 need rise to 5V again, the use of electric charge is very inefficent thus, because the drain voltage between the extra electric current of needs improves and the program that is reduced in circulates to program verification, when the drain of many memory cells is connected to single high capacitance bit line, the program that can be increased in is to the transit time between the program verification circulation, can increase the transit time of this increase and increases the whole procedure operating time.

Fig. 3 demonstration is described in United States Patent (USP) the 6th, 011, the two MONOS storage arrangements (being referred to as NROM) that store of a located by prior art of No. 725 (Eitan), two memory storage districts 304 and 305 are wherein arranged in a memory cell, and point to the read method of a kind of being called " reverse reading ", in the close diffusion region 303 of having chosen memory storage district 305, become lower voltage or source electrode, and with respect to the diffusion region 301 of choosing memory storage district 305, then become higher voltage or drain, if in height critical " 0 " memory state, in order in substrate, to set up an exhaustion region, drain voltage is higher than source voltage, and therefore stride across and to be stored in the electric charge that is not selected in the storing memory storage area, the kind of this NROM memory cell can only be operated under reverse read mode, be owing to do not need a higher voltage not to be selected memory channel in the memory storage district being selected to stride across, if this assembly is desired to read with the direction of forward, then higher drain voltage can stride across has chosen the memory storage district, and this unit will can sensedly be always low Vt " 1 " and memory state.

Another located by prior art is two to store the MONOS component description in the U. S. application case of application on October 25th, 1999 number the 09/426th, No. 692, be referred to as two MONOS unit and be shown among Fig. 4 a, in the memory cell of this kind, except a word gate 402 and two diffusion regions 401 and 403 are arranged, more include two extra sidewall polycrystalline silicon control grid structures 406 and 407, different with the control grid 302 of Fig. 3 is, word gate 402 at Fig. 4 a does not have memory nitride storage area at it down, the memory storage district places under sidewall polycrystalline silicon control grid structure gate 406 and 407 on the contrary, shown in Fig. 4 a, two sidewall polycrystalline silicon control grids between two adjacent memory cells, in the mode that electrically connects, to define the control grid of an equivalence, because extra control grid 406 and 407 provides another selection, two MONOS unit, and two MONOS unit can be easily be read in two modes of reverse and forward, the voltage (Vcg override) of some increment on by the voltage that increases control grid to the highest possibility critical voltage, and can increase the channel bottom of not choosing nitride region.Though two MONOS unit can two-way mode read, because lower cell current, less critical boundary, and limited voltage range, the read performance that forward reads is lower.Fig. 4 b shows that drain voltage is to choosing the critical graph of a relation in nitrogenize district, and memory nitride channel length is greater than 50nm and less than 50nm, can be found to, during forward reads, high Vt unit (" 0 ") on higher drain-source voltage can be subjected to critical decline, this kind effect can be more obvious because of short channel length, therefore keeps the low about 0.3-0.5V of voltage of drain between sensitive period, to keep rational critical boundary between " 1 " and " 0 " unit as far as possible.

Fig. 4 c is the schematic diagram in the two MONOS cell array of diffusion in the bit architecture, each memory cell by a word gate, two control grid one side of something (half), be positioned at mononitride storage area and two diffusion region one side of something under each control grid one side of something.In this array, memory cell is arranged in rows into row, wherein the word gate is with word line WL[0-1] flatly link together, and the diffusion region, position is with bit line BL[0-3] vertically link together, and control grid is with control line CG[0-3] vertically link together, control line CG[0-3] and bit line BL[0-3] can pass from top each other, and have one about 30% coupling capacitance.

In high frequency range program is used, hope can be parallel to many memory cell sequencing, if many bit lines and control line need to be recharged between program is to the program verification circulation and discharge, then required voltage and the electric current of charge pump and voltage regulator will be very high, influences power and whole sequencing time.Especially in the multilayer storing memory, in order between critical condition, to have strict control, can improve the number of times of program usually, so this hope makes in program the voltage-transition between the program verification is dropped to minimum to the program verification circulation.

Summary of the invention

A main purpose of the present invention is to provide the low-power methods of the two storage areas of a kind of sequencing MONOS memory cell.

Another object of the present invention is to provide the program verification method of a kind of pair of storage area MONOS memory cell.

Another purpose of the present invention is that the program that is provided at is to the effective conversion between the program verification operation.

Another purpose of the present invention is by the charge and discharge that reduces diffusion position line, and makes program reduce to minimum to the transition between the program verification.

Another purpose of the present invention is by the charge and discharge that reduces control grid voltage, and makes program reduce to minimum to the transition between the program verification.

Another purpose of the present invention is to make program that the required reference voltage quantity of program verification is reduced to minimum.

Another purpose of the present invention is the program verification of using forward to read.

Another purpose of the present invention is to use reverse program verification of reading.

Another purpose of the present invention is used capacitive coupling between control sluice polar curve and bit line, by making the voltage that puts on control sluice polar curve and bit line reduce to minimum, to obtain a critical voltage.

Another purpose of the present invention avoids being subjected to program disturb in the adjacent unit of protection.

Another purpose of the present invention is by connecting a load transistor to source diffusion region, with the control program cell current.

Another purpose of the present invention is to keep and reaches the control grid voltage of same program to program verification.

According to the present invention, the method for a kind of sequencing a pair of storage area MONOS memory cell is provided, comprising:

A) a drain diffusion region bias voltage is become one first high voltage;

B) with one source pole diffusion region bias voltage ground connection;

C) be not selected the control grid bias voltage with one and become one second high voltage;

D) choose the control grid bias voltage with one and become one the 3rd high voltage;

E) a word gate bias voltage is become one first low-voltage; And

F) one of an adjacent cells is not selected the diffusion region bias voltage and becomes one greater than 0 volt second low-voltage.

According to the present invention, the programs device of a kind of pair of storage area MONOS memory cell also is provided, comprising:

A) a kind of so as to the device of bias voltage one word gate with the limits storage cell current;

B) a kind of so as to bias voltage one first control grid bias voltage to cross over the device that one under this first control grid is not selected the storage area critical voltage;

C) a kind of so as to being coupled to the device of a load component;

D) a kind ofly one chosen storage location to spray electronics under this second control grid so as to bias voltage one second control grid; And

E) a kind of so as to being suppressed at the device that an adjacent cells one is not selected the disturbance state in the diffusion region.

In the present invention, a kind of program of two MONOS memory assemblies of making is described to the fast switch over method between the program verification, to be become a low-voltage by the unit word gate bias voltage of sequencing, with the limits storage cell current is several micromicroamperes (μ A), drain diffusion region bias voltage becomes a high voltage, and with source diffusion ground connection, the drain diffusion region is close by the diffusion region of sequencing storage area in two storage areas assembly, the storage area then is a nitride region below control grid, in two storage areas device, two control grids and two nitride regions that separate are arranged, the control grid bias voltage of not choosing becomes a high voltage, to stride across the highest possibility critical voltage that is positioned at the memory storage district that is not selected under the control grid, chosen control grid for being positioned at the top, storage area, desire by the control grid of sequencing, and in order to allow electrospray to the nitride storage area and bias voltage becomes a high voltage, source diffusion region is connected to a load component, with the restriction and the control unit electric current, and cell current with a low word gate voltage Be Controlled.In order to control the program disturb of adjacent cells; not not the choosing diffusion region voltage and can improve a little of adjacent cells; improve the voltage of not choosing adjacent diffusion region and can reduce the voltage of gate, can increase the critical voltage of adjacent storage area simultaneously, and protected location avoids program disturb to source electrode.

In order to want a sequencing memory cell of the present invention, need a program verification operation, to whether have been reached an enough sequencing voltage by the unit of sequencing with decision, in order to reach this purpose, the rarest transducer of operating from procedure operation to a program verification back and forth, during the sequencing of a unit, between operation, several transducers can be arranged, when inequality haply as if the voltage that comprises two operations, have considerable multiple connecting line charging and discharge, wherein can cause so formation time being postponed.In order to make the time delay between twice operation reduce to minimum, during both programs were to program verification, bit-line voltage and control grid voltage will be adjusted and become as far as possible as many.In addition, a program is used the direction of " forward reads " to the variation of program verification, low voltage put on relatively chosen on the diffusion region of nitride storage area, " forward reads " operation will provide the bit line of minimum and the charging and the discharge of control grid, when the channel length under nitride region reaches the critical voltage slippage than hour (shown in Fig. 4 b) for long, this kind read forward access method is the most effective, and wherein the critical voltage slippage is the function of drain-source voltage.

In order in a pair of MONOS memory cell, program verification one to have chosen nitride region, source electrode and the adjustment of drain bit line are equated to become a voltage, this voltage is the high drain voltage of half during sequencing, simultaneously, reduce the control grid voltage of having chosen a little, then word line is raise and become a high voltage, implement word gate channel to provide, at last, one of them reduces to a lower voltage with two bit lines, a sensing amplifier is connected to the bit line monitor, and another bit line is then with respect to a reference voltage; If this target nitride region is fully by sequencing, then will keep this voltage, otherwise will descend again, can be by selecting decline two bit lines or be connected to sensing amplifier, and make checking can forward and reverse dual mode carry out.

The present invention also mentions another program technic, wherein carry out program by the electric capacity that utilizes BL, because the high ejection efficiency of channel hot electron (CHE) program of two MONOS memories, be stored in electric charge on the high voltage drain end member line capacitance by utilization, can be in a short time efficiently finish sequencing, in order to increase threshold voltage ranges,, and carry out proving programization by coupling capacitance between the electric capacity that utilizes BL and bit line and control sluice polar curve.At first, suitable voltage puts on control sluice polar curve and bit line in order to sequencing, then control sluice polar curve and bit line are suspended, and word line will be risen to a lower voltage with the limiting program electric current, when opening word line, then open all channels between source electrode and drain, to such an extent as to electric current will flowing between two bit lines.Yet the low-voltage of word line is the voltage of limits source bit line also, when the voltage of drain end bit line descends above some, stops electrospray.In order to want the sequencing checking, word line will rise to a high voltage, so that two bit line adjustment are equal to a medium voltate.Afterwards, the most close bit line of having chosen nitride region will drop to a lower voltage, the critical value of verification operation is deducted low bit line voltage and is determined it by the control grid voltage of choosing end, the voltage of phase pairs of bit line can monitor out, whether chosen nitride region fully by sequencing with decision, so that keeping bit-line voltage, is to be unlikely to descend.

The program among the present invention of being described in also can be applicable on the high program frequency range that how critical level stores in the single nitride region the result of program verification.

Description of drawings

The present invention will be described by following conjunction with figs., wherein:

Fig. 1 is a kind of located by prior art method that is used for program to program verification one non-volatile memory unit.

Fig. 2 a is the schematic diagram of located by prior art one MONOS unit, the voltage of display routineization.

Fig. 2 b is the schematic diagram of located by prior art one MONOS unit, the voltage of display routine checking.

Fig. 3 is the schematic diagram of the two MONOS of storage of located by prior art unit.

Fig. 4 a is the schematic diagram that located by prior art has two MONOS of storage unit of two control grids.

Fig. 4 b is the chart that concerns between the critical voltage of two MONOS of storage unit of located by prior art with two control grids and the drain-source voltage.

Fig. 4 c is the schematic diagram of an array of two the store MONOSs unit of located by prior art with two control grids.

Fig. 5 a is the schematic diagram that a pair of of the present invention stores the MONOS unit, shows the voltage of first embodiment procedure operation.

Fig. 5 b is the schematic diagram that a pair of of the present invention stores the MONOS unit to Fig. 5 d, shows the voltage of first embodiment program verification operation.

Fig. 6 is the analog result schematic diagram of first embodiment program to program verification method.

Fig. 7 is the schematic diagram of two MONOS of storage of the present invention unit, shows the voltage of second embodiment program verification operation.

Fig. 8 a is the schematic diagram that a pair of of the present invention stores the MONOS unit to Fig. 8 b, shows the voltage of the 3rd embodiment procedure operation.

Fig. 8 c is the schematic diagram that a pair of of the present invention stores the MONOS unit to Fig. 8 d, shows the voltage of the 3rd embodiment program verification operation.

Fig. 9 is the analog result schematic diagram of the 3rd embodiment program to program verification method.

Figure 10 is the schematic diagram of of the present invention two adjacent two MONOS of storage unit.

Figure number is to as directed:

201 source electrodes

202 control grids

203 drains

204 nitride regions

301 diffusion regions

302 control grids

303 diffusion regions

304 memory storage districts

305 have chosen the memory storage district

Diffusion region, 401 left side

402 word gates

403 right diffusion regions

404 nitride storage areas

405 nitride storage areas

406 control grids

407 control grids

410 memory cells

BLL 401 left bit lines

WL 402 word gates

BLR 403 right bit lines

CGL 406 left control grids

CGL 407 right control grids

503 word gates

601 left memory cells

602 right memory cells

605 high voltage diffusion regions

606 are not selected adjacent diffusion region

607 right memory storage districts

608 have chosen the memory storage district

609 memory storage districts

610 right memory storage districts

Embodiment

According to the memory unit among Fig. 4 a, Fig. 5 a to Fig. 5 d shows the U.S. patent application case number the 09/426th of application on October 25th, 1999, No. 692, situation relevant for the sequencing and the checking of two MONOS memory cells, memory cell 410 is by a word gate 402, one left diffusion region 401, one right diffusion region 403, two control grids 406 and 407, and two nitride storage areas 404 and 405 compositions, nitride storage area, a left side 404 is positioned at the below of left control grid 406, the top of diffusion region 401, a left side, and near word gate 402, and right nitride storage area 405 is positioned at the below of right control grid 407, the top of right diffusion region 403, and near word gate 402.

It should be noted that, shown sequencing state is starkly lower than the MONOS component programs voltage of commonly using, the difference of this voltage is because the relation of the reinforcement electronics injection device in two MONOS assembly, yet, also it should be noted that, shown voltage only is approximation, and actual voltage needs to be determined by processing procedure and product specification parameter, such as the thickness of threshold variations, oxide and ONO, dopant profiles, and program and checkout time specification.Suppose that the critical value under " a 0 " state is Vth＞2.0V, the critical value that the critical value under one state is about 0.5V and word gate 503 is 0.5V.

Memory profile according to Fig. 4 a, Fig. 5 a shows when the voltage status of the present invention of choosing right nitride storage area, in order to want right nitride storage area 405 sequencing of sequencing, an about 5V drain applies for passing through memory cell to source voltage, for CHE injects, the most close diffusion region 403 of having chosen the storage area becomes drain, among two diffusion regions 401 and 403, right diffusion region 403 has the highest drain electrode of about 5V, left diffusion region 401 then becomes the source electrode of about 0V, the low word gate voltage limiting program cell current of an about 1V, left side control grid 406 bias voltages become the high voltage of an about 5V, do not choosing the possible critical condition in memory storage district 404 to stride across one, though low left control grid voltage that procedure operation still may be a 3V when being about 2.0V as if the target program critical value, select be used in program verification during stride across the identical 5V high voltage of voltage, to reduce in program the transit time between the program verification pattern, right control grid 407 bias voltages become 5V.

Fig. 5 b is provided at the voltage status of program to the transition period between the program verification pattern, when between program is to the program verification pattern, switching, high control grid voltage need not to discharge becomes the low-voltage of a normal read operation, can save the charge pump utmost point mode switch time.On the contrary, control grid 406 remains near the 5V, make source diffusion region 401 and drain diffusion region 403 be equal to 2.5V, it is half of high drain voltage when being used for sequencing, simultaneously when considering the substrate effect, the voltage of right control grid 407 changes becomes Vcg_pv, when target critical during for 2V its Vcg_pv be about 4V.When the voltage of a left side and right diffusion region 401 and 403 had been set at 2.5V, two diffusion regions that then suspend were shown in the 5th figure.For the disintegration voltage that will make 2.5V passes through easily, word gate 402 is elevated to the high voltage of about 4V then, and this also may equate the adjustment of word line bias voltage simultaneously with the bit line of wanting bias voltage.Program verification result's final step is shown in 5d figure, and the voltage of right diffusion region 403 drops to Vbl_pv, is about 1.8V and monitors the voltage of left diffusion region 401.If the critical value of right nitride region 405 is higher than target 2.0V, the voltage of then left diffusion region 401 will maintain 2.5V, otherwise, if critical value is lower than 2.0V, the voltage of then left diffusion region 401 will descend, because two lower diffusion region voltages are with choosing the same same side in nitrogenize district, so read direction is reverse reading.The critical voltage of target programization by Vcg_pv and Vbl_pv voltage determined, Vtarget_threshold ≈ Vcg_pv-Vbl_p wherein, and source electrode-substrate voltage of considering non-zero can make substrate effect composition have influence on V target-critical value.

Fig. 6 is the analog result that is described in Fig. 5 a program verification of first embodiment in Fig. 5 d, its voltage curve that shows left control grid CGL406, right control grid CGL407, word gate WL402, left bit line BLL401 and right bit line BLR403 shows the effect of the critical voltage of left bit line BLL401 to time relation figure among the figure.

In second embodiment of the present invention, the direction that program verification can forward be read is carried out, be shown in Fig. 5 a to the program of Fig. 5 c and checking result for identical, yet, in the end in step, the voltage status of Fig. 7 can be replaced by the voltage of Fig. 5 d, in forward reads, with commutative in comparison source electrode and drain diffusion region during reverse the reading.From choosing the voltage that nitride region 405 left diffusion region 401 voltages farthest drop to a Vbl_pv, the prison side is near right diffusion region 403 voltages of choosing nitride region 405, with the decision critical value, be higher than 2.0V if chosen the critical value of nitride region 405, then will keep the voltage of right diffusion region 403.In forward reads, the value that critical voltage descends is the function of drain-source voltage, therefore it is very important drain being maintained 0.3 to 0.5V to source voltage, in order to verify the targets threshold of a 2.0V, Vcg_pv should for 2.0V greater than Vbl_pv (voltage that adds some extra substrate effects is calculated).

In the 3rd embodiment of the present invention, the process of program is shown among Fig. 8 a to Fig. 8 b, and program verification the results are shown among Fig. 8 c to Fig. 8 d.

Fig. 8 a provides the voltage status for the right nitrogenize district 405 that wants the two MONOS memory cells of sequencing Fig. 4 a, left side control grid 406 bias voltages become a leap voltage that is about 5V, what right control grid 407 bias voltages became an about 5V chooses programm voltage, with left diffusion region 401 ground connection, and the high drain voltage that becomes an about 5V is improved in right diffusion region 403, be connected respectively to diffusion region 401 and 403 at bit line and control sluice polar curve, and the control grid 406 and 407 of having chosen memory cell has been set at after its suitable voltage, they separate with its voltage supply and are what suspend, when electronics begins to move to the drain bit line by source bit line, the word line that is connected to word gate 402 raises and start programization then, the high CHE of the two MONOS unit of the present invention injects usefulness, use is stored in the energy of high drain voltage bit line, and provide effective sequencing, and need not actual source electrode and the bias voltage DC of drain, word line voltage also can the agretope equalization scope, because source bit line will can not improve the critical voltage that deducts the word gate above word line voltage, it is about 00.5V.Therefore, bring up to 0.5V in source bit line, and after the drain bit line reduces to 4.5V, electric charge will no longer move between two bit lines, and CHE injects and will stop, the variation of bit-line voltage also can have influence on the voltage of two Suspension Control gate lines, if we suppose that bit line is 30% to the coupling efficiency of control sluice polar curve, then a 0.5V bit-line voltage variation will cause 0.15*3=0.15V control sluice polar curve change in voltage, and bit line and control grid voltage are shown in Fig. 8 b after shut down procedureization.

In Fig. 8 c, in order to make a left side and right bit line to a 2.5V all wait until a medium voltate that is about 2.5V, word gate 402 voltages are brought up to the high voltage of an about 4V, and suspend then, simultaneously, bit line can be incorporated into 2.5V, rises to 5.75C such as the capacity coupled control grid voltage of left control grid 406, and right control grid 407 drops to 4.25V, and the voltage of this right control grid 407 equals the Vcg_pv among first embodiment of the present invention.

Shown in Fig. 8 d, when the voltage of right diffusion region 403 drops to Vbl_pv, this may determine to have chosen the nitrogenize district and whether is higher than target critical voltage Vtarget_threshold (wherein Vtarget_threshold ≈ Vcg_pv-Vbl_pv) then, be connected to left diffusion region 404 by the monitoring bit line, if keep certain voltage or be kept above a certain voltage, then sequencing is just enough, otherwise the voltage of left diffusion region 404 will descend.

The 3rd the embodiment advantage good than first embodiment be, Vcg_pv need not be added on outward on the memory cell, and on the contrary, it can and utilize the capacitive coupling between bit line and control sluice polar curve and obtain by the time series of uniqueness.

The program verification result's of the 3rd embodiment analog result among Fig. 9 displayed map 8a to Fig. 8 d, its voltage curve that shows left control grid CGL406, right control grid CGR407, word gate WL402, left bit line BLL401 and right bit line BLR403 shows the effect of the critical voltage of left bit line BLL401 and left control grid 406 to time relation figure among the figure.

The high program frequency range that many critical layers stored during first and the 3rd embodiment of the present invention can be applicable in single nitride region is used, by the formula of using Vtarget_threshold ≈ Vcg_pv-Vbl_pv, the critical value of can strict control wanting (noting: also need to consider) because the substrate effect of source electrode-substrate bias, according to the simulation data of Fig. 6 and Fig. 9, can determine by setting Vcg_pv, Vbl-pv or both less than the critical voltage increment of 0.1V.

At first, among second and the 3rd embodiment, during the program verification sequence, also may use another transistor and equal equipotential line, its transistor can be connected between a left side and the right bit line, phase of equality at any time and deactivate during, this transistorized gate can be activated.

At first, among second and the 3rd embodiment, by setting Vcg_pv-Vbl_pv＞Vtarget_threshold, and can shorten the program verification time, both will not descend by the bit line of fully sequencing and by the bit-line voltage of fully sequencing, yet, borrow bit-line voltage is likened to reference voltage or reference unit, might distinguish both of these case.If bit line decline still is kept above reference voltage in a known time interval, then this unit is promptly fully by sequencing.

In another embodiment of the present invention; during sequencing; by the voltage that improves the relative diffusion district a little; and can protect adjacent cells in order to avoid be subjected to program disturb; the 10th figure is the profile that shows two adjacent memory cells 601 and 602; when memory storage district 608 has been chosen will be by sequencing the time in the right side of left unit 601; adjacent memory storage district 609 in adjacent cells 602 (sharing same high voltage control grid and high voltage diffusion region 605) will be among the danger of program disturb.If right relatively memory storage district 610 in right sided cell storage area 602 has a negative critical value, then this adjacent right unit 602 may conduction current, and therefore, sequencing is not selected the memory storage district 609 of adjacent cells.Not to be selected neighbor memory cell and to deposit storage area 609 and avoid being subjected to program disturb in order to protect; this is not selected the summary high voltage that adjacent diffusion region 606 bias voltages become an about 1V; improving the voltage that is not selected adjacent diffusion region 606 can effectively increase the critical value in memory storage district 610; and promote the source voltage of this unit, and it is important that diffusion region voltage or program disturb that this can be too not high can be transmitted to adjacent cells 601.In another embodiment of the present invention, in the time of during sequencing, by connecting a current loading transistor to left source diffusion region 401, with the electric current of writable control storage.

Though the present invention represented especially, and does explanation with reference to its preferred embodiment, only on the various forms and the change of details in not deviating under spirit of the present invention and the category for it, for the personage who has the knack of present technique can understand.

Claims (11)

1. the method for a sequencing a pair of storage area MONOS memory cell comprises:

A) a drain diffusion region bias voltage is become one first high voltage;

B) with one source pole diffusion region bias voltage ground connection;

C) be not selected the control grid bias voltage with one and become one second high voltage;

D) choose the control grid bias voltage with one and become one the 3rd high voltage;

E) a word gate bias voltage is become one first low-voltage; And

F) one of an adjacent cells is not selected the diffusion region bias voltage and becomes one greater than 0 volt second low-voltage.

2. the method for claim 1 is characterized in that, this source diffusion region is connected to a load component with the restriction electric current.

3. the method for claim 1 is characterized in that, this word gate bias voltage is become a low-voltage, the limits storage cell current.

4. method as claimed in claim 3 is characterized in that, this word gate bias voltage is become a low-voltage, and the electric current of limits storage unit is in several micromicroamperes.

5. the method for claim 1 is characterized in that, this control grid bias voltage that is not selected is become this second high voltage, strides across one and is positioned at the highest possibility critical value that this is not selected the memory storage district under the control grid.

6. the method for claim 1 is characterized in that, this control grid bias voltage of having chosen is become the 3rd high voltage, promotes electrospray to choose memory storage district under the control grid to being positioned at this.

7. the method for claim 1, it is characterized in that, this drain diffusion region bias voltage is become first high voltage and the control grid bias voltage that this has been chosen is become one the 3rd high voltage, can cause the disturbance state of this adjacent cells, can become this second low-voltage by the diffusion region bias voltage that is not selected, to suppress adjacent cells with this adjacent cells.

8. the programs device of two storage areas MONOS memory cell comprises:

A) a kind of so as to the device of bias voltage one word gate with the limits storage cell current;

B) a kind of so as to bias voltage one first control grid bias voltage to cross over the device that one under this first control grid is not selected the storage area critical voltage;

C) a kind of so as to being coupled to the device of a load component;

D) a kind ofly one chosen storage location to spray electronics under this second control grid so as to bias voltage one second control grid; And

E) a kind of so as to being suppressed at the device that an adjacent cells one is not selected the disturbance state in the diffusion region.

9. programs device as claimed in claim 8 is characterized in that, so as to bias voltage one word gate this device with the limits storage cell current, uses a low-voltage cell current is controlled at several micromicroamperes.

10. programs device as claimed in claim 8 is characterized in that, so as to being coupled to this device of a load component, the restriction electric current flows.

11. programs device as claimed in claim 8 is characterized in that, so as to being suppressed at this device that an adjacent cells one is not selected the disturbance state in the diffusion region, increasing by a voltage and is coupled to this and is not selected the diffusion region.

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