CN1230021A - Manufacturing method of memory cell array - Google Patents

Abstract

A method for manufacturing memory cell array includes such steps as forming multiple channels and a transistor on semiconductor substrate, depositing the first insulating layer to fill the channels to form multiple insulating plugs, depositing the second insulating layer to form an opening to expose the semiconductor substrate and the corner of one of the insulating plugs, etching the corner to form a recess, depositing a doped polysilicon layer in the recess, depositing a conducting layer to fill the recess, etching to form a conducting plug, forming the third insulating layer on the conducting plug and its periphery to form buried bit line, and annealing to diffuse impurities in source/drain region and doped polysilicon layer for contacting.

Description

Manufacturing method of memory cell array

The present invention relates to a method for manufacturing a memory cell array (Memory Cell Array), in particular to a method for manufacturing a memory cell array with a buried bit line (Buried Bit Line). The buried bit line can be self-aligned to the transfer transistor (Transistor) in the memory cell array without occupying additional space, and can be applied to manufacture a high-density (High Density) memory cell array.

Improving device performance (Performance) and reducing manufacturing process costs are the development directions of semiconductor manufacturing processes. These goals have been successfully achieved in sub-micron (Sub-Micron) or micro-miniaturization (Micro-Miniaturization) manufacturing processes. If it is necessary to develop to a smaller scale (Features) manufacturing process, the capacitance quality in the device will be destroyed, and the resistance effect will become obvious, which will reduce the performance of the device. And due to the reduction of the scale, the size of the chip (Chip) will also become smaller, so that the integration level will be increased and the manufacturing cost of individual chips will be reduced.

It is very important in the manufacturing process of the reduced-scale dynamic random access memory (Dynamic Random Access Memory; DRAM) element. A DRAM memory cell usually has a stacked capacitor structure, and the stacked capacitor is located above the source (Source) or drain (Drain) region of the transfer transistor. As for the bit line in the DRAM memory cell, it includes a metal line extending along an insulating layer, and the insulating layer communicates with the source or drain region through a contact hole. An existing method for reducing the area of bit lines in DRAM memory cells is to use the concept of buried bit lines. For example, US Patent Nos. 5,250,457 and 5,364,808 both propose a method for manufacturing buried bit lines in transfer transistors. However, the buried bit lines in the above-mentioned inventions will increase the bit line connection (Bit Line Coupling) on the silicon substrate. If the source/drain region is insulated from the silicon substrate, there will be no defects (Defect), and the manufacturing Its yield (Yield) is difficult to control.

In view of this, the main purpose of the present invention is to provide a method of fabricating a memory cell array, and in particular to a method of fabricating a memory cell array with buried bit lines. The bit line is buried in the insulating oxide layer, or in the shallow trench (Shallow Trench), or in the field oxide layer (FieldOxide Region). Therefore, the bit line does not occupy extra space, the density of the components can be increased, and the connection of the bit line is reduced, and the field oxide layer can be automatically isolated from the silicon substrate.

To achieve the above object, the present invention proposes a method for manufacturing a memory cell array, the steps of which at least include forming a plurality of beam grooves on a semiconductor substrate. Then a first insulating layer is deposited to fill up the plurality of trenches to form a plurality of insulating plugs. A second insulating layer is deposited on the semiconductor base, and a first opening is formed thereon to expose the semiconductor base and a corner of an insulating plug among the plurality of insulating plugs. Then the corner of the insulating plug is etched to form a groove, and a doped first polysilicon layer is deposited in the groove. Afterwards, a conductive layer is deposited to fill up the groove, and then a recess step is performed to form a conductive plug. A third insulating layer is formed on and around the conductive plug to form a buried bit line. A transfer transistor is formed on the semiconductor substrate, including a gate and source/drain regions. A tempering step is performed so that impurities in the source/drain regions and the doped first polysilicon layer are diffused into contact. A fourth insulating layer is deposited on each of the above layers, and a second opening is formed thereon to expose the source/drain region. forming a second polysilicon layer on the periphery of the second opening to fill the second opening, forming a lower electrode, forming a dielectric layer on the lower electrode, and depositing a third polysilicon layer on the dielectric layer, used to form an upper electrode. Then the lower electrode, the dielectric layer and the upper electrode form a stack capacitor structure.

In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given and described in detail with accompanying drawings. In the attached picture:

FIG. 1 shows a schematic top view of a memory cell array according to a preferred embodiment of the present invention;

Figures 2 to 7a show schematic cross-sectional views of a memory cell array manufacturing process along line AA' in Figure 1 according to a preferred embodiment of the present invention;

FIG. 7b shows a schematic cross-sectional view of a manufacturing step of a memory cell array along line BB' in FIG. 1 according to a preferred embodiment of the present invention; and

FIG. 8 and FIG. 9 are cross-sectional schematic diagrams illustrating manufacturing steps of a stack capacitor in a memory cell array according to a preferred embodiment of the present invention.

The invention proposes a manufacturing method of a memory cell array, in which a stacked capacitor structure covers a buried bit line. The buried bit line can be in the field oxide layer, or in the insulating shallow trench, or in other insulating oxide layers, which can solve the problem that the existing bit line occupies too much space. In addition, this buried bit line structure has the function of automatically aligning the source/drain regions of the adjacent transfer transistors. Through the outdiffusion of impurities in the bit lines and source/drain regions, it can naturally Ground connects the source/drain regions in the transfer transistor and the buried bit line together.

First, please refer to FIG. 1 , which shows a schematic top view of a memory cell array according to a preferred embodiment of the present invention. A plurality of shallow trenches 12 have been filled with insulating material for insulation and isolation. The exposed areas of the semiconductor substrate 10 are distributed around the plurality of shallow trenches 12 . A buried bit line 17, indicated by a dashed line in FIG. In addition, an opening 14 is used as a via, where a stack capacitor 15 can be formed.

Next, please refer to FIG. 2 , which shows a schematic cross-sectional view of manufacturing steps of a memory cell array along line AA' in FIG. 1 according to a preferred embodiment of the present invention. A semiconductor substrate 10 is provided, cut along a crystal plane 100 of single crystal silicon, and a thin oxide layer (not shown) is formed thereon. Then, on the semiconductor substrate 10 , a plurality of trenches 12 are formed by using anisotropic reactive ion etching method (Reactive IonEtch; RIE) with chlorine (Cl ₂ ) as an etchant. The depths of the plurality of trenches 12 are approximately between 4000 angstroms and approximately 6000 angstroms, and each trench 12 has an appropriate width and spacing according to the device design principles (DesignRules). Next, using low pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition; LPCVD), or plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition; PECVD), at a temperature between about 300°C and about 700°C, on the semiconductor substrate A first insulating layer 21 a , such as silicon oxide, is deposited on the 10 to fill up the plurality of trenches 12 , and the thickness of the first insulating layer 21 a is about two-thirds of the width of the plurality of trenches 12 . Then, using chemical mechanical polishing (CMP), or anisotropic reactive ion etching, using trifluoromethane (CHF3) as an etchant, etch and remove the redundant first insulating layer 21a outside the plurality of trenches 12 , forming a plurality of insulating plugs 21 .

Next, referring to FIG. 3, a second insulating layer 31 is formed with a thickness of about 500 angstroms to about 1000 angstroms by using low pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, or thermal oxidation (Thermal Oxidation). . Then, a photoresist layer 32 with a defined pattern is coated on the second insulating layer 31 . Using the photoresist layer 32 as a mask, an anisotropic reactive ion etching method is used, and trifluoromethane is used as an etchant to form an opening 33 on the second insulating layer 31, exposing part of the semiconductor substrate 10, and exposing more The corner (Corner) of an insulating plug 21 in the insulating plug 21. Continue to etch the insulating plug 21 to form a groove 34 in the trench 12, the depth of the groove 34 is between about 2500 angstroms and about 3500 angstroms. The photoresist layer 32 is then removed.

Next, referring to FIG. 4 , a thin first polysilicon layer 41 is deposited on the above layers, and the first polysilicon layer 41 is doped with impurities such as arsenic or phosphine. The method is to form it by low-pressure chemical vapor deposition at a temperature between about 550° C. and about 650° C., using silane as a reaction gas, doping arsenic and phosphorus ions at the same time. The doped first polysilicon layer 41 has a thickness between about 250 angstroms and about 350 angstroms. Then, at a temperature between about 600°C and about 800°C, using Tungsten Hexafluoride (Tungsten Hexafluoride) as a reactive gas, a conductive layer 42 is deposited on the first polysilicon layer 41 by a low-pressure chemical vapor deposition method, and Its thickness is between about 1500 Angstroms and about 2500 Angstroms. If the material of the conductive layer 42 is tungsten, before the conductive layer 42 is formed, a thin titanium nitride layer (Titanium Nitride) will be deposited as a barrier layer (Barrier Layer) (not shown) to prevent the first polycrystalline The silicon layer 41 is damaged. The material of the conductive layer 42 can also be tungsten silicide (Tungsten Silicide), which is formed by low-pressure chemical vapor deposition using tungsten hexafluoride and silane as reaction gases.

Next, please refer to Fig. 5, carry out the step of etching back (Etch Back) on above-mentioned each layer, utilize anisotropic reactive ion etching method, take chlorine gas as etchant, etch the first polysilicon layer 41 and conductive layer 42 , leaving the portion in the groove 34 , and then continue to perform the etching recess step (Recess) to between about 1000 angstroms and about 2000 angstroms below the surface of the semiconductor substrate 10 to form a conductive plug 51 . The thickness of the conductive plug 51 is about 1500 angstroms to about 2500 angstroms, and the conductive plug 51 is located at the corner of the insulating plug 21 .

Next, referring to FIG. 6, the second insulating layer 31 is removed, and a first insulating layer is deposited on the semiconductor substrate 10 at a temperature between about 300° C. and about 700° C. by using a low-pressure chemical vapor deposition method or a plasma-enhanced chemical vapor deposition method. The third insulating layer 61 has a thickness between about 2000 angstroms and about 3000 angstroms. Carry out dry etching (Dry Etching) step at the 3rd insulation layer 61 then, take trifluoromethane as etchant, stay the 3rd insulation layer 61 on the conductive plug 51 and the periphery, so the conductive plug 51 becomes a buried bit line .

Next, please refer to FIG. 7 b , which shows a schematic cross-sectional view of a manufacturing process of a memory cell array along line BB' in FIG. 1 according to a preferred embodiment of the present invention. First, grow a thin gate insulating layer 71 (Gate Insulator Layer), such as silicon dioxide, on the semiconductor substrate 10 at a temperature between about 850° C. and about 950° C. The thickness is between about 50 Angstroms and about 200 Angstroms. Then, at a temperature between about 550° C. and about 650° C., a gate 13, such as a polysilicon layer, is formed on the gate insulating layer 71 by using a low-pressure chemical vapor deposition method. The thickness of the gate 13 is about 2000 angstroms to about 4000 angstroms. Between Angles. Next, perform ion implantation (IonImplantation) on the gate 13, implant N-type ions, such as arsenic ions or phosphorus ions, the energy of which is between about 25KeV and about 100KeV, and the dose is about 1×10 ¹⁴ atoms/square centimeter to about Between about 1×10 ¹⁶ atoms/square centimeter. The environmental doping step (Situ Doping Procedure) can also be performed in an environment of mixing N-type ions, such as arsenic ions or phosphorus ions, and filling silane gas. The gate 13 is generally used as a word line, and is vertically arranged with the buried bit line 17 formed above (as shown in FIG. 1 ). Then, carry out the ion implantation method again, implant N-type ions, such as arsenic ions or phosphorus ions, on the semiconductor substrate 10 next to the gate 13 to form a lightly doped source/drain region 74, whose energy is about Between 30KeV and about 75KeV, the dose is between about 1×10 ¹² atoms/cm² and about 1×10 ¹⁴ atoms/cm². Next, deposit an oxide layer with a thickness of about 1500 angstroms to about 3000 angstroms on the gate 13 at a temperature between about 300° C. and about 700° C. by using a low-pressure chemical vapor deposition method or a plasma-enhanced chemical vapor deposition method. 74a. Then, an anisotropic reactive ion etching method is used to form a spacer 74 on the side of the gate 13 by using trifluoromethane as an etchant. Next, using the ion implantation method, N-type ions, such as arsenic ions or phosphorus ions, are implanted on the semiconductor substrate 10 next to the gate 13 to form a heavily doped source/drain region 75 with an energy of about 50KeV. To about 100 KeV, the dose is between about 1×10 ¹⁴ atoms/cm 2 to about 1×10 ¹⁶ atoms/cm 2 .

Next, please refer to FIG. 7 a , which shows a schematic cross-sectional view of a manufacturing process of a memory cell array along line AA' in FIG. 1 according to a preferred embodiment of the present invention. A lightly doped source/drain region 73, a heavily doped source/drain region 75, and a gate insulating layer 71 have been formed on the semiconductor substrate 10, and the above layers are not covered by the third insulating layer 61 . Then carry out a rapid thermal tempering (Rapid Thermal Anneal) step, the temperature is between about 950 ° C to about 1050 ° C, and the time is between about 10 seconds to about 60 seconds. Impurities in the heavily doped source/drain region 75 , the lightly doped source/drain region 73 and the doped first polysilicon layer 41 can gain energy and begin to diffuse to contact each other. Therefore, the positions of the doped first polysilicon layer 41, the heavily doped source/drain region 75 and the lightly doped source/drain region 73 will be automatically aligned, that is, the buried bit line 51 is self-aligned with the heavily doped source/drain region 75 and the lightly doped source/drain region 73. In this way, the alignment step of the subsequent photolithography manufacturing process (Photolithography) can be omitted, and there is no need to worry that the exposure alignment of the photolithography is not easy to control.

Next, referring to FIG. 8 , a fourth insulating layer 81 is deposited on the above-mentioned layers, and a second opening 14 is formed thereon, exposing lightly doped source/drain regions 73 and heavily doped source/drain regions. surface of the drain region 75 . The second opening 14 is formed by using an anisotropic reactive ion etching method, using trifluoromethane as an etchant, and the temperature is between about 300°C and about 500°C. Then, a second polysilicon layer 83a is formed on the periphery of the second opening 14 with a thickness of about 5000 angstroms to about 8000 angstroms by using a low pressure chemical vapor deposition method at a temperature between about 550°C and about 650°C. The second polysilicon layer 83a is used to fill up the second opening 14, and an ion implantation step is performed thereon, implanting N-type ions, such as arsenic ions or phosphorus ions, with an energy of about 25KeV to about 75KeV, and a dose of about Between 1×10 ¹⁶ atoms/cm² and about 5×10 ¹⁶ atoms/cm². Alternatively, the ambient doping step is performed in an environment filled with silane gas and mixed N-type ions, such as arsenic ions or phosphorus ions. Then photolithography and anisotropic reactive ion etching are used to pattern the second polysilicon layer 83 a by using chlorine gas as an etchant to form a lower storage electrode 83 .

Next, referring to FIG. 9 , a dielectric layer 91 is formed on the storage lower electrode 83 for insulation. The dielectric layer 91 can be formed by sputtering, using a material with a high dielectric constant (HihgDielectric Constant), such as an oxide of tantalum, preferably tantalum pentoxide (Ta ₂ O ₅ ), with a thickness of about Between 200 Angstroms and about 300 Angstroms. The dielectric layer 91 can also be deposited to form a silicon oxide/silicon nitride/silicon oxide layer (Oxidized/Silicon Nitride/Silicon Oxide; ONO) with a thickness of about 40 angstroms to about 80 angstroms. The method is to heat growing a silicon oxide layer with a thickness of about 10 angstroms to about 50 angstroms, then forming a silicon nitride layer with a thickness of about 10 angstroms to about 20 angstroms, and then performing a step of thermal oxidation, on the silicon nitride layer A silicon oxide layer is formed on it. Next, a third polysilicon layer 92a is deposited on the dielectric layer 91 by using a low pressure chemical vapor deposition method at a temperature between about 550°C and about 650°C. The thickness of the third polysilicon layer 92a is between about 2000 angstroms and about 3000 angstroms. Then, ions are doped on the third polysilicon layer 92a by performing an ambient doping step in an environment filled with silane gas and mixed phosphine gas. Then, photolithography and anisotropic reactive ion etching are used to pattern the third polysilicon layer 92 a by using chlorine gas as an etchant to form an upper electrode 92 . The above storage lower electrode 83 , dielectric layer 91 and upper electrode 92 form a structure of a stacked capacitor 15 .

In summary, although the present invention has been disclosed in conjunction with preferred embodiments, it is not intended to limit the present invention. Those skilled in the art can make various modifications and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be defined by the appended claims.

Claims (40)

1. the manufacture method of a memory cell array comprises the following steps: at least

(a) in the semiconductor substrate, form a plurality of trench;

(b) on this semiconductor-based end, form one first insulating barrier, in order to fill up this a plurality of trench;

(c) remove at suprabasil this first insulating barrier of this semiconductor, stay these a plurality of trench that fill up, form a plurality of insulating plugs;

(d) on this semiconductor-based end and these a plurality of insulating plugs, deposit one second insulating barrier;

(e) on this second insulating barrier, form one first opening, this semiconductor-based end of exposed portions serve, and the corner of exposing the insulating plug in these a plurality of insulating plugs;

(f) remove this first insulating barrier under this insulating plug corner, form a groove;

(g) on this second insulating barrier, this semiconductor-based end of part of exposing and this groove, form first polysilicon layer that mixes;

(h) deposition one conductive layer on first polysilicon layer of this doping, and this conductive layer fills up this groove;

(i) remove at first polysilicon layer of this conductive layer, this doping and this semiconductor-based end of part, stay first polysilicon layer of this conductive layer in this groove and this doping, form a conductive plug;

(j) on this conductive plug, carry out an etching notched step, in order to form a bit line;

(k) on this conductive plug, reach periphery and form one the 3rd insulating barrier, in order to bury this bit line;

(l) on this semiconductor-based end, form a gate insulator, and on this gate insulator, form a grid;

(m) form a lightly doped source/drain regions at this grid on this other semiconductor-based end, and this lightly doped source/drain regions is distributed in the zone between the 3rd insulating barrier and this a plurality of trench;

(n) form a clearance wall at this grid side;

(o) form a heavily doped source/drain regions at this clearance wall on this other semiconductor-based end, so this lightly doped source/drain regions, this heavily doped source/drain regions and this grid form a transfering transistor;

(p) carry out a tempering step, make impurity in first polysilicon layer of this heavily doped source/drain regions, this lightly doped source/drain regions and this doping to spread and contact;

(q) deposition one the 4th insulating barrier on above-mentioned each layer;

(r) form one second opening at the 4th insulating barrier, expose the surface of this lightly doped source/drain regions and this heavily doped source/drain regions;

(s) form one second polysilicon layer at this second opening periphery,, form a bottom electrode in order to fill up this second opening;

(t) on this bottom electrode, form a dielectric layer; And

(u) deposition one the 3rd polysilicon layer on this dielectric layer is in order to form a top electrode, so this bottom electrode and this top electrode form a structure of piling up electric capacity.

2. the method for claim 1, wherein the formation method of these a plurality of trench of step (a) is the anisotropic reactive ion-etching, etchant is a chlorine.

3. the method for claim 1, wherein the degree of depth of these a plurality of trench all about 4000 dusts between about 6000 dusts.

4. the method for claim 1, wherein the formation method of this first insulating barrier of step (b) is between about 300 ℃ to about 700 ℃ of temperature, utilizes chemical vapour deposition technique and forms.

5. the method for claim 1, wherein this first insulating barrier comprises the oxide of silicon.

6. the method for claim 1, wherein the thickness of this first insulating barrier is about 2/3rds of these a plurality of trench width.

7. the method for claim 1, wherein to form the method for this groove be the anisotropic reactive ion-etching to step (f), etchant is a fluoroform.

8. the method for claim 1, wherein the degree of depth of this groove is about 2500 dusts between about 3500 dusts.

9. the method for claim 1, wherein the formation method of first polysilicon layer of this doping of step (g) is between about 550 ℃ to about 650 ℃ of temperature, with the silicomethane is reacting gas, and simultaneously arsenic doped, phosphonium ion utilize Low Pressure Chemical Vapor Deposition and form.

10. the method for claim 1, wherein the thickness of first polysilicon layer that should mix about 250 dusts between about 350 dusts.

11. the method for claim 1, wherein the formation method of this conductive layer of step (h) is between about 600 ℃ to about 800 ℃ of temperature, is reacting gas with the tungsten hexafluoride, utilizes Low Pressure Chemical Vapor Deposition and forms.

12. method as claimed in claim 11, wherein the material of this conductive layer comprises tungsten.

13. method as claimed in claim 11, wherein the thickness of this conductive layer arrives between about 3500 dusts about 2500 dusts.

14. the method for claim 1, wherein the formation method of this conductive layer of step (h) is between about 600 ℃ to about 800 ℃ of temperature, with tungsten hexafluoride and silicomethane reacting gas, utilizes Low Pressure Chemical Vapor Deposition and forms.

15. method as claimed in claim 14, wherein the material of this conductive layer comprises the silicide of tungsten.

16. method as claimed in claim 14, wherein the thickness of this conductive layer arrives between about 2500 dusts about 1500 dusts.

17. the method for claim 1, wherein this etching notched step of step (j) is to utilize the anisotropic reactive ion-etching, etchant is a chlorine, make the thickness of this conductive plug arrive between about 2500 dusts about 1500 dusts, and this bit line about 2000 Izod right sides under this trench surface that form.

18. the method for claim 1, wherein the formation method of step (k) the 3rd insulating barrier is between about 300 ℃ to about 700 ℃ of temperature, utilizes chemical vapour deposition technique and forms.

19. the method for claim 1, wherein the 3rd insulating barrier comprises the oxide of silicon.

20. the method for claim 1, wherein the thickness of the 3rd insulating barrier arrives between about 2500 dusts about 1500 dusts.

21. the method for claim 1, wherein this gate insulator is the oxide of silicon, and between about 200 dusts, its formation method is between about 850 ℃ to about 950 ℃ of temperature to its thickness about 50 dusts, utilizes thermal oxidation method and forms.

22. the method for claim 1, wherein this lightly doped source/drain regions of step (m) is implanted N type ion, and between about 75KeV, dosage is about 1 * 10 about 30KeV for its energy ¹²Atom/square centimeter is to about 1 * 10 ¹⁴Between atom/square centimeter.

23. the method for claim 1, wherein this heavily doped source/drain regions of step (o) is implanted N type ion, and between about 100KeV, dosage is about 1 * 10 about 50KeV for its energy ¹⁴Atom/square centimeter is to about 1 * 10 ¹⁶Between atom/square centimeter.

24. the method for claim 1, wherein the tempering step temperature of step (p) is between about 950 ℃ to about 1050 ℃, and the time of carrying out is between 10 seconds to about 60 seconds.

25. the method for claim 1, this dielectric layer of step (t) wherein, its thickness arrives between about 80 dusts about 40 dusts, the formation method be form earlier a thickness about 10 dusts to the silicon oxide layer between about 50 dusts, then form a thickness about the silicon nitride layer of 10 dusts between about 20 dusts, carry out the step of thermal oxidation then, on this silicon nitride layer, form one silica layer.

26. the method for claim 1, wherein this dielectric layer of step (t) is the oxide of tantalum, and about 200 dusts of its thickness utilize sputtering method and form between about 300 dusts.

27. the manufacture method of a memory cell array comprises the following steps: at least

(a) in the semiconductor substrate, form a plurality of trench, and deposit one first insulating barrier in order to fill up this a plurality of trench;

(b) form a groove in the corner on these a plurality of trench trench surface wherein;

(c) deposit a doped polycrystalline silicon layer at this groove;

(d) deposition one conductive layer on this doped polycrystalline silicon layer, and this conductive layer fills up this groove;

(e) this conductive layer of etch-back forms a conductive plug in this groove, carry out etching notched step then on this conductive plug, and this semiconductor-based end of etching is in order to form a bit line;

(f) on this bit line, reach periphery and form one second insulating barrier, in order to bury this bit line;

(g) on this semiconductor-based end, form source, and this source/drain regions is distributed in the zone between these a plurality of trench; And

(h) carry out tempering step, the impurity in the doped polycrystalline silicon layer can spread and contact with source/drain regions, makes this bit line that buries can aim at this source/drain regions automatically.

28. method as claimed in claim 27, wherein the formation method of these a plurality of trench of step (a) is the anisotropic reactive ion-etching, and etchant is a chlorine, and the degree of depth of these a plurality of trench all arrives between about 6000 dusts about 4000 dusts.

29. method as claimed in claim 27, this first insulating barrier of step (a) oxide that is silicon wherein, the formation method is between about 300 ℃ to about 700 ℃ of temperature, utilizes chemical vapour deposition technique and forms.

30. method as claimed in claim 27, wherein the thickness of this first insulating barrier is 2/3rds of these a plurality of trench width.

31. method as claimed in claim 27, wherein the formation method of this groove of step (b) is the anisotropic reactive ion-etching, and etchant is a fluoroform.

32. method as claimed in claim 27, wherein the degree of depth of this groove is about 2500 dusts between about 3500 dusts.

33. method as claimed in claim 27, wherein the formation method of this doped polycrystalline silicon layer of step (c) is between about 550 ℃ to about 650 ℃ of temperature, with the silicomethane is reacting gas, while arsenic doped, phosphonium ion, utilize Low Pressure Chemical Vapor Deposition and form, and the thickness of this doped polycrystalline silicon layer about 250 dusts between about 350 dusts.

34. method as claimed in claim 27, wherein the material of this conductive layer of step (d) comprises tungsten, its formation method is between about 600 ℃ to about 800 ℃ of temperature, with the tungsten hexafluoride is reacting gas, utilize Low Pressure Chemical Vapor Deposition and form, and the thickness of this conductive layer about 2500 dusts between about 3500 dusts.

35. method as claimed in claim 27, wherein the material of this conductive layer of step (d) comprises tungsten, its formation method is between about 600 ℃ to about 800 ℃ of temperature, with tungsten hexafluoride and silicomethane reacting gas, utilize Low Pressure Chemical Vapor Deposition and form, and the thickness of this conductive layer about 2500 dusts between about 3500 dusts.

36. method as claimed in claim 27, wherein the thickness of this bit line of step (e) arrives between about 2500 dusts about 1500 dusts.

37. method as claimed in claim 27, wherein this depression step of step (e) is the anisotropic reactive ion-etching, utilizes chlorine to be etchant, makes this bit line about 1000 dusts under this trench surface arrive about 2000 Izod right sides.

38. method as claimed in claim 27, wherein this second insulating barrier of step (f) comprises the oxide of silicon, its formation method is between about 300 ℃ to about 700 ℃ of temperature, utilize chemical vapour deposition technique and form, and the thickness of this second insulating barrier about 2000 dusts between about 3000 dusts.

39. method as claimed in claim 27, wherein this source/drain regions of step (g) utilizes ionic-implantation and forms, and implants energy and arrives between about 100KeV about 50KeV, and dosage is about 1 * 10 ¹⁴Atom/square centimeter is to about 1 * 10 ¹⁶N type ion between atom/square centimeter.

40. method as claimed in claim 27, wherein between about 950 ℃ to about 1050 ℃ of the tempering step temperature of step (h), the time of carrying out is between 10 seconds to about 60 seconds.

Images