CN1228833C

CN1228833C - active pixel sensor

Info

Publication number: CN1228833C
Application number: CNB981087108A
Authority: CN
Inventors: 季明华
Original assignee: Vanguard International Semiconductor Corp
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 1998-05-29
Filing date: 1998-05-29
Publication date: 2005-11-23
Anticipated expiration: 2018-05-29
Also published as: CN1237774A

Abstract

An active pixel sensor includes a photodiode, a bi-carrier transistor, and a metal oxide semiconductor transistor. The photodiode has a cathode connected to a power supply and an anode connected to the MOS transistor. The photon energy impinges on the anode and creates an electrical charge in the photodiode. And a metal oxide semiconductor transistor for preventing an image from being too bright by disconnecting the anode of the photodiode from the base of the bi-carrier transistor, and connecting the anode of the photodiode to the metal oxide semiconductor transistor so that charges in the photodiode flow through the metal oxide semiconductor transistor. The dual carrier transistor amplifies the charge to generate an electrical signal.

Description

CMOS active pixel sensor

The present invention relates to a kind of active pixel sensor cell, be particularly related to circuit and semiconductor device, in order to receive the light and convert light to a signal of telecommunication represent light intensity and to cross picture lag problem bright and that cause by the residual charge in the device in order to the image that elimination is caused by excessive charge.

The traditional images circuit comprises the photoreceptor array of a two dimension.Each photoreceptor comprises an image-element (pixel).Clash into the array of photoreceptor from the luminous energy of object radiation or reflection.Luminous energy converts electronic signal to by photoreceptor.Vision circuit scans each photoreceptor to read the signal of telecommunication.The signal of telecommunication of image is handled and is revealed by external circuit.

Using prevailing one chip image technology at present is charge coupled device (Charged CoupleDevice is hereinafter referred to as CCD) camera.CCD is operated by the electric charge that the photoreceptor trap that is accumulated in the Semiconductor substrate produces.The degree of depth of trap is controlled by being positioned at the semiconductor substrate surface grid potential.By changing grid potential, electric charge can move to sensing point at semiconductor substrate surface.Electric charge just is exaggerated into the signal of telecommunication of image.

Present metal-oxide semiconductor (MOS) (hereinafter referred to as MOS) technology allows the electric charge in the CCD structure to transmit, and can finish with video to be close to perfect efficient.Yet the sub-fraction charges accumulated can be lost when mobile along surperficial.Each trap institute charges accumulated can be moved and sensing when each frame.General this time is the order of magnitude of per second 30-60 frame.

CCD technology defectiveness.By sensing and before amplifying, can directly be removed by the electric charge that the light bump produces.Because this process is inefficent, the gain of this device (electronics output is to the photon input) is less than 1.Therefore, can limit each trap charge stored amount.The lowest charge amount that can be sensed is can be by the amount that sensor amplifier sensed on the sensor amplifier noise.The maximum sensing quantity of electric charge is confined to then that essence can produce and can moves on to the quantity of electric charge in another trap by a trap.

Overcome the restriction of these CCD dynamic ranges, come the sensing incident light with transistor.In U.S. Patent No. 5,260,592 (Mead people etc.), U.S. Patent No. 5,324,958 (Mead people etc.), and " AHigh Resolution CMOS Imager With Active Pixel Using Capacitively CoupledBiPolar Operation ", Chi people etc., paper #82, and Proceedings of InternationalConference on VLSI-technology, systens, and applications, Taipei, Taiwan, June 1997, and described high-definition image has just like Figure 1A, 1B, the simple structure shown in the 1C.These dot structures adopt the standard process techniques of typical CMOS logic technology.

N type impurity injects a P type substrate 5 in order to form a N type trap 10.Field oxide 20 is grown up on the surface of Semiconductor substrate, in order to limit the border of pixel.P type impurity is injected into the P type base stage 15 that forms transistor Q1160 in field oxide 20.N type trap is connected to a power supply unit, as the collector electrode of transistor Q1160.Next step is grown up the thin layer of a gate oxide, in order to form the capacitor dielectric 30 of capacitor C 65 on the surface of P type base stage 15.One deck polysilicon 35 is deposited on the whole P type base stage 15.In order to form second pole plate of capacitor C 65.The edge reoxidize form with the oxide gap after, N type impurity is injected into the emitter 25 as transistor Q1160.P type base stage 15 keeps floating.Its current potential is by coupling capacitance C65 current potential V _RowDetermine.The polycrystalline silicon substances layer is connected to row enable circuit V _Row62.Row enable circuit V _Row62 will make the collected electric charge of transistor Q1160 transfering transistor Q1160.

Second insulant as silicon dioxide is deposited on the surface of Semiconductor substrate in order to form dielectric medium 40.One metal level 45 places contact hole 50 with the emitter 25 of bipolar transistor Q1160.This metal level 45 is as the intraconnections that is connected to sensor amplifier 70.Above-mentioned technology can be used to make the CMOS transistor significantly.For example, polycrystalline silicon substances 35 can be used for can be used to do source/drain regions as the N type infusion of this emitter 25 in order to form the transistorized grid of CMOS.Compare with the process with manufacturing CCD, making double carriers pixel and the transistorized compatibility of CMOS is a very big advantage.

Strike the active area 17 of P type base stage from the light quantum L1105 of external world's reflection or radiation.Light quantum 105 is absorbed the back and forms electron-hole pair near collector-base bonding land and emitter region-base stage bonding land.Electron-hole pair can be collected in nearest p-n bonding land.A spot of charge carrier collected in collector-base bonding land 12 or emitter-base stage bonding land as base current.It is collector current that base current is multiplied by transistorized current gain.Signal code I on the emitter 25 of transistor Q1160 _SCFor photon conversion become base current that electron-hole pair produces and collector current and.Signal code I _SC100 are transferred to sensor amplifier 70 under certain conditions.

Referring now to the operation of Fig. 1 D with the understanding transistor pixel structure.102 row enable circuit V between integration period _Row62 remain on a fixed potential uses so that base-emitter bonding land 22 reverses biased of transistor Q160.In this case, photon 105 converts the electric current that electron-hole pair produces to and can accumulate on the capacitor C65.

When wanting to read in the quantity of electric charge of 107 generations between integration period, row enable circuit V _Row62 during time for reading 104, and its current potential can reach high potential.By being coupled to capacitor C65 to V _Row62, P type base stage potential energy rises, and becomes forward bias according to emitter 25.Understand the base stage 15 of inflow transistor Q1 160 and form emitter current at the electric charge of capacitor C65, that is signal code I _SC100.

Other structures that comprise optical diode and MOS transistor can be with reference to " Image Capture Circuitsin CMOS " E.Fossum, Paper #B1, Proceedings of International Conference onVLSI-Technology, Systems, and Applications, Taipei, Taiwan, June 1997.One passive pixel circuit comprises an optical diode and a MOS transmission transistor, and optical diode converts light to electric charge.The MOS transmission transistor makes electric charge by arriving electric charge accumulation amplifier.One active pixel circuit comprises an optical diode, a MOS transmission transistor and the one source pole follower temporary amplifier as electric charge accumulation amplifier.The MOS transistor of signal institute activation of being reset is placed into the active pixel circuit, makes it as an electronic switch in order to the optical diode that resets.

With the described cmos pixel circuit of Chi by comparison, the advantage that Figure 1A, the active double carriers image element circuit shown in 1B and the 1C have high sensitivities, simplify pixel layout and reduce manufacturing cost.Yet the double carriers active pixel had bright and shortcoming picture lag.

With reference to Fig. 2 to understand bright phenomenon.In a pel array (pixel A 80-pixel X85), a row pixel A 80 can accumulation be clashed into the electric charge that transistor Q160a produces from light quantum L1105.At this moment, row enable circuit V _RowaReach electronegative potential, make the base-emitter bonding land reverse biased of transistor Q1; And allow electric charge be collected on the capacitor C65a.At this moment, another row pixel X85 can be read with sensing at present at the charge potential of capacitor C65a.

If the light quantum energy that impinges upon on the pixel A 80 is enough big, electric charge begins the base-emitter bonding land forward bias voltage drop with transistor Q160a.This can cause that one overflows electric current (overflowcurrent) I _Ofc95 flow to row intraconnections 90.The total current I that sensor amplifier senses _Tot110 for overflowing electric current I _Ofc95 with signal code I _SCSum.The pixel that is read (pixel X85) will this has than it brightness also bright.This can cause that bright spot is bright excessively in the image.

Referring now to the reason of Fig. 3 with the understanding picture lag.Pixel X in this figure, last frame 200, the frame before present frame is read.As row enable circuit V _RowxWhen reaching electronegative potential 185 by high potential, according to emitter, by the coupling of capacitor C165, this P type base stage is anti-phase bias voltage.

In image integration time at the beginning the time, all pixels that are not all row all have identical P type base stage potential energy.Read action at the beginning, V one _RowWhen transferring to electronegative potential by high potential, promptly during pulse height, the slippage of P type base stage potential energy is:

Δ _VB=(pulse height) * (coupling rate)

The coupling efficiency of capacitor C 165 is defined as:

γ = \frac{C}{C + C_{BE} + C_{BC}}

Wherein:

C _BEIt is the junction capacitance of the base-emitter of transistor Q1 160

C _BCIt is the junction capacitance of base stage-collector electrode of transistor Q1 160

P type base potential is by current potential V _Row(γ) controls with coupling efficiency.Therefore, the electric charge of removing from capacitor C165 is also incomplete, and can cause a part of aftercurrent 210 at the emitter of transistor Q1 160.

The second portion of aftercurrent 210 is, is retained in the residue of the small part charge carrier of p-base stage from the injection electronics of the base stage-emitter-base bandgap grading bonding land of the suitable phase bias voltage of transistor Q1 160 between the time for reading formerly.The electric charge that remains in P type base stage continues to flow to the emitter of transistor Q1 160 with current gain, and adds the signal code 215 of present time for reading.This can form a ghost after trailing mobile object or bright object.Remaining electric charge can disappear because of reorganization or minority carrier leave P type base stage at last after a period of time.The time of picture lag approximately is the lifetime (being about 100 milliseconds) of minority carrier, and its sustainable several frame.

Impurity can be added in P type base stage and be used for as " killer between the lifetime " (life-time killer) in order to reduce reorganization time.The difficulty of " killer between the lifetime " is that it can increase leakage current between the bonding land, lowers the sensitivity of image.

U.S. Patent No. 5,097, the optical sensor that 305 (Mead people etc.) are carried has the capacitor that a transistor and is coupled to transistor base.One transmission transistor be placed on emitter in order to coupled signal electric current optionally to sensor amplifier.

U.S. Patent No. 5,288,988 (Hashimo people etc.) describe one and are similar to Figure 1A, the optical sensor circuit shown in 1B and the 1C.This device adds a MOS transistor in its light-switching device.When the MOS transistor activation, make that by the residual charge of eliminating from transistorized base stage above-mentioned aftercurrent is blocked.

Therefore main purpose of the present invention is to provide a kind of CMOS active pixel sensor to become a signal of telecommunication in order to the convert light energy of a quantum, represents the size of this light quantum energy.

Another main purpose of the present invention provides a kind of CMOS active pixel sensor and is used for avoiding the bright excessively problem of image.

Another main purpose of the present invention provides a kind of CMOS active pixel sensor and is used for reducing residual charge to reduce the problem of picture lag.

According to purpose of the present invention, a kind of CMOS active pixel sensor comprises an optical diode, a double carriers transistor and a MOS transistor.Optical diode has a negative electrode and an anode that is connected to a power supply unit.Light quantum can impinge upon and produce electric charge on the anode and in optical diode.MOS transistor can avoid image bright excessively.MOS transistor has drain electrode, one source pole and a grid that is connected to the anode of optical diode, and this grid is connected to sensor control circuit, in order to optionally to make MOS transistor activation and inefficacy be used for stoping or to allow flow of charge through MOS transistor.The double carriers transistor can amplify the charge generation signal of telecommunication.The double carriers transistor has a collector electrode and is connected to power supply unit, and the source electrode that a base stage is connected to MOS transistor is in order to receiving electric charge when MOS transistor is enabled, and an emitter is connected to external circuit and sends the signal of telecommunication to external circuit.

CMOS active pixel sensor also comprises a parasitic mos transistor, and this parasitic MOS transistor has a drain electrode, is the anode of optical diode; One source pole is the anode of optical diode of showing an adjacent CMOS active pixel sensor of active picture sensor in an active pixel sensor array.Parasitic mos transistor has a grid and is connected to a reset circuit in order to the parasitic mos transistor conducting, make it to reset at a potential energy of anode of showing the optical diode of identical potential energy current potential, therefore after resetting, can on CMOS active pixel sensor, eliminate by the picture lag phenomenon that anode potential inequality causes.

For above-mentioned purpose of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. are done following detailed description.

Figure 1A and 1B provide the top view of traditional photo sensor unit and the profile of Semiconductor substrate.

Fig. 1 C provides the circuit diagram of traditional photo sensor unit among Figure 1A and the 1B.

Fig. 1 D provides the sequential chart of traditional photo sensor unit among Figure 1A and the 1B.

Fig. 2 provides the circuit diagram of two unit of the photosensor array unit of conventional art, overflows electric current in order to explanation and causes image bright excessively.

Fig. 3 provides the circuit diagram of the photosensor array unit of conventional art, in order to the caused picture lag of explanation residual circuitry.

Fig. 4 A and 4B provide according to the top view of CMOS active pixel sensor of the present invention and the profile of Semiconductor substrate.

Fig. 4 C provides the circuit diagram of active pixel sensor cell of the present invention among Fig. 4 A and Fig. 4 B.

Fig. 4 D provides the sequential chart of active pixel sensing unit of the present invention.

Fig. 5 provides the circuit diagram of two unit of active pixel sensor array of the present invention unit, eliminates in order to explanation and overflows electric current.

Fig. 6 A, 6B and Fig. 6 C provide the top view and the profile of three unit, active pixel sensor array of the present invention unit, in order to illustrate that the optical diode reset operation is to reduce picture lag.

With reference to Fig. 4 A, 4B and 4C, it shows according to a preferred embodiment of the present invention.In order to understand the structure of CMOS active pixel sensor of the present invention.The manufacturing of this device is since a typical silicon wafer P type substrate 305.Then with P substrate 305 surface shaded and inject a N type impurity as N type trap 310.One insulation layer or field oxide 315 are grown up to limit the zone of active pixel cell.Among the zone of active pixel sensor cell, limit the p type anode 330 of optical diode D1 420 with mask.N type trap and power supply V _CCContact and as the negative electrode of optical diode D1 420.Second district among the zone of active pixel sensor cell limits the zone of the P type base stage 320 of double carriers transistor Q1 420 with mask.Inject a p type impurity to form P type base stage 320.Afterwards, in the zone of P type base stage 320, cover the 3rd zone and inject the emitter 325 of N type impurity as double carriers transistor Q1 420.The collector electrode of double carriers transistor Q1 420 is a N type trap 310.

The P type base stage 320 of double carriers transistor Q1 420 and the p type anode 330 of optical diode D1 420 form the source electrode and the drain electrode of MOS transistor respectively.Grid oxic horizon 340 is grown up above

source electrode

320 and 330 channel region 337 of drain electrode.One polycrystalline silicon substances 335 is arranged on the grid oxic horizon 340 and is etched with the grid that forms MOS transistor M1 315.

One insulant is deposited on the surface of Semiconductor substrate in order to form dielectric medium 350.Be formed at an opening of dielectric medium 350 with the contact 327 of N+ emitter 325.Deposit one metal level 355 is the external circuit of an active pixel sensor array in order to connect emitter 325 and the sensor amplifier 425 of transistor M1 410.The polycrystalline silicon substances 335 that forms MOS transistor M1 415 grids is connected to row enable circuit V _Row416, be a sensor control circuit.Apparently, above-described flow process can be used to make the CMOS transistor.For example polycrystalline silicon substances 335 can be used as the transistorized grid of CMOS, is used for doing the N type infusion of emitter 325 to form source/drain regions.With the process that is used for making the CCD method by comparison, making double carriers pixel and the transistorized compatibility of CMOS has very large advantage.

Referring now to the operating principle of Fig. 4 D with the understanding active pixel sensor cell.The p type anode of light quantum L 334 bump diode D1 420.Light quantum L 334 can give enough energy and produce electron-hole pair, is similar at Figure 1A the transistor Q1 160 that 1B and 1C describe.The p type anode of hole meeting migration optical diode D1 420.Electronics can be collected at the negative electrode (N type trap 310) of optical diode D1 420 and via power supply V _CCRemove.The hole of positively charged is accumulated in the p type anode of optical diode D1 420, and diagram is a potential energy that increases progressively.Row enable circuit V _Row415 become electronegative potential from a high potential, and conducting PMOS transistor M1 415 then.Charge Q by light quantum L 334 (image) generation _S494 current potential V with p type anode _P-anodeExpression, the P type base stage 320 of meeting inflow transistor Q1 410 forms base current I _B1417.Base current I _B1417 can be amplified and form signal code I by transistor Q1 410 _SC412.After sensing signal code, row enable circuit V _Row416 can be returned to electronegative potential 485, have the P type base stage 320 that a residual charge Q496 is retained in optical diode S1 420 this moment.Afterwards, the p type anode 330 of optical diode D1 420 can reset to a current potential with described reset operation hereinafter.

Earlier avoid the bright excessively operating principle of pixel image to understand CMOS active pixel sensor of the present invention with reference to Fig. 5.Pixel A 430 is two CMOS active pixel sensor of active pixel sensor array with pixel X435.Pixel A 430 is connected to row 460 and common sensor amplifier 426 with pixel X435.

This pixel A 430 triggers control by row enable circuit V _Rowa440 via intraconnections Rowa450 control, and pixel X435 triggers control by row enable circuit V _Rowx455 control via intraconnections Rowx455.When row cause system energy circuit V _Rowa450 arrive high potential 422, and pixel A 430 can be in accumulated time 489.This moment is if the stored charge that the optical diode D1420b of light quantum L2470 bump pixel X435 produces is read row enable circuit V _Rowx455 can reach electronegative potential 477 with conducting PMOS transistor M1 415b.Signal code I _SC412b can flow out from the emitter of the transistor Q1 410b of pixel X435.

Even it is very strong to impinge upon the light quantum of optical diode D1 420a, do not have the electric current I of overflowing among Fig. 2 yet _Ofc95.PMOS transistor M1415a does not work and does not have electric current can flow through this transistor Q1410a.The hole can be accumulated on the p type anode under extremely strong light quantum L1465 effect, and the potential energy that increases p type anode apace is up to optical diode forward bias a little, and " overflowing electric current " can flow to the power supply V of the negative electrode that is connected on optical diode _CCTherefore, total current I _Tot413 do not have incoherent part and only by signal code I _SCConstitute.Because sensing is put 425 electric currents that can receive suitable size of device, so can prevent the formation that image is bright excessively.

With reference to Fig. 4 A, 4B, 4C and 4D understand reset response.Second polycrystalline silicon substances 360 is deposited on one deck when grid oxic horizon is grown up on the formed megohmite insulant.The polysilicon 360 that resets is connected to a reset circuit V _ResetReset circuit V _ResetCan execute an electronegative potential 480 in order to the polysilicon 360 that resets, this will make by the contiguous formed parasitic PMOS transistor turns of active pixel sensor and make all p type anodes 330 reset to identical potential energy.About the details of parasitic P-MOS transistor AND gate reset response, at following Fig. 6 A, 6B and 6C can be illustrated.

Fig. 6 A, 6B and 6C show three the CMOS active pixel sensor 500a that list in an active pixel sensor array that is made of row and row, 500b, 500c.Each CMOS

active pixel sensor

500a, 500b, the PMOS transistor M1515a of 500c, 515b, the grid 505a of 515c, 505b, 505c is connected to row enable circuit V by this common row polycrystalline silicon substances 335 _Row Reset polysilicon 360 and each CMOS

active pixel sensor

500a, 500b, the polysilicon 360 that resets of 500c is connected to each other, and is connected to reset control circuit V _Reset535.At an end end of showing active picture sensor, bonding land, an edge 520 is injected into Semiconductor substrate 305 by a P type material and is formed.This edge join district is connected to a grid bias power supply V _P+330.Formed oxide layer 365 when grid oxic horizon is grown up can be polysilicon layer 360 and the P-anode 330a of resetting, 330b, and 330c is isolated.

Each

p type anode

330a, 330b, 330c be as each CMOS

active pixel sensor

500a, 500b, the PMOS transistor M1515a of 500c, 515b, the drain/source of 515c.As reset circuit V _Reset530 when being biased into an electronegative potential, each CMOS

active pixel sensor

500a, 500b, respectively this PMOS transistor M1515a of 500c, 515b, 515c can be switched on and all

p type anode

330a, 330b, the current potential of 330c are reset to the current potential identical with the edge join district, grid bias power supply V _P+530.

The channel region that one VT infusion 535 optionally is placed in parasitic transistor P1 550 in order to the stopping potential that limits a parasitic mos transistor P1 550 to the value of wanting.This infusion can be N type impurity or the p type impurity end depends on that parasitic mos transistor P1 550 is used as to strengthen or the shortage MOS transistor.

Parasitic transistor P1 550 action, by the current potential of all p type anodes of row that reset to the bias V in edge join district _P+530 is identical, and the problem that this meeting part removal of images lags behind is as described at conventional art.

With reference to Fig. 4 C and 4D.During reading action, image charge Q _S494 can flow into P type base stage as a base current, make the P type base stage forward bias voltage drop of transistor Q1 410 and open beginning double carriers transistor action.Image charge Q _S494 base currents that form can be exaggerated and become emitter current I _SC, it can flow into sensor amplifier 425.The total electrical charge that sensor amplifier 425 is gathered, the image charge Q that is exaggerated _S494, be used for representing impinging upon the intensity of the light quantum L1334 of optical diode D1 420.

The annode area of this optical diode D1 420 is designed to also bigger than the base stage of double carriers transistor Q1 410.This can force the base stage of double carriers transistor Q1 410 to have the voltage identical with the anode of optical diode D1 420.The minority carrier (from the emitter injected electrons) that injects is bound in the base stage of double carriers transistor Q1 410, and can't flow through reverse P type channel MOS transistor and arrive the anode of optical diode D1 420.

One corresponding pixel, PNP bipolar transistor and nmos pass transistor can be by this injection of reversing the polarity of silicon matter finish at an easy rate.The operation bias voltage also can be suitably reverse.

In sum; though the present invention discloses as above with a preferred embodiment; right its is not in order to limit the present invention; any those skilled in the art; without departing from the spirit and scope of the present invention; can do various changes and retouching, so protection scope of the present invention should be as the criterion with claims institute restricted portion.

Claims

1. An active pixel sensor for receiving light quantum energy and converting the light quantum energy into an electrical signal, comprising:

a photodiode having a cathode connected to a power supply and an anode where the photon will strike the anode and generate charge in the photodiode;

A metal-oxide-semiconductor transistor for preventing image overbrightness having a drain connected to the anode of the photodiode, a source and a gate connected to a sensor control circuit, wherein the sensor control circuit can select selectively enabling and disabling the MOS transistor to allow the charge to flow through the MOS transistor; and

A bicarrier transistor for amplifying the charges to generate an electrical signal has a collector connected to the power supply, a collector connected to the metal-oxide-semiconductor transistor for receiving when the metal-oxide-semiconductor transistor is enabled The base of these charges and an emitter connected to the external circuit for transferring the electrical signal to the external circuit.

2. The active pixel sensor as claimed in claim 1, wherein the sensor is formed on a semiconductor substrate, the impurity with the first conductivity type is implanted on a surface of the semiconductor substrate, and the impurity of the second conductivity type A well is implanted in the surface of the semiconductor substrate.

3. The active pixel sensor as claimed in claim 2, wherein the cathode of the photodiode is a well implanted in the surface of the semiconductor substrate, and the anode is implanted in the well with impurities of the first conductivity type into the second A region is formed where the anode is sufficiently larger than the base of the bicarrier transistor such that residual minority carriers in the base are trapped in the base to reduce image lag problems.

4. The active pixel sensor as claimed in claim 3, wherein the collector of the bicarrier transistor is a well implanted in the semiconductor substrate, and the base is made of the first conductivity type in the well. Impurities are implanted into the second region, and the emitter is formed by implanting the impurities of the second conductivity type into the third region in the base.

5. The active pixel sensor as claimed in claim 4, wherein the drain of the metal oxide semiconductor transistor is a first region having the impurity of the first conductivity type, and the source of the metal oxide semiconductor transistor is a first region having the first conductivity type. The second region of impurities of a conductivity type, and the gate are formed by growing a channel region between the source and the drain of a gate oxide layer.

6. The active pixel sensor of claim 5, wherein the emitter is connected to external circuitry via a metal interconnect deposited on an insulating layer on the surface of the semiconductor integration, and is in contact with emitter set .

7. The APS of claim 1, further comprising a parasitic metal-oxide-semiconductor transistor having a drain that is the anode of the photodiode and a source that is an active column in the APS array. The anode of the photodiode of the adjacent active pixel sensor of the pixel sensor and a gate are connected to the reset circuit for turning on the parasitic metal oxide semiconductor transistor, thereby resetting a potential of the anode of the photodiode to prevent the active Image lag issue on source pixel sensor.

8. An image array, used to receive light energy reflected or radiated from the outside, and convert the light energy into an electrical signal to represent the intensity of the light energy, including:

a) A plurality of active pixel sensors arranged in rows and columns, wherein each active pixel sensor of the plurality of active pixel sensors includes:

a photodiode having a cathode connected to a power supply and an anode, wherein light energy strikes the anode and generates charge at the cathode;

a metal oxide semiconductor transistor to prevent image overbrightness in an image array having a drain connected to the anode of the photodiode, a source, and a gate, and

A bicarrier transistor for amplifying the charges to generate the electrical signal has a collector connected to a power supply and a base connected to the MOS transistor when the MOS transistor is enabled for receiving these charges, and an emitter;

b) a column enabling circuit is connected to each gate of the metal oxide semiconductor transistors on each column to selectively enable and disable each metal oxide semiconductor transistor on each column, so that these charge flows through the metal oxide semiconductor transistor; and

c) a plurality of sense amplifiers, wherein each sense amplifier is connected to the emitters of the bicarrier transistors of the active pixel sensors on each row to sense and amplify the electrical signal, and transmit the electrical signal sent to external circuits.

9. The image array as claimed in claim 8, wherein the active pixel sensor array is formed on a semiconductor substrate, with impurities of the first conductivity type implanted on a surface of the semiconductor substrate, and in the semiconductor substrate A well of impurities of the second conductivity type is implanted into the surface of the substrate.

10. The image array as claimed in claim 9, wherein the cathode of the photodiode of each active pixel sensor is a well implanted in the surface of the semiconductor substrate, and the anode is in the cathode in the first conductivity type Impurity implantation is formed in the first region, wherein the anode is sufficiently larger than the base of the bicarrier transistor, so residual minority carriers in the base are trapped in the base to reduce image lag.

11. The image array as claimed in claim 10, wherein the collector of the bicarrier transistor of each active pixel sensor is a well implanted in the semiconductor substrate, and the base is formed in the well with a first Impurities of the conductivity type are implanted into the second region, and the emitter is formed by implanting the impurities of the second conductivity type into the third region in the second region.

12. The image array as claimed in claim 11, wherein the drain of the metal oxide semiconductor transistor of each active pixel sensor is a first region with impurities of the first conductivity type, and the source of the metal oxide semiconductor transistor There is a second region with impurities of the first conductivity type, and the gate is formed by depositing an entire gate oxide layer on the entire source and a communication region between the drain.

13. The image array of claim 12, wherein the emitter is connected to a sense amplifier and contacts the emitter with a metal interconnect deposited on an insulating layer on the surface of the semiconductor substrate.

14. The image array of claim 8, wherein each active pixel sensor further comprises a parasitic metal-oxide-conductor transistor having a drain electrode that is the anode of the photodiode, a drain electrode in an active pixel sensor array A source of the anode of the photodiode and a gate of a column of APS adjacent to the APS.

15. The image array as claimed in claim 14 , further comprising a reset circuit connected to the gate of the parasitic metal-oxide-semiconductor transistor, thereby enabling the parasitic metal-oxide-semiconductor transistor to be activated in each column of the active pixel sensor The anodes of each photodiode are reset to an equal potential to avoid image lag problems on the image array.

16. A method for manufacturing a semiconductor device, which is used to manufacture an active pixel sensor on a semiconductor substrate having impurities of the first conductivity type, so as to receive light quantum energy and convert the light quantum into an electrical signal, the steps comprising:

a) forming a well in the semiconductor substrate through the mask region of the semiconductor substrate, and implanting impurities of the second conductivity type into the semiconductor substrate;

b) defining a region of the active pixel sensor by growing a field oxide layer outside the region;

c) forming a photodiode in the well with the mask region of the semiconductor substrate, and injecting impurities of the first conductivity type to form an anode of the photodiode, wherein the well is a cathode of the photodiode;

d) forming a double-carrier transistor, applying a mask to the semiconductor substrate, and injecting impurities of the first conductivity type as a base, applying a mask to the semiconductor substrate, and injecting impurities of the second conductivity type to make is the emitter, wherein the bicarrier transistor has a collector which is the well; and

e) forming a metal-oxide-semiconductor transistor by depositing a gate oxide in a channel region of the anode for use as the drain of the metal-oxide-semiconductor transistor, and the base for use as the a source of the metal oxide semiconductor transistor; and depositing first polysilicon to form a gate on the gate oxide layer.

17. The method of claim 16, wherein the gate is connected to a sensing control circuit for selectively enabling and disabling the MOS transistor such that the photon hits the charge formed at the anode flows to the base of the bicarrier transistor.

18. The method of claim 16, wherein the anode is sufficiently larger than the base of the bicarrier transistor so that minority carriers in the base are trapped in the base, thereby reducing image lag.

19. The method of claim 16, further comprising a step of forming a parasitic metal oxide semiconductor transistor, the step comprising:

a) growing an insulating material to form a parasitic gate oxide layer of the parasitic metal oxide semiconductor transistor;

b) depositing a second polysilicon substance on the parasitic gate oxide layer as a gate of the parasitic metal oxide semiconductor transistor; and

c) wherein a drain of the parasitic metal-oxide-semiconductor transistor is the anode of the photodiode, and a source of the parasitic metal-oxide-semiconductor transistor is the photodiode formed on the semiconductor substrate adjacent to an active pixel sensor the anode of the diode.

20. The method of claim 16, wherein the gate of the parasitic MOS transistor is connected to a reset circuit so that a reset signal is provided to enable the parasitic MOS transistor to reset the anode at a potential to avoid image lag on the APS.