CN1218402C - Compound semiconductor switch circuit apparatus - Google Patents

Abstract

A compound semiconductor switching circuit device originally adopted a method of increasing the gate width Wg to reduce the on-resistance of the FET in order to reduce the insertion loss as much as possible. In addition, the distance between the pad and the adjacent wiring layer is also taken to be 20 μm or more. For the high frequency above 2.4GHz, the design focuses on ensuring the isolation and omitting the shunt FET, and uses the reverse thinking method to consider the effect of reducing the on-resistance of the FET used in the past from two aspects. That is, in the compound semiconductor switching circuit device, the gate width of the switching FET is set at 700 μm or less to reduce its size, and at the same time, the high concentration region 40 is provided at the periphery of the pad to ensure a high density with a small space. Coupling and withstand voltage of frequency signals. As a result, the size of the chip can be greatly reduced.

Description

Compound semiconductor switching circuit device

technical field

The present invention relates to a compound semiconductor switch circuit device used in high-frequency switches, in particular to a compound semiconductor switch circuit device used in a frequency band above 2.4 GHz.

Background technique

In mobile communication devices such as mobile phones, microwaves in the 2.4 GHz band are often used, and switching elements for switching these high-frequency signals are often used in antenna switching circuits and transmission and reception switching circuits (for example, Japanese Patent Application Laid-Open No. 9-181642) . As this element, field-effect transistors (hereinafter referred to as FETs) using gallium arsenide (GaAs) are often used because they deal with high-frequency electromagnetic waves. integrated circuits (MMICs).

Figure 7(A) shows a cross-sectional view of a GaAs FET. The surface part of the undoped GaAs substrate 1 is doped with N-type impurities to form an N-type channel region 2. On the surface of the channel region 2, a gate 3 contacted by spot welding is arranged, and on the GaAs surface on both sides of the gate 3 The sources and drains 4, 5 of ohmic contacts are configured. The transistor uses the gate potential to form a depletion layer in the channel region 2 directly below to control the channel current between the source 4 and the drain 5 .

FIG. 7(B) shows a schematic circuit diagram of a compound semiconductor switching circuit device called SPDT (Single Pole Double Throw) using GaAs.

The sources (or drains) of the first and second FET1 and FET2 are connected to the common input terminal IN, and connected to the first and second control terminals ctl-1 and ctl-2 through the gate resistors R1 and R2 of each FET1 and FET2 , and the drain (or source) of each FET is connected to the first and second output terminals OUT1 and OUT2. The signals applied to the first and second control terminals ctl-1 and ctl-2 are complementary signals, the FET applied with the H level signal is turned on, and the signal applied to the input terminal IN is transmitted to any output terminal. Resistors R1 and R2 are configured to prevent the high-frequency signal from leaking through the grid to the DC potential of the control terminals ctl-1 and ctl-2 that are grounded to the AC.

FIG. 8 shows an equivalent circuit diagram of the compound semiconductor switching circuit arrangement. In the microwave, the impedance of each terminal can be expressed as R1=R2=R3=50Ω based on the characteristic impedance of 50Ω. In addition, if the potentials of each terminal are V1, V2, and V3, the insertion loss and isolation can be expressed by the following equations.

Insertion loss=20log(V2/V1)[dB]

This is the insertion loss when transmitting a signal from the common input terminal IN to the output terminal OUT1,

Isolation＝20log(V3/V1)[dB]

This is the degree of isolation between the common input terminal IN and the output terminal OUT2. For compound semiconductor switching circuit devices, the above-mentioned insertion loss is required to be as small as possible and the isolation is high, so the design of FETs inserted in series into the signal path is particularly important. The reason why GaAs FET is used as this FET is that because GaAs has higher electron mobility than Si, the resistance can be reduced to achieve low loss, and because GaAs is a semi-insulating substrate, it is suitable for high isolation between signal channels. On the contrary, GaAs substrates are more expensive than Si, and if equivalent transistors can be made of Si like PIN diodes, they cannot compete with Si in terms of cost.

FIG. 9 is a circuit diagram of a compound semiconductor switching circuit device that has been put into practical use so far.

In this circuit, a shunt FET3, FET4 is connected between the output terminals OUT1, OUT2 of FET1 and FET2 that perform switching operations and the ground, and the control terminals ctl-2/ctl of FET1 and FET2 are applied to the gates of the shunt FET3 and FET4. Complementary signal of -1. As a result, when FET1 is on, shunt FET4 is on and FET2 and shunt FET3 are off.

In this circuit, when the signal path from the common input terminal IN to the output terminal OUT1 is connected, and the signal path from the common input terminal IN to the output terminal OUT2 is disconnected, because the shunt FET4 is turned on, the input signal is sent to the output terminal OUT2. The leakage current flows to the ground through the ground capacitor C, which can improve the isolation performance.

FIG. 10 shows an example of such an integrated compound semiconductor switch.

On the GaAs substrate, FET1 and FET2 for switching operation are arranged on the left and right of the central part, shunt FET3 and FET4 are arranged near the left and right lower corners, and resistors R1, R2, R3, and R4 are connected to the gates of each FET. In addition, pads corresponding to the common input terminal IN, the output terminals OUT1, OUT2, the control terminals Ctl-1, Ctl-2, and the ground terminal GND are provided around the substrate. Furthermore, it is connected to the sources of the shunt FET3 and FET4, and is connected to the ground terminal GND via a capacitor C for grounding. In addition, the second-layer wiring shown by the dotted line is the gate metal layer (Ti/Pt/Au) formed at the same time as forming the gate of each FET, and the third-layer wiring shown by the solid line is for connecting and connecting each element. Pad metal layer (Ti/Pt/Au) for pad formation. The ohmic metal layer (AuGe/Ni/Au) that is in ohmic contact with the first layer of substrate is the metal layer that forms the source, gate, and lead-out electrodes at both ends of each FET. In Figure 10, in order to protrude the pad metal layer, so it is not shown.

FIG. 11(A) shows an enlarged plan view of a portion of FET1 shown in FIG. 10 . In this figure, a rectangular area surrounded by a dotted line is a channel region 12 formed on a substrate 11 . The four comb-tooth-shaped third-layer pad metal layers 30 extending from the left side are the source 13 (or drain) connected to the output terminal OUT1, and there is a source formed by the first-layer ohmic metal layer 10 below it. pole 14 (or drain). In addition, the four comb-tooth-shaped third-layer pad metal layers 30 extending from the right side are the drain 15 (or source) connected to the common input terminal IN, and there is a first-layer ohmic metal layer 10 below it. The drain 16 (or source) is formed. The two electrodes are arranged in the shape of comb teeth meshing with each other, and the gate 17 formed by the second gate metal layer 20 is arranged on the channel region 12 in a comb shape.

Fig. 11(B) shows a partial cross-sectional view of the FET. On the substrate 11, an n+ type high-concentration region forming an n-type channel region 12 and a source region 18 and a drain region 19 are formed on both sides thereof. The drain 14 and the source 16 are formed by the first ohmic metal layer 10 . Furthermore, as described above, the drain 13 and the source 15 formed of the third pad metal layer 30 are provided, and the wiring of each element is performed.

In the above-mentioned compound semiconductor switch circuit device, in order to minimize the insertion loss of FET1 and FET2, a design method is employed in which the gate width Wg is increased to reduce the on-resistance of the FETs. For this reason, the sizes of FET1 and FET2 are increased due to the large gate width, so that product development is directed toward increasing the chip size.

In addition, in the compound semiconductor switching circuit device, a GaAs substrate of a semi-insulating substrate is used, and thermally pressed directly as a wiring of a conductive line or a pad of a bonding wire is provided thereon. However, since the signal to be processed is a high-frequency signal in the GHz band, it is necessary to provide a separation distance of 20 μm or more for isolation between adjacent wirings. The isolation required for the compound semiconductor switching circuit device is 20 dB or more. Experimentally, in order to ensure the isolation of 20 dB or more, a separation distance of 20 μm or more is necessary.

Although the theoretical basis is not too sufficient, it is still considered that the withstand voltage of the semi-insulating GaAs substrate should be infinite from the perspective of the insulating substrate. However, it is found from the actual measurement that its withstand voltage is limited. Therefore, it is considered that in the semi-insulating GaAs substrate, when the depletion layer extends to the electrode adjacent to the depletion layer due to the change in the distance from the high-frequency signal corresponding to the depletion layer, leakage of high-frequency signals will occur . Therefore, it can be inferred that a separation distance of 20 μm or more is necessary to ensure an isolation of 20 dB or more.

As can be seen from FIG. 10, in the prior compound semiconductor switching circuit device, pads corresponding to the common input terminal IN, output terminals OUT1, OUT2, control terminals Ctl-1, Ctl-2, and ground terminal GND are provided on the substrate. around. Forming the wiring layer at least 20 μm away from the pad will lead to a further increase in chip size.

In the above-mentioned compound semiconductor switch circuit device, in order to make the insertion loss of FET1 and FET2 as small as possible, the gate width Wg is made larger to reduce the on-resistance of FET, so the size of FET becomes larger. , In addition, in order to ensure the isolation performance of the pad and wiring layer during design, a separation distance of 20 μm is necessary.

Therefore, in the conventional compound semiconductor switching circuit device, the direction of increasing the chip size is increasingly being developed. As long as the GaAs substrate, which is more expensive than the silicon substrate, is used, the compound semiconductor switching circuit device has the advantage of being cheap. The trend of silicon chip replacement, which will bring the result of losing the market.

Contents of the invention

The present invention is proposed in view of the above-mentioned various matters, and its object is to reduce the size of the FET by shortening the gate width, and at the same time, shorten the distance between the pad and the wiring layer, thereby realizing a compound with a small chip size. Semiconductor switching circuit devices.

According to the present invention, a compound semiconductor switching circuit device, the first and second FETs with source, gate and drain are formed on the surface of the channel layer provided on the semi-insulating substrate, and the sources of the two FETs are The pole or drain is used as a common input terminal, and the drain or source of the two FETs are used as the first and second output terminals, and a control signal is applied to the control terminals respectively connected to the gates of the two FETs to turn on any FET. And form a signal path between the above-mentioned common input terminal and the above-mentioned first output terminal or the second output terminal, it is characterized in that:

Pads serving as the common input terminals, the first and second output terminals, and the control terminals are provided on the semi-insulating substrate, and a high concentration In the region, the distance between the pad and other circuit patterns of the compound semiconductor switching circuit device directly provided on the semi-insulating substrate is 20 μm or less. Description of drawings:

Fig. 1 is a circuit diagram for explaining the present invention.

Fig. 2 is a plan view for explaining the present invention.

Fig. 3 is a characteristic diagram for explaining the present invention.

Fig. 4 is a characteristic diagram for explaining the present invention.

Fig. 5 is a characteristic diagram for explaining the present invention.

Fig. 3 is a sectional view for explaining the present invention.

Fig. 7 is (A) a sectional view and (B) a circuit diagram for explaining a conventional example.

Fig. 8 is an equivalent circuit diagram for explaining the prior art.

Fig. 9 is a circuit diagram for explaining a prior example.

Fig. 10 is a plan view for explaining the prior art.

Fig. 11 is a plan view (A) and a sectional view (B) for explaining a conventional example.

Detailed ways

Next, an embodiment of the present invention will be described with reference to FIGS. 1 to 6 .

FIG. 1 is a circuit diagram showing a compound semiconductor switching circuit device of the present invention. The sources (or drains) of the first FET1 and the second FET2 are connected to the common input terminal IN, the gates of the FET1 and FET2 are respectively connected to the first and second control terminals Ctl-1 and Ctl-2 via resistors R1 and R2, and , the drains (or sources) of FET1 and FET2 are connected to the first and second output terminals OUT1 and OUT2. The control signals added to the first and second control terminals Ctl-1 and Ctl-2 are complementary signals, which make the FET with H level turned on, and transmit the input signal added to the common input terminal IN to a certain output terminals. Resistors R1 and R2 are configured to prevent the high-frequency signal from leaking through the grid to the DC potential of the control terminals ctl-1 and ctl-2 that are grounded to the AC.

The circuit shown in FIG. 1 is roughly the same as the circuit structure of the principle circuit of the compound semiconductor switch circuit device called SPDT (Single Pole Double Throw) using GaAs shown in FIG. 7(B). The biggest difference is that the FET1 And the gate width Wg of FET2 is designed below 700 μm and the distance between the pad and the wiring layer is greatly shortened.

The narrower gate width Wg means that the on-resistance of the FET is larger, and it means that the parasitic capacitance caused by the spot bond contact between the gate and the channel region is small because the gate area (Lg×Wg) is small , there will be a large deviation in the circuit operation.

In addition, greatly shortening the distance between the pad and the wiring layer contributes to reducing the size of the compound semiconductor switching circuit device.

FIG. 2 shows an example of a compound semiconductor chip in which the compound semiconductor switching circuit device of the present invention is integrated.

On the GaAs substrate, FET1 and FET2 for switching operation are arranged in the center, and resistors R1 and R2 are connected to the gates of the respective FETs. In addition, pads corresponding to the common input terminal IN, output terminals OUT1, OUT2, and control terminals Ctl-1, Ctl-2 are provided around the substrate. In addition, the second-layer wiring shown by the dotted line is the gate metal layer (Ti/Pt/Au) 20 formed at the same time as forming the gate of each FET, and the third-layer wiring shown by the solid line is for connecting each element. and pad metal layer (Ti/Pt/Au) 30 formed for the pad. The ohmic metal layer (AuGe/Ni/Au) 10 that is in ohmic contact with the first layer of substrate is the metal layer that forms the source, gate, and lead-out electrodes at both ends of each FET. In FIG. 2, in order to protrude from the pad The metal layer is not shown in the figure.

It can be seen from Fig. 2 that the constituent parts only have pads corresponding to FET1, FET2, resistors R1, R2, common input terminals IN, output terminals OUT1, OUT2, and control terminals Ctl-1, Ctl-2, which is the same as that of the prior art shown in Fig. 10 Compared with the compound semiconductor switching circuit device, it is constructed with the fewest components.

In addition, in the present invention, since FET1 is formed with a gate width of 700 μm or less which is half of that of the past (the same is true for FE), FET1 is only half as large as in the past. That is, the FET1 shown in FIG. 2 is formed on a rectangular channel region 12 surrounded by a dashed-dotted line. The three comb-shaped third-layer pad metal layers 30 extending from the lower side are the source 13 (or drain) connected to the output terminal OUT1, and there is a source formed by the first-layer ohmic metal layer 10 below it. pole 14 (or drain). In addition, the three comb-tooth-shaped third-layer pad metal layers 30 extending from the upper side are the drain 15 (or source) connected to the common input terminal IN, and there is a first-layer ohmic metal layer 10 below it. The drain 14 (or source) is formed. The two electrodes are arranged in the shape of comb teeth meshing with each other, and the gate 17 formed by the second gate metal layer 20 is arranged in the shape of four comb teeth on the channel region. In addition, the drain 13 (or source) of the middle comb extending from the upper side is shared by FET1 and FET2, which can further reduce the size. Here, the gate width being 700 μm or less means that the sum of the gate widths of the comb-shaped gates 17 of each FET is 700 μm or less.

Since the cross-sectional structures of FET1 and FET2 are the same as the conventional structure shown in FIG. 11(B), description thereof will be omitted.

Next, explain whether a design that omits the shunt FET can ensure isolation performance at high frequencies above 2.4GHz.

FIG. 3 shows the relationship between the gate width Wg and the insertion loss when the gate length Lg of the FET is 0.5 μm.

If the gate width Wg is reduced from 1000μm to 600μm when the input signal is 1GHz, the insertion loss will change from 0.35dB to 0.55dB, thereby increasing 0.2dB. However, if the gate width Wg is reduced from 1000μm to 600μm when the input signal is 2.4GHz, the insertion loss will change from 0.60dB to 0.65dB, an increase of only 0.05dB. From this, it can be seen that when the input signal is 1 GHz, the insertion loss is greatly affected by the on-resistance of the FET, but when the input signal is 2.4 GHz, the insertion loss is hardly affected by the on-resistance of the FET.

This is because the 2.4GHz input signal has a higher frequency than the 1GHz input signal, and the influence of the capacitance component due to the gate of the FET is greater than the influence due to the on-resistance of the FET. Therefore, for high frequencies above 2.4MHz, if the capacitance component has a greater influence on the insertion loss than the on-resistance of the FET, instead of reducing the on-resistance, it is better to focus on reducing the capacitance component during design. That is, it is necessary to consider the completely opposite idea from the past design.

On the other hand, FIG. 4 shows the relationship between the gate width Wg and the isolation when the gate length Lg of the FET is 0.5 μm.

If the gate width Wg is reduced from 1000μm to 600μm when the input signal is 1GHz, the isolation will change from 19.5dB to 23.5dB, which can be improved by 4.0dB. If the gate width Wg is reduced from 1000μm to 600μm when the input signal is 2.4GHz, the isolation will change from 14dB to 18dB, which can also be improved by 4.0dB. That is, the degree of isolation is improved depending on the on-resistance of the FET.

Therefore, it can be seen from Figure 3 that for high frequencies above 2.4MHz, if the insertion loss is only slightly increased, it is better to give priority to the isolation shown in Figure 4 during design, which can reduce the size of the compound semiconductor chip. That is, when the input signal is 2.4 MHz, the gate width Wg is 700 μm or less, and an isolation of 16.5 dB or more can be ensured, and when the gate width is 600 μm or less, an isolation of 18 dB or more can be secured.

Specifically, in the compound semiconductor switching circuit device of the present invention whose actual circuit pattern is shown in FIG. 2, FET1 and FET2 having a gate length Lg of 0.5 μm and a gate width of 600 μm are designed to ensure an insertion loss of 0.65 μm. dB, the isolation is 18dB. This feature can be used as a 4GHz ISM band (industrial, scientific and medical frequency band) to effectively utilize the communication switch in the spectrum diffusion communication application field.

Next, a case where the distance between the pad and the wiring layer is significantly reduced will be described.

2 and 6 show pad structures of the compound semiconductor switching circuit device of the present invention. As shown in the plan view of FIG. 2, five pads common to the input terminal IN, output terminals OUT1, OUT2, and control terminals Ctl-1, Ctl-2 are arranged around the substrate. The features of each pad are as shown in Figure 6, by the n+ type high concentration region 40 (indicated by double dotted line in Figure 2) arranged along its periphery on the substrate 11, most of the pads arranged on the substrate 11 A gate metal layer 20 and a pad metal layer 30 overlapping on the gate metal layer 20 are formed. The high concentration region 40 is formed simultaneously in the ion implantation process for forming the source region and the drain region. Accordingly, the bonding wire 41 of gold is ball-bonded on the pad metal layer 30 of the pad.

Therefore, unlike the case where all pads are formed directly on the substrate 11 in the past, the high-concentration region 40 is provided on the surface of the substrate below the peripheral portion of the pad. Therefore, unlike the surface of the undoped substrate 11 (although it is semi-insulating, the substrate resistance value is 1×10 ⁷ Ω·cm), due to the high impurity concentration (the ion type is 29Si ⁺ , the concentration is 1 to 5×10 ⁸ cm ^-3 ) does not extend to the depletion layer at the periphery of the pad, so the distance between the pad and the adjacent wiring layer can be reduced from 20 μm to 5 μm, which ensures 20 dB isolation.

Specifically, as can be seen from FIG. 2, except for the upper side, the pads of the common input terminal IN are provided with high-concentration regions 40 along its three sides, and the pads of the output terminals OUT1 and OUT2 are arranged in a C-shape along its four sides. In the high-concentration region 40, only the corners of the GaAs substrate remain, and the pads of the control terminals Ct11 and Ct12, except the corners of the GaAs substrate and the connection parts of the resistors R1 and R2, form a letter C along the four sides of the irregular pentagon The shape sets the high concentration region 40 . The portion without the high-concentration region 40 is a portion facing the periphery of the GaAs substrate. Even if the depletion layer is widened, there is a sufficient distance between adjacent pads and wiring, and this is a portion where there is no leakage problem.

Therefore, since the five pads occupy nearly half of the semiconductor chip, if the pad structure of the present invention is adopted, wiring layers can be arranged near the pads, which contributes to reducing the size of the semiconductor chip.

As a result, the compound semiconductor chip of the present invention can be downsized to 0.37×0.30 mm ² . This means that the size of compound semiconductor chips can actually be reduced by 20% compared with past compound semiconductor chips.

Furthermore, in the compound semiconductor switching circuit device of the present invention, various improvements in circuit characteristics are achieved. First, the voltage standing wave ratio VSWR, which represents the reflection of the switch to high-frequency input power, has reached 1.1 to 1.2. VSWR represents the ratio of the maximum value to the minimum value of the voltage standing wave generated between the reflected wave and the incident wave that occurs in the discontinuous part of the high-frequency transmission line. In an ideal state, VSWR=1, which means that the reflection is 0. In the conventional compound semiconductor switching circuit device having a shunt FET, VSWR=1.4 or so, and the present invention greatly improves the voltage standing wave ratio. This is because, in the compound semiconductor switching circuit device of the present invention, there are only FET1 and FET2 used as switches in the high-frequency transmission line, and the circuit is simple, and only FETs with an extremely small element size are used.

Second, the linear characteristic P _in 1dB representing the distortion level of the output signal relative to the high-frequency input signal has achieved 30dBm. Figure 5 shows the linear characteristics of the input and output power. The power ratio of input to output is ideally 1, but the output power decreases due to insertion loss. Because the output power is distorted when the input power is large, the point at which the output power drops 1dB relative to the input power is expressed as P _in 1dB. In the compound semiconductor switching circuit device with a shunt FET, P _in 1dB was 26dBm, but in the compound semiconductor switching circuit device without a shunt FET, P _in 1dB was 30dBm, an improvement of about 4dB or more. This is because, affected by the pinch-off voltage of the FET, for the case with a shunt FET, it is the result of multiplying the pinch-off switching FET and the shunt FET, while for the case of the present invention without a shunt FET, Only pinched switching FETs are affected.

Invention effect

As described above, according to the present invention, the following various effects can be obtained.

First, for the high frequency above 2.4GHz, focus on ensuring the isolation and save the shunt FET in the design, use the reverse thinking method, consider the effect of reducing the on-resistance of the FET used in the past from two aspects, and use the switch The gate width Wg of FET1 and FET2 is designed to be 700 μm or less. As a result, the size of the switching FET1 and FET2 can be reduced, the insertion loss can be suppressed to be small, and the isolation can be ensured.

The 2nd, in the compound semiconductor switch circuit device of the present invention, because can realize the design that omits shunt FET, so constituent parts only have and FET1, FET2, resistance R1, R2, common input terminal IN, output terminal OUT1, OUT2, The pads corresponding to the control terminals Ctl-1 and Ctl-2 have an advantage that they can be configured with the minimum number of components as compared with the conventional compound semiconductor switching circuit device.

Third, by providing a high-concentration region on the periphery of the pad that occupies nearly half the size of the semiconductor chip, the pad and the adjacent wiring layer can be placed close to each other, and the distance can reach 5 μm, so it can be used in a small space. To ensure the coupling and withstand voltage of high-frequency signals, the chip size is greatly reduced.

The 4th, as mentioned above, can make semiconductor chip 20% smaller than the prior compound semiconductor switch circuit device by the minimum constituent parts and narrow the distance between pad and wiring layer, can greatly improve the contact with silicon semiconductor chip. price competitiveness. In addition, due to the small chip size, it can be packaged into a small package (SMCP6 size is 1.6mm×1.6mm×0.75mm) smaller than the existing small package (MCP6 size is 2.1mm×2.0mm×0.9mm).

Fifth, because the insertion loss does not increase even for high frequencies above 2.4MGz, it is possible to realize a design that ensures isolation performance even if the shunt FET is omitted. For example, with a 3Ghz input signal, even with a gate width of 300μm, sufficient isolation performance can be ensured without a shunt FET.

Sixth, in the compound semiconductor switching circuit device of the present invention, the voltage standing wave ratio VSWR indicating the reflection of the switch to high-frequency input power can be set to 1.1 to 1.2, and a switch with low reflection can be provided.

Seventh, in the compound semiconductor switch circuit device of the present invention, the linearity characteristic P _in 1dB indicating the distortion level of the output signal relative to the high-frequency input signal can be increased to 30dBm, and the linearity characteristic of the switch can be greatly improved.

Claims (6)

1. A compound semiconductor switch circuit device, the first and the second FETs with source, grid and drain are formed on the surface of the channel layer provided on the semi-insulating substrate, and the source or drain of the two FETs As the common input terminal, the drains or sources of the two FETs are used as the first and second output terminals, and a control signal is applied to the control terminals respectively connected to the gates of the two FETs to turn on any FET, and in the above A signal path is formed between the common input terminal and the above-mentioned first output terminal or the second output terminal, which is characterized in that: Pads serving as the common input terminals, the first and second output terminals, and the control terminals are provided on the semi-insulating substrate, and a high concentration In the region, the distance between the pad and other circuit patterns of the compound semiconductor switching circuit device directly provided on the semi-insulating substrate is 20 μm or less. 2. The compound semiconductor switching circuit device according to claim 1, wherein in the portions having the adjacent pads, the mutual peripheral portions are surrounded by the high-concentration regions. 3. The compound semiconductor switching circuit device according to claim 1, wherein a central portion of the pad is provided in contact with the semi-insulating substrate, and a bonding wire is fixed to the central portion of the pad. 4. The compound semiconductor switching circuit device according to claim 1, wherein the high-concentration region is a region formed simultaneously in the ion implantation process of the source region and the drain region. 5. The compound semiconductor switching circuit device according to claim 1, wherein a GaAs substrate is used as said semi-insulating substrate, and said channel layer is formed on the surface thereof. 6. The compound semiconductor switch circuit device as claimed in claim 1, wherein the first and second FETs are formed of gates in contact with the channel layer by spot bonding and source electrodes and drain electrodes in ohmic contact with the channel layer form.

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