CN1218400C - Field-effect transistor with neck-shaped channel and manufacturing method thereof - Google Patents

Abstract

A field effect transistor having a neck channel and a method of fabricating the same. The inventive FET with neck channel is a dual-gate MOSFET, which at least comprises: a channel between the source and the drain, wherein the channel is a neck-shaped structure with a thin middle and two wide ends, thereby avoiding short channel effect and simultaneously reducing the resistance value of the series channel; and a wrap-around spacer covering the channel and the active regions of the source and drain, thereby preventing silicidation of these regions. The manufacturing method of the present invention includes at least: forming a neck channel, a source electrode and a drain electrode on an SOI substrate or the like by photoetching and etching processes with an active area mask; and forming a wrapping gap wall after depositing the grid material layer.

Description

Field-effect transistor with neck-shaped channel and manufacturing method thereof

technical field

The invention relates to a field effect transistor (Field Effect Transistor; FET) with a necking channel and a manufacturing method thereof. In particular, it relates to a vertical double gate metal oxide half field effect transistor (MOSFET) with a neck channel and a manufacturing method thereof.

Background technique

In recent years, the semiconductor industry has developed vigorously, and integrated circuits have now developed into the field of Ultra Large Scale Integrated Circuit (ULSI). In order to pursue higher density, higher speed and lower power consumption integrated circuits, metal oxide semiconductor devices must continue to shrink. As the integration of semiconductor components increases, the short channel effect becomes more and more serious, so various metal oxide half field effect transistors are proposed to solve the problem of short channel effect (short channel effect), among which the double gate metal oxide half field The effect transistor is a device that has received considerable attention. The FINFET that has appeared in recent years is a vertical double-gate metal-oxide-semiconductor field-effect transistor that uses an ultra-narrow rectangular parallelepiped (called "FIN") channel to suppress the short channel effect.

Please refer to FIG. 1 . FIG. 1 is a schematic bottom view illustrating the channel structure of a conventional FINFET. The source 20 , the channel 80 and the drain 30 made of silicon material are formed on a barrier oxide 15 , and the barrier oxide 15 is formed on a substrate (not shown). The channel 80 is a cuboid, ie the width is the same from one end to the other. If the width of the channel 80 is narrower, the gate voltage (V _g ) can be more sensitively controlled on the drain current (I _d ), and the short channel effect can be prevented, and the subthreshold swing can be improved. However, in order to achieve the aforementioned effects, it is often necessary to use a rather narrow channel, such as tens of nanometers, and such a narrow channel 80 will cause the problem that the series channel resistance value (series channel resistance) is too large, causing problems in both design and use. Great difficulty. In addition, in the process of fabricating FINFET, when the metal silicidation step is performed, the narrow channel, especially the position connecting the source (source) and the drain (drain) is very easy to be damaged.

Therefore, it is very urgent to develop a channel structure that can not only effectively suppress the occurrence of short channel effects, increase the control sensitivity of the gate voltage to the drain current, improve the subthreshold swing, but also have a smaller series channel resistance value, To reduce the difficulty of design and use. In addition, the structure of the FINFET, especially the narrow channel, can be prevented from being damaged during the metal silicidation step.

Contents of the invention

In view of the above-mentioned background of the invention, the existing FINFET uses a rather narrow channel to increase the control sensitivity of the gate voltage to the drain current, and to prevent the short channel effect from occurring, and such a narrow channel will produce a series channel resistance value that is too large The problems caused great difficulties in both design and use. In addition, the structure of the FINFET, especially the narrow channel, is easily damaged when the metal silicidation step is performed on the existing FINFET.

Therefore, an object of the present invention is to provide a field effect transistor with a neck-shaped channel, so that when the control sensitivity of the gate voltage to the drain current is increased, the short channel effect is prevented, and the subthreshold swing is improved, At the same time, the series channel resistance value can be reduced.

Another object of the present invention is to provide a field effect transistor with a neck-shaped channel, wherein a wrap up spacer is formed before the metal silicidation step, so as to prevent the FINFET from being damaged during the metal silicidation step. Structures, especially narrow passages, were damaged.

Another object of the present invention is to provide a method for manufacturing a field effect transistor with a neck channel, which is used to effectively form a source, a drain, and a neck channel, as well as subsequent gates and surrounding spacers.

According to the above objectives of the present invention, the present invention therefore provides a field effect transistor with a neck channel and a manufacturing method thereof. The field effect transistor with neck-shaped channel of the present invention at least comprises: SOI (Silicon On Insulator) substrate or similar substrate structure, and wherein this substrate comprises silicon substrate, the barrier oxide layer (barrier oxide) that is formed on silicon substrate, and a silicon material layer formed on the barrier oxide layer; a source electrode, a drain electrode, and a neck-shaped channel connecting the source electrode and the drain electrode made of the silicon material layer, wherein the maximum width of the neck-shaped channel is located at both ends of the channel , and the minimum width is located in the middle of the channel; the gate is formed in the middle of the neck channel; and the wrapping spacer covers the active area of the channel and the source and drain.

In other words, the field effect transistor with a neck-shaped channel of the present invention at least includes: a substrate, wherein the substrate includes: a base material; a barrier oxide layer is formed on the base material; and a silicon material layer is formed on the barrier oxide layer; a source; a drain; a neck channel, wherein the neck channel is connected between the source and the drain, and the source, the drain and the neck channel are made of the silicon material layer, and the neck-shaped channel has a first width and a second width less than the first width, the first width is located at about one end and the other end of the neck-shaped channel, and the second width is located at about A middle position of the neck-shaped channel, the shape of the neck-shaped channel is gradually narrowed from the one end to the middle position, and then gradually expanded from the middle position to the other end; and a gate layer, wherein the gate layer forms At the middle position of the neck-shaped channel, the gate layer at least includes: a gate oxide layer formed on the surrounding side of the middle position of the neck-shaped channel; and a gate material layer deposited on the gate oxide layer .

In addition, the manufacturing method of the field effect transistor with neck-shaped channel of the present invention at least includes: providing a substrate, such as an SOI substrate, wherein the substrate includes a silicon substrate, a barrier oxide layer is formed on the silicon substrate, and a silicon material layer is formed on the barrier oxide layer; performing photolithography and etching processes on the silicon material layer with an active area mask (ODmask) to form a neck-shaped channel, source and drain; and forming a gate oxide layer in the middle of the neck-shaped channel around, where a hard mask layer (such as oxide or nitride) can also be formed over the middle of the channel, and then gate material, such as polysilicon or metal material, is deposited; deposition and etching processes are performed to form wrapping spacers, Such as oxide or nitride to cover the channel, and the active regions of the source and drain.

The main advantage of the present invention is to provide a field-effect transistor with a neck-shaped channel, which can simultaneously reduce the Series channel resistor. Moreover, the two ends of the channel of the present invention are wider, so it is not easy to be damaged by the metal silicide step.

Another advantage of the present invention is to provide a field effect transistor with a neck-shaped channel. The present invention forms a wrapping spacer before performing the metal silicidation step, so when performing the metal silicidation step, it is possible to avoid making the structure of the FINFET particularly narrow channel is damaged.

Another advantage of the present invention is to provide a method for manufacturing field effect transistors with neck channels, which can effectively form source, drain and neck channels, as well as subsequent gates and wrapping spacers.

Description of drawings

Preferred embodiments of the present invention will be described in more detail with the help of the following drawings in the following descriptive texts, wherein:

Fig. 1 is a schematic bottom view showing the channel structure of an existing FINFET;

2 is a schematic bottom view showing the channel structure of a field effect transistor with a neck-shaped channel according to the present invention;

3 is a schematic bottom view showing a field effect transistor with a neck channel of the present invention, wherein the spacer has not been formed yet;

4 is a schematic cross-sectional view (viewed from the direction A-A of FIG. 3 ) of a field effect transistor with a neck-shaped channel according to the present invention;

5 is a schematic bottom view illustrating a field effect transistor with a neck channel of the present invention, wherein a spacer has been formed; and

FIGS. 6A to 6D are schematic cross-sectional views (viewed from the direction B-B of FIG. 3 ) illustrating the process flow of the method for manufacturing a field effect transistor with a neck-shaped channel according to the present invention.

Explanation of symbols in the figure:

12 Substrate

15 Barrier oxide layer

18 Silicon material layer

20 source

30 Drain

80, 100 channels

102 Minimum width

104 Maximum width

200 Gate layer

220 Gate oxide layer

230 Hard mask layer

240 Gate material layer

320, 330, 340, 350 wrapped spacer

Detailed ways

The invention discloses a field effect transistor with a neck channel and a manufacturing method thereof. The so-called neck-shaped channel means that the channel between the source and the drain has a structure that is wide at both ends and thin in the middle, rather than the narrow and rectangular channel 80 of the existing FINFET as shown in FIG. 1 .

Please refer to FIG. 2 . FIG. 2 is a schematic bottom view illustrating a channel structure of a field effect transistor with a neck channel according to the present invention. One of the main features of the present invention is to provide a neck channel 100 with a central position of approximately minimum width 102 and two ends approximately of maximum width 104 . The neck channel 100 has a shape that gradually narrows from one end with the largest width 104 to a middle position with the smallest width 102 , and then gradually expands from the middle position with the smallest width 102 to the other end with the largest width 104 . The minimum width 102 can be, for example, about 10 nm to about 50 nm, so as to sufficiently achieve the goals of increasing the control sensitivity of the gate voltage to the drain current, improving the subthreshold swing, and preventing the occurrence of short channel effects. Simultaneously, because the maximum width 104 is arranged at both ends, its width is far greater than the minimum width 102, so compared with the thin rectangular channel 80 of the existing FINFET as shown in Figure 1, the field effect transistor with the neck channel of the present invention Channel 100 can greatly reduce the resistance value of the series channel. In addition, when the metal silicide step is performed to reduce the resistance value of the MOSFET, since the two ends of the channel 100 of the present invention are far wider than the two ends of the existing channel 80, the ability of the channel 100 to withstand damage It is also much higher than the existing channel 80.

Please refer to FIG. 3 and FIG. 4, FIG. 3 is a schematic bottom view showing a field effect transistor with a neck-shaped channel of the present invention, wherein the spacer has not yet been formed; and FIG. 4 shows a field effect transistor with a neck-shaped channel of the present invention A schematic cross-sectional view of a transistor (viewed in the direction of A-A in FIG. 3 ). The field effect transistor with neck channel of the present invention at least includes: a substrate, this substrate can be the substrate of SOI substrate or other similar structure, and wherein this substrate comprises substrate 12 such as silicon substrate, is formed on substrate 12 barrier oxide layer 15 , and a silicon material layer 18 formed on the barrier oxide layer 15 . The present invention also includes at least: a source 20, a drain 30, and a neck channel 100 connecting the source 20 and the drain 30 formed on the silicon material layer 18, wherein the neck channel 100 has an approximate maximum width at the neck Both ends of the neck-shaped channel 100, and its minimum width is located in the middle of the neck-shaped channel 100. The shape of the neck channel 100 is tapered from one end with about the largest width to an intermediate position with about the smallest width, and then gradually expanded from the middle position with about the smallest width to the other end with about the largest width. The present invention at least includes: the gate layer 200 is formed at the middle position of the neck-shaped channel 100, wherein the gate layer 200 at least includes: the gate oxide layer 220 is formed at the surrounding sides of the middle position of the neck-shaped channel 100, which can also be A hard mask layer 230 (such as oxide or nitride) is formed above the middle position of the neck channel 100; film layer 230 (optional).

Please refer to FIG. 5 . FIG. 5 is a schematic bottom view of a field effect transistor with a neck-shaped channel according to the present invention, where spacers have been formed. The field effect transistor with a neck-shaped channel of the present invention also at least includes: wrapping spacers 320, 330, 340 and 350, wherein the wrapping spacers 340 and 350 cover the neck-shaped channel 100, and the wrapping spacers 320 and 330 cover the source 20 and the active region of the drain 30 , and the surrounding spacers 320 , 330 , 340 and 350 can be made of, for example, silicon oxide or silicon nitride. When the metal silicidation step is performed to reduce the resistance value of the MOSFET, the wrapping spacers 340 and 350 can protect the channel 100, and the wrapping spacers 320 and 330 can protect the active regions of the source 20 and the drain 30, thereby The channel 100, and the active regions of the source 20 and drain 30 are prevented from being damaged.

In addition, please refer to FIG. 6A to FIG. 6D , which are cross-sectional schematic diagrams (viewed from the direction of B-B of FIG. 3 ) illustrating the process flow of the field effect transistor with a neck channel of the present invention. The manufacturing method of the field effect transistor with neck channel of the present invention at least includes the following steps. First, as shown in FIG. 6A, a substrate, such as an SOI substrate, is provided, wherein the formation method of the substrate includes providing a substrate 12 such as a silicon substrate; forming a barrier oxide layer 15 on the substrate 12; and forming a silicon material layer 18 on the barrier oxide layer 15 . Next, as shown in Figure 6B

As shown, the neck channel 100 , the source 20 and the drain 30 are formed by performing photolithography and etching processes on the silicon material layer with an OD mask. Then, as shown in FIG. 6C, a gate oxide layer 220 is formed on the surrounding sides of the middle position of the neck-shaped channel, wherein a hard mask layer 230 (such as: oxide or nitride) can also be formed above the middle position of the channel. back. Then, as shown in FIG. 6D, a gate material layer 240 (such as polysilicon or metal material) is deposited on the gate oxide layer 220 and the hard mask layer 230 (optional), followed by deposition and etching processes to form Wrapping spacers 340 and 350 cover the channel 100 , and wrapping spacers 320 and 330 cover the active regions of the source 20 and drain 30 . The wrapping spacers 320 , 330 , 340 and 350 can be oxides or nitrides, for example.

As those skilled in the art understand, the above descriptions are only preferred embodiments of the present invention, and are not intended to limit the patent scope of the present invention; all other equivalents that do not depart from the spirit disclosed by the present invention are completed Changes or modifications should be included within the scope of the claims.

Claims (10)

1. field-effect transistor with neck shape channel comprises at least:

One substrate, wherein this substrate comprises:

One base material;

One obstacle oxide layer is formed on this base material; And

One silicon material layer is formed on this obstacle oxide layer;

One source pole;

One drain electrode;

One neck shape channel, wherein this neck shape channel is connected between this source electrode and this drain electrode, and this source electrode, this drain electrode and this neck shape channel are made by this silicon material layer, and this neck shape channel has one first width and less than one second width of this first width, this first width is positioned at an end and the other end of this neck shape channel, this second width is positioned at a centre position of this neck shape channel, being shaped as by this end of this neck shape channel is contracted to this centre position gradually, is expanded to this other end gradually by this centre position again; And

One grid layer, wherein this grid layer is formed at this centre position of this neck shape channel, and this grid layer comprises at least:

One grid oxic horizon is formed at the peripheral side in this centre position of this neck shape channel; And

One gate material layers is deposited on this grid oxic horizon.

2. the field-effect transistor with neck shape channel as claimed in claim 1 is characterized in that: this field-effect transistor with neck shape channel also comprises at least:

A plurality of parcel clearance walls, wherein these parcel clearance walls cover the active area of this neck shape channel and this source electrode and this drain electrode.

3. the field-effect transistor with neck shape channel as claimed in claim 1 is characterized in that: this base material is a silicon substrate.

4. the field-effect transistor with neck shape channel as claimed in claim 1 is characterized in that: this substrate is the SOI substrate.

5. the field-effect transistor with neck shape channel as claimed in claim 1 is characterized in that: the material of this gate material layers is a polysilicon.

6. the field-effect transistor with neck shape channel as claimed in claim 1 is characterized in that: the material of this gate material layers is a metal material.

7. the field-effect transistor with neck shape channel as claimed in claim 2 is characterized in that: the material of these parcel clearance walls is a silica.

8. the field-effect transistor with neck shape channel as claimed in claim 2 is characterized in that: the material of these parcel clearance walls is a silicon nitride.

9. the manufacture method with field-effect transistor of neck shape channel is characterized in that, comprises at least:

One substrate is provided, and wherein the formation method of this substrate comprises:

One base material is provided;

Form an obstacle oxide layer on this base material; And

Form a silicon material layer on this obstacle oxide layer;

This silicon material layer is carried out photoetching and etch process forms a neck shape channel, one source pole and a drain electrode with the active area mask;

Form the peripheral side of a grid oxic horizon in a centre position of this neck shape channel; And

Deposit a gate material layers on this grid oxic horizon.

10. the manufacture method with field-effect transistor of neck shape channel as claimed in claim 9 is characterized in that: this manufacture method with field-effect transistor of neck shape channel also comprises at least:

Deposit with etch process to form the active area that a plurality of parcel clearance walls cover this neck shape channel and this source electrode and this drain electrode.

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