CN1218377C - Integrated circuit packaging device with heat dissipation wiring design - Google Patents

Abstract

An integrated circuit packaging device with heat dissipation wiring design is provided, wherein an integrated circuit chip is placed on a packaging substrate, a power supply ring structure is arranged around the chip, the power supply ring structure close to a high-heat energy area of the integrated circuit chip has a larger surface area so as to improve the contact area between the power supply ring structure and the packaging substrate, and the power supply ring structure is connected with an equipotential conducting layer of a multilayer circuit board through an electric circuit so as to improve the heat dissipation efficiency.

Description

Integrated circuit packaging device with heat dissipation wiring design

technical field

The invention relates to an integrated circuit chip packaging device, in particular to an integrated circuit chip packaging device with heat dissipation wiring design.

Background technique

In the manufacturing process of integrated circuits, multiple semiconductor chips are manufactured on the wafer. After the semiconductor process is completed, the die containing the semiconductor chips is cut from the wafer, and each die is a semiconductor component. . After obtaining the die, it is necessary to carry out the packaging process of the die, so that the semiconductor components on the die can operate independently on the packaging substrate. Then, fix the die on the packaging substrate. If it is a general packaging device, connect the semiconductor component and the packaging substrate with a wire bonding process. If it is a flip-chip packaging device, connect the semiconductor component and the packaging substrate with metal pads; finally , carry out the overall packaging process, and package the semiconductor components on the packaging substrate.

In the packaging process of integrated circuits, the design of the packaging substrate is determined according to the electrical characteristics or heat dissipation characteristics required by the semiconductor components.

As shown in FIG. 1 , it is a structural diagram of a core logic chip packaged and arranged on a motherboard according to the prior art, wherein the core logic chip 10 is placed on the upper surface of a substrate 11 , and the core logic chip 10 is connected by bonding wires 12 The signal input and output pads on the substrate 11 are connected to the ball pins 14 on the lower surface of the substrate 11 through the through holes 13 . However, because the number of power wires of the chip 10 is large, a power ring structure (power ring) 15 is arranged above the substrate 11, and a plurality of power wires 16 are connected to the power ring 15, and the power ring 15 passes through multiple power rings. Each through hole 17 is electrically connected with the lower ball pin 18 . A plastic cover 19 is provided around and above the substrate 11 to protect the core logic chip 10 itself. The core logic chip 10 is connected to the signal input and output wiring pads or the power supply ring structure of the package substrate 11 through bonding wires 12 or power supply wiring 16, then connects the ball pins 14, 18 through the metal plugs in the through holes 14, 17, and then electrically Connected to the motherboard 20 , the core logic chip 10 can be electrically connected to other circuit components on the circuit board 20 through this packaging device.

In the integrated circuit packaging device shown in Figure 1, a power supply ring structure is arranged on the packaging substrate 11, and the power supply ring structure is arranged on one side of the semiconductor chip. This structure is convenient for the power supply wire between the semiconductor chip and the power supply ring structure. Wiring process and simplified wiring on package substrate. However, setting the power ring structure on one side of the package substrate will greatly increase the thermal stress problem on the package substrate, because during the normal operation of the semiconductor chip, the power ring structure will generate heat due to a large amount of current. If the package substrate The poor heat dissipation effect or poor heat conduction effect will cause thermal stress on the packaging substrate to cause the packaging substrate to be distorted, or the semiconductor chip cannot operate normally due to the high temperature of the packaging substrate.

Therefore, heat dissipation efficiency has always been an important issue in the manufacture of semiconductor chips, especially on core logic chips with fast operating speed and high integration. If the heat dissipation efficiency of the chip is not good, the probability of failure will increase a lot. However, in the above-mentioned method of packaging the core logic chip and being arranged on the motherboard, the core logic chip is electrically connected to the package substrate through metal bonding wires, and the bottom of the core logic chip is connected to the package substrate, and the package substrate is connected to the package substrate with ball-shaped pads. Even if it is connected to the motherboard, it cannot effectively meet the actual demand for heat dissipation, and how to improve the defects of the above-mentioned technical means is a problem that needs to be solved at present. .

Contents of the invention

In order to solve the above problems, the object of the present invention is to provide an integrated circuit chip packaging device with a heat dissipation wiring design. The integrated circuit chip is placed on a package substrate, and a power ring structure is arranged around the integrated circuit chip. The high heat energy area, the power ring structure has a larger surface area, so that there is a larger contact area between it and the package substrate, so as to improve the heat dissipation performance.

Another object of the present invention is an integrated circuit chip packaging device with heat dissipation wiring design, which utilizes the electrical connection path between the packaging substrate and the computer motherboard to increase the contact area of the electrical connection path to improve heat dissipation performance.

Another object of the present invention is to provide an integrated circuit chip packaging device with heat dissipation wiring design, which uses a heat dissipation metal cover to protect the integrated circuit chip on the package substrate to improve heat dissipation performance.

According to the idea above, in the chip packaging device described in this application, the power ring is composed of a plurality of disconnected blocks, and the surface area of the block at the periphery of the area where the chip generates more heat energy is larger than that of other blocks.

Description of drawings

FIG. 1 shows a schematic diagram of a core logic chip package and an existing structure arranged on a motherboard;

FIG. 2 shows a top view of a preferred embodiment of an integrated circuit packaging device with heat dissipation wiring design according to the present invention;

FIG. 3 is a schematic cross-sectional side view of an integrated circuit package device with heat dissipation wiring design according to the present invention.

Explanation of symbols in the figure 10 core logic chip 11 Substrate 12 Signal Wiring 13 through holes 14 ball pins 15 Power ring structure 16 Power Wiring 17 through holes 18 Ball Pins 19 plastic cover 20 Motherboard 30 chips 31 Substrate 32 power ring 321, 322 blocks 36 Power Wiring 37 through holes 38 Ball Pins 39 Cover 391 heat dissipation metal cover 40 motherboard 41 through hole 42 Equipotential conductive layer

Detailed ways

The integrated circuit packaging device with heat dissipation wiring design of the present invention will be described in detail below with reference to the accompanying drawings.

As shown in FIG. 2 , it shows a schematic top view of a preferred embodiment of the chip package heat dissipation structure according to the present invention, wherein the chip 30 is placed on the top of the substrate 31, and the power ring 32 is composed of a plurality of blocks 321, 322. And in order to effectively enhance the heat dissipation function, the surface area of the peripheral block 321 in the area where the chip 30 generates more heat energy (in this example, the lower left area of the chip is the area with more heat generation) is larger than the surface area of other blocks 322. In this way, the lower left area of the chip with a higher temperature can effectively dissipate heat and maintain a better working temperature.

In addition, as shown in FIG. 3 , it is a schematic side view cross-sectional view of a preferred embodiment of the chip package heat dissipation structure according to the present invention, wherein the chip 30 is placed on the top of the substrate 31, and a plurality of power wires 36 on the chip 30 are connected to On the power ring (power ring) 32, the power ring 32 is then electrically connected to the ball pins 38 below through metal plugs in a plurality of through holes 37, and the electrical connection between the ball pins 38 and the motherboard 40 is completed. contact, the chip 30 can be electrically connected with other circuit components on the circuit board 40 . And in order to improve the heat dissipation function of the chip, the present invention is used to protect the outer cover 39 of the chip 30 to make the heat dissipation metal upper cover 391 with metal materials (such as metals such as aluminum), so that the chip and its heat dissipation can be effectively increased. The heat dissipation efficiency of the packaged device as a whole.

Moreover, in order to increase the heat dissipation area, the present invention also uses the metal plug of the through hole 41 on the circuit board 40 with a multilayer structure, and then the ball pin 38 and the equipotential conductive layer 42 (which can be arranged on the circuit board 40 ) connection to the power or ground plane) so that the chip can use these large-area potential conductive layers for heat dissipation. In a preferred embodiment of the present invention, the circuit board is a multi-layer circuit board with an equipotential conductive layer, and the circuit board can be a general computer motherboard.

Therefore, the substrate 31 passes through the power ring structure 32 around the chip 30 (as shown in FIG. 3 ), and generates more heat energy in the area of the chip 30 (such as the lower left corner of the chip shown in FIG. 2 ), and the power ring structure 321 ( As shown in Figure 2) has a larger surface area to increase the contact area between the substrate 31 and the power ring structure, and the power ring structure is connected to the ball pin 38 through the metal plug in the through hole 41, and is connected to the circuit board 40. The equipotential conductive layer 42 (as shown in FIG. 3 ) is used to enhance the heat dissipation efficiency of the substrate 31 . In other words, increasing the surface area of the power ring structure in the area around the chip to increase the contact area between the power ring structure and the packaging substrate will enhance the heat dissipation performance of the packaging substrate through the equipotential conductive layer of the circuit board.

In summary, the present invention changes the existing chip packaging device and uses the special structure of the lower circuit board to improve heat dissipation efficiency, thereby effectively solving the defects of the prior art, and the chip of the present invention can be a core logic chip ), and the multilayer circuit board is a computer motherboard, but the technical means of the present invention can be applied to other similar chip packaging devices, any deformation and modification of the present invention, as long as it does not depart from the spirit of the present invention , will be regarded as included in the scope of the present invention, and the scope of the present invention is defined by its claims.

Claims (9)

1. the packaging system of an integrated circuit (IC) chip, this packaging system comprises:

One substrate, its first surface is used to place this integrated circuit (IC) chip;

A plurality of spherical pins are arranged at second of this substrate; And

One power ring, this power ring of this first surface that is arranged at this substrate electrically connects by many power supply wirings and this chip, and finishes electric connection via a plurality of metal plug of passing this substrate with these spherical pins, it is characterized in that,

This power ring be centered around this integrated circuit (IC) chip around, and the surface area of this power ring around this integrated circuit (IC) chip produces the more zone of heat energy is greater than at other regional surface area.

2. packaging system as claimed in claim 1 is characterized in that, this power ring is made up of a plurality of mutual disjunct blocks, and produces the surface area of the block table area of the more regional periphery of heat energy greater than other block in this integrated circuit (IC) chip.

3. packaging system as claimed in claim 1 is characterized in that, covers a heat radiating metal loam cake above this substrate and this integrated circuit (IC) chip, to protect this integrated circuit (IC) chip and to strengthen the radiating effect of this integrated circuit (IC) chip.

4. packaging system as claimed in claim 3 is characterized in that, the material of this heat radiating metal loam cake is an aluminum metal.

5. packaging system as claimed in claim 1 is characterized in that, this integrated circuit (IC) chip is a core logic chipset.

6. packaging system as claimed in claim 1 is characterized in that, this substrate is electrically connected with a multilayer circuit board by this spherical pin.

7. packaging system as claimed in claim 6, it is characterized in that, this multilayer circuit board has an equipotential conductive layer and a plurality of open-work, and this spherical pin sees through these a plurality of open-works, and finish electric connection, and then make this integrated circuit (IC) chip can utilize this equipotential conductive layer to dispel the heat with an equipotential conductive layer in this multilayer circuit board.

8. packaging system as claimed in claim 7 is characterized in that, this equipotential conductive layer is a bus plane or a ground plane.

9. packaging system as claimed in claim 6 is characterized in that, this multilayer circuit board is a computer main frame panel.

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