CN121301167A - A debugging system and method for RISC-V and FPGA system-on-a-chip - Google Patents

Abstract

A debugging system and method for RISC-V and FPGA system-on-a-chip (SoC) is disclosed. The system includes a control module, a multiplexer, a debugging module, and a JTAG interface. The debugging module comprises a RISC-V DAP submodule and an FPGA TAP submodule. The control module acquires the debugging mode and sends corresponding debugging link configuration commands to the multiplexer. The multiplexer configures the signal routing paths of the two submodules to form a debugging link. The RISC-V DAP submodule debugs and generates debugging results when the debugging link routes debugging commands to it for RISC-V debugging. The FPGA TAP submodule debugs and generates debugging results when the debugging link routes debugging commands to it for FPGA debugging. Therefore, by configuring different signal routing paths, different debugging links are constructed, supporting multiple debugging modes and improving debugging flexibility.

Description

Debugging system and method for RISC-V and FPGA system level chip

Technical Field

The present invention relates to system level chip debugging technology, and is especially one kind of debugging system of RISC-V and FPGA system level chip.

Background

With the rapid development of the fields of embedded systems, internet of things, industrial control, intelligent terminals and the like, the requirements of the systems on safety, reliability and high performance are increasingly improved, and the evolution of a system-on-chip (SoC) platform to a heterogeneous integration direction is promoted.

Under the background, the debugging system is used as a key link for guaranteeing software development, fault diagnosis and system maintenance, and the flexibility of the debugging system is very important.

However, in the related art, the SoC debug system is built based on a fixed debug mode, and once the debug mode is determined, the system supports only the debug of the mode, so that flexibility is insufficient.

Disclosure of Invention

The embodiment of the application provides a debugging system of a RISC-V and FPGA system-level chip, which comprises a control module, a multiplexer, a debugging module and a JTAG interface, wherein the debugging module comprises a RISC-V DAP sub-module comprising a plurality of RISC-V debugging functions and an FPGA TAP sub-module comprising a plurality of FPGA debugging functions;

the control module is used for acquiring a debugging mode and sending a debugging link configuration instruction corresponding to the debugging mode to the multiplexer;

the multiplexer is used for configuring a signal routing path of the RISC-V DAP sub-module and a signal routing path of the FPGA TAP sub-module according to the debugging link configuration instruction so as to form a debugging link;

The RISC-V DAP submodule is used for debugging RISC-V according to the debugging command when the debugging link routes the debugging command to the submodule to debug RISC-V, and debugging RISC-V and generating a debugging result;

The FPGA TAP sub-module is used for debugging the FPGA according to the debugging command when the debugging link routes the debugging command to the sub-module to debug the FPGA, and the FPGA is debugged according to the debugging command to generate a debugging result.

The embodiment of the application provides a debugging method of a RISC-V and FPGA system-level chip, which is applied to the debugging system of the RISC-V and FPGA system-level chip, and comprises the following steps:

the control module acquires a debugging mode and sends a debugging link configuration instruction corresponding to the debugging mode to the multiplexer;

The multiplexer configures a signal routing path of the RISC-V DAP sub-module and a signal routing path of the FPGA TAP sub-module according to the debugging link configuration instruction to form a debugging link;

When the RISC-V DAP submodule routes the debugging command to the submodule to carry out RISC-V debugging, the RISC-V is debugged according to the RISC-V debugging function which is contained in the debugging command, and a debugging result is generated;

And when the FPGA TAP submodule routes the debugging command to the submodule to debug the FPGA, the FPGA TAP submodule debugs the FPGA according to the debugging command to call the contained FPGA debugging function and generates a debugging result.

The control module acquires a debugging mode, sends a debugging link configuration instruction corresponding to the debugging mode to the multiplexer, configures a signal routing path of the RISC-V DAP sub-module and a signal routing path of the FPGA TAP sub-module according to the debugging link configuration instruction to form a debugging link, and the RISC-V DAP sub-module is used for calling the RISC-V debugging function according to the debugging command when the debugging link routes the debugging command to the sub-module for debugging the RISC-V, debugging the RISC-V and generating a debugging result, and the FPGA TAP sub-module is used for calling the FPGA debugging function according to the debugging command and generating the FPGA debugging result when the debugging link routes the debugging command to the sub-module for debugging the FPGA. Therefore, the construction of different debugging links of signals is realized by configuring different signal routing paths, and the support of multiple debugging modes is realized, so that the debugging flexibility is greatly improved.

Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application. Other advantages of the application may be realized and attained by the structure particularly pointed out in the written description and drawings.

Drawings

The accompanying drawings are included to provide an understanding of the principles of the application, and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain, without limitation, the principles of the application.

FIG. 1 is a schematic diagram of a debug system of a RISC-V and FPGA system-on-chip according to an embodiment of the present application;

FIG. 2 is a schematic diagram of another exemplary embodiment of a debug system of a RISC-V and FPGA system-on-chip;

FIG. 3 is a schematic diagram illustrating a process of independent debug mode according to an embodiment of the present application;

FIG. 4 is a schematic diagram of a cascaded debug mode flow according to an embodiment of the present application;

FIG. 5 is a schematic diagram illustrating an operation process of a debug system according to an embodiment of the present application;

FIG. 6 is a schematic diagram of a cascade mode JTAG signal connection according to an embodiment of the present application;

FIG. 7 is a schematic diagram of a RISC-V DAP sub-module according to one embodiment of the present application;

FIG. 8 is a schematic diagram of an FPGA TAP sub-module according to an embodiment of the present application;

FIG. 9 is a flowchart of a method for debugging a system-on-chip RISC-V and FPGA according to an embodiment of the present application.

Detailed Description

The present application has been described in terms of several embodiments, but the description is illustrative and not restrictive, and it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible within the scope of the described embodiments. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are possible. Any feature or element of any embodiment may be used in combination with or in place of any other feature or element of any other embodiment unless specifically limited.

The present application includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The disclosed embodiments, features and elements of the present application may also be combined with any conventional features or elements to form a unique inventive arrangement. Any feature or element of any embodiment may also be combined with features or elements from other inventive arrangements to form another unique inventive arrangement. It is therefore to be understood that any of the features shown and/or discussed in the present application may be implemented alone or in any suitable combination. Accordingly, the embodiments are not to be restricted except in light of the attached claims and their equivalents. Further, various modifications and changes may be made within the scope of the appended claims.

Furthermore, in describing representative embodiments, the specification may have presented the method and/or process as a particular sequence of steps. However, to the extent that the method or process does not rely on the particular order of steps set forth herein, the method or process should not be limited to the particular sequence of steps described. Other sequences of steps are possible as will be appreciated by those of ordinary skill in the art. Accordingly, the particular order of the steps set forth in the specification should not be construed as limitations on the claims. Furthermore, the claims directed to the method and/or process should not be limited to the performance of their steps in the order written, and one skilled in the art can readily appreciate that the sequences may be varied and still remain within the spirit and scope of the embodiments of the present application.

The embodiment of the disclosure provides a debugging system of a RISC-V and FPGA system-level chip, as shown in FIG. 1, comprising a control module 10, a multiplexer 11, a debugging module 12 and a JTAG interface 13, wherein the debugging module 12 comprises a RISC-V DAP submodule 120 containing multiple RISC-V debugging functions and an FPGA TAP submodule 121 containing multiple FPGA debugging functions;

the control module 10 is configured to obtain a debug mode, and send a debug link configuration instruction corresponding to the debug mode to the multiplexer 11;

the multiplexer 11 is configured to configure a signal routing path of the RISC-V DAP submodule 120 and a signal routing path of the FPGA TAP submodule 121 according to the debug link configuration instruction to form a debug link;

The RISC-V DAP submodule 120 is configured to, when the debug link routes the debug command to the submodule to debug RISC-V, invoke the included RISC-V debug function according to the debug command, debug RISC-V and generate a debug result;

the FPGA TAP submodule 121 is configured to debug the FPGA and generate a debug result according to the debug command when the debug link routes the debug command to the submodule to debug the FPGA.

The control module may determine the debug mode by reading the configuration register values or external jumper status.

RISC-V debug functions included in the RISC-V DAP sub-module may include register access, memory access, breakpoint setting, single-step execution, run/pause control, exception and interrupt handling, multi-threaded debugging. The register access refers to a general register and a control status register of a read-write processor, the memory access refers to direct access to a memory (such as read-write data and instructions) through a system bus or an abstract command, the breakpoint setting refers to setting a breakpoint through a hardware trigger, the program execution is paused, the single-step execution refers to executing instructions one by one, the code logic is debugged, the running/pause control refers to remotely controlling the running status (such as pause and resume) of the processor, the exception and interrupt handling refers to managing exception and interrupt events during debugging, and the multi-thread debugging refers to supporting independent debugging on a plurality of hardware threads.

The FPGA debugging function included in the FPGA TAP sub-module can comprise signal capturing and analyzing, real-time monitoring and modifying, triggering and condition capturing, resource occupation analyzing and power consumption and temperature monitoring, wherein the signal capturing and analyzing means that internal signal waveforms (such as ILA, signalTap) are observed in real time, the real-time monitoring and modifying means that dynamic read-write registers (such as VIOs) are used for triggering data acquisition according to specific conditions (such as signal changes and error marks), the resource occupation analyzing means that the utilization conditions of resources such as a logic unit, a RAM, time sequence and the like are counted, and the power consumption and the temperature monitoring means that the chip voltage and the temperature are monitored in real time through hard cores such as XADC and the like.

The debugging command is used for indicating what RISC-V debugging is performed or for indicating what FPGA debugging is performed, and when the RISC-V DAP sub-module and the FPGA TAP sub-module call the included FPGA debugging functions according to the debugging command, the corresponding FPGA debugging functions are called according to the debugging command. For example, when the debug command is to perform register access to RISC-V, the RISC-V DAP sub-module invokes the included register access debug function to debug RISC-V and generate a debug result, and when the debug command is to perform resource occupation analysis to FPGA, the FPGA TAP sub-module invokes the included resource occupation analysis function to debug FPGA and generate a debug result.

The control module acquires a debugging mode, sends a debugging link configuration instruction corresponding to the debugging mode to the multiplexer, configures a signal routing path of the RISC-V DAP sub-module and a signal routing path of the FPGA TAP sub-module according to the debugging link configuration instruction to form a debugging link, and the RISC-V DAP sub-module is used for calling the RISC-V debugging function according to the debugging command when the debugging link routes the debugging command to the sub-module for debugging the RISC-V, debugging the RISC-V and generating a debugging result, and the FPGA TAP sub-module is used for calling the FPGA debugging function according to the debugging command and generating the FPGA debugging result when the debugging link routes the debugging command to the sub-module for debugging the FPGA. Therefore, the construction of different debugging links of signals is realized by configuring different signal routing paths, and the support of multiple debugging modes is realized, so that the debugging flexibility is greatly improved.

In an illustrative example, as shown in FIG. 2, the RISC-V DAP submodule 120 includes a first JTAG interface 120a, the FPGA TAP submodule 121 includes a second JTAG interface 121a, the debug modes include an independent debug mode and a cascaded debug mode, when the debug mode is the independent debug mode, the first JTAG interface 120a and the second JTAG interface 121a outgoing modes include a first outgoing mode and a second outgoing mode, the first outgoing mode refers to a mode in which the first JTAG interface 120a and the second JTAG interface 121a are both outgoing, and the second outgoing mode refers to a mode in which the first JTAG interface 120a is not outgoing and the second JTAG interface 121a is outgoing;

In the case that the debug mode is the independent debug mode, and the exit mode of the first JTAG interface 120a and the second JTAG interface 121a is the first exit mode, the debug link configuration instruction is a first independent debug link configuration instruction;

In the case that the debug mode is the independent debug mode, and the outgoing mode of the first JTAG interface 120a and the second JTAG interface 121a is the second outgoing mode, the debug link configuration instruction is a second independent debug link configuration instruction;

and under the condition that the debugging mode is the cascade debugging mode, the debugging link configuration instruction is a cascade debugging link configuration instruction.

In the independent debug mode, the outgoing modes of the first JTAG interface and the second JTAG interface include two kinds, namely a first outgoing mode and a second outgoing mode. The first extraction mode is suitable for the design of sufficient chip pin resources, wherein JTAG interfaces of the RISC-V DAP sub-module and the FPGA TAP sub-module are extracted outside the chip, and the second extraction mode is suitable for the design of limited pins (such as a small packaged chip), wherein JTAG interfaces of the RISC-V DAP sub-module are not extracted, and only JTAG interfaces of the FPGA TAP sub-module are extracted outside the chip. For the second exit mode, debugging of the RISC-V processor may be accomplished through the JTAG interface of the FPGA TAP sub-module.

The RISC-V DAP submodule on the PS side strictly conforms to the RISC-V Debug specification, the FPGA TAP submodule on the PL side strictly conforms to the IEEE 1149.1 standard, and when the cascade mode is to be realized, the cascade debugging mode is realized by the FPGA TAP submodule and the FPGA TAP submodule seamlessly through a multiplexer.

The hardware architecture is based on hierarchical modular design, and modularizes functions such as command analysis, data processing, state feedback and the like, thereby realizing an architecture which is easy to expand and maintain. The FPGA TAP sub-module supports boundary scan register, on-line monitoring and FPGA logic debugging, accords with IEEE 1149.1 standard, and ensures compatibility with external debugging tools and RISC-V DAP sub-modules.

In cascade mode, the TDI receives the RISC-V DAP TDO signal from the multiplexer, and the TDO returns the processing results to the external debug tool.

The multiplexer provided by the embodiment of the application supports dynamic routing of debugging signals, dynamically switches an independent mode and a cascade mode according to system configuration, ensures signal isolation of two sets of debugging interfaces and avoids switching interference, adopts a high-speed analog switch or a digital multiplexer to realize branching or series connection of TCK, TMS, TDI, TDO signals, and a built-in mode control logic dynamically determines a working mode through a preset register or external configuration input, supports on-line dynamic switching, and provides state feedback to upper-layer debugging software for confirming and adjusting the debugging mode.

In an exemplary embodiment, when the debug link configuration instruction is a first independent debug link configuration instruction, the first JTAG interface is used for connecting with a first debug tool, the second JTAG interface is used for connecting with a second debug tool, and the debug command comprises a first debug command initiated by the first debug tool for debugging RISC-V and a second debug command initiated by the second debug tool for debugging the FPGA;

the multiplexer configures the signal routing path of the RISC-V DAP sub-module and the signal routing path of the FPGA TAP sub-module according to the debug link configuration instruction to form a debug link, comprising:

The multiplexer configures a signal routing path conducted between the first JTAG interface and a first debugging tool and a signal routing path conducted between the second JTAG interface and a second debugging tool according to the first independent debugging link configuration instruction so as to form the debugging link;

the debugging link is used for routing the first debugging command to the RISC-V DAP sub-module through the first JTAG interface so that the RISC-V DAP sub-module can debug RISC according to the first debugging command, and routing the second debugging command to the FPGA TAP sub-module through the second JTAG interface so that the FPGA TAP sub-module can debug FPGA according to the second debugging command.

The independent debug mode flow may be as shown in FIG. 3, with the RISC-V DAP submodule outputting debug signals via a separate JTAG interface for use by standard RISC-V debug tools (e.g. OpenOCD). The FPGA TAP submodule is independently connected to another debugging interface for internal debugging and logic verification of the FPGA. The RISC-V DAP and the FPGA TAP respectively output standard debugging signals, and the debugging tools can be respectively connected and independently debugged. The modules are not connected in series by direct signals, so that the independence of the debugging process is ensured, and the development and the independent verification of the division of labor are facilitated.

In an exemplary embodiment, when the debug link configuration instruction is a second independent debug link configuration instruction, the second JTAG interface is used for connecting a third debug tool and a fourth debug tool, and the debug command comprises a third debug command initiated by the third debug tool for debugging RISC-V and a fourth debug command initiated by the fourth debug tool for debugging the FPGA;

the multiplexer configures the signal routing path of the RISC-V DAP sub-module and the signal routing path of the FPGA TAP sub-module according to the debug link configuration instruction to form a debug link, comprising:

The multiplexer is connected with the first JTAG interface and the second JTAG interface in series according to the second independent debugging link configuration instruction, and configures a signal routing path conducted between the second JTAG interface and the third debugging tool and the fourth debugging tool so as to form the debugging link;

The debugging link is used for routing the third debugging command to the RISC-V DAP sub-module through the second JTAG interface so that the RISC-V DAP sub-module can debug RISC according to the third debugging command, and routing the fourth debugging command to the FPGA TAP sub-module through the second JTAG interface so that the FPGA TAP sub-module can debug FPGA according to the fourth debugging command.

In an exemplary embodiment, when the debug link configuration command is a cascade debug link configuration command, the FPGA TAP submodule further includes a plurality of RISC-V debug functions, and when the debug link routes the debug command to the submodule to perform RISC-V debugging, the FPGA TAP submodule is further configured to invoke the included RISC-V debug functions according to the debug command to debug the RISC-V and generate a debug result;

The second JTAG interface is used for connecting a fifth debugging tool, and the debugging command comprises a fifth debugging command initiated by the fifth debugging tool and used for debugging RISC-V and FPGA, wherein the fifth debugging command comprises a first sub-debugging command and a second sub-debugging command, the first sub-debugging command is used for debugging RISC-V, and the second sub-debugging command is used for debugging FPGA;

the multiplexer configures the signal routing path of the RISC-V DAP sub-module and the signal routing path of the FPGA TAP sub-module according to the debug link configuration instruction to form a debug link, comprising:

The multiplexer is connected with the TDI of the fifth debugging tool and the TDI of the first JTAG interface according to the cascade debugging link configuration instruction, is connected with the TDO of the first JTAG interface and the TDI of the second JTAG interface, and is connected with the TDO of the second JTAG interface and the TDO of the fifth debugging tool to form the debugging link;

The debug link is configured to route a fifth debug command to the RISC-V DAP sub-module through the second JTAG interface, so that the RISC-V DAP sub-module parses the first sub-debug command therein, and route the parsed first sub-debug command and the parsed second sub-debug command to the FPGA TAP sub-module, so that the FPGA TAP sub-module debugs RISC-V according to the parsed first sub-debug command, and debugs the FPGA according to the second sub-debug command.

In the cascade debug mode, the entire SoC platform connects the Debug Access Port (DAP) on the RISC-V side and the Test Access Port (TAP) on the FPGA side in series through the internal signal route to form a unified JTAG chain, so that the external debug tool can access the PS (RISC-V) and PL (FPGA) parts in sequence only by accessing a single JTAG interface, as shown in fig. 4.

The operation process of the debugging system provided by the embodiment of the application, as shown in fig. 5, includes:

1. system power-on and global reset

After the system is powered on, PL (FPGA side) loads configuration files to finish FPGA initialization, and PS (processor side) enters a reset state to wait for starting.

2. Global reset release and system initialization completion

After global reset is released, all modules of the system are initialized.

3. Debug mode detection and selection

The system detects the current debug mode through an internal configuration register or an external jumper, and determines whether to adopt the cascade debug mode.

4. Initializing a debug control unit

And loading the corresponding DAP and TAP debugging firmware according to the detection result to complete the basic initialization of the debugging module.

5. Configuration Multiplexer (MUX)

According to cascading mode requirements, the internal multiplexer routes the TDO output signal of RISC-V DAP with the TDI input of FPGA TAP, while the TCK and TMS signals are distributed to the two modules in parallel.

6. Cascade debug link establishment

A continuous JTAG chain is formed through the multiplexer, namely TDI of an external debugging tool, RISC-V DAP, FPGA TAP and TDO of the external debugging tool are all connected, and unified debugging is realized.

7. External debug tool connection and online debugging

After the external debugging tool is connected to the unified JTAG interface of the system, a debugging command is started to be sent, and meanwhile, the online state monitoring module feeds back the debugging state, so that the stable and efficient operation of the whole debugging link is ensured.

The power-on and reset stage may include the following specific processes:

1. system power-up

After the system is powered on, both PS and PL are reset and initialized. The FPGA side completes initialization of the internal logic of the PL by loading the configuration file, wherein the initialization comprises a safe debugging system module.

2. Reset synchronization

And the cross-clock reset synchronizer is utilized to ensure that the RISC-V kernel and the FPGA debugging module are started in the same reset state.

The debug mode detection and selection stage may include:

1. pattern detection

The system detects the current debug mode at start-up through configuration registers (which may be configured by external jumpers or software):

and in an independent debugging mode, the RISC-V kernel and the FPGA respectively have independent JTAG debugging ports.

Cascade debugging mode, namely combining two parts of JTAG signals into a unified debugging chain through an internal multiplexer.

2. Bootloader environment initialization

The Bootloader initializes the debug system in the starting process, including loading debug controller firmware (DAP and TAP firmware), initializing signal route, and setting corresponding debug mode according to the detection result.

Debugging in cascaded debug mode may include:

1. Mode selection and initialization

After the system is powered on, each subsystem is initialized, and a control module reads a configuration register or detects an external jumper to determine a debugging mode. When configured in cascaded debug mode, the control unit instructs the multiplexer to cascade the debug signals of RISC-VDAP and FPGATAP.

2. Signal routing setup

After the system is started, a control unit of the debugging system determines a cascading mode through a configuration register, and the multiplexer is switched to a cascading working state. The external JTAG debugging signal is routed to a RISC-V DAP sub-module through a built-in digital multiplexer or a high-speed analog switch, TCK and TMS signals are distributed in parallel between the RISC-V DAP and the FPGA TAP to ensure synchronization, the TDO output of the RISC-V DAP is dynamically routed to the TDI input of the FPGA TAP through the internal multiplexer, the FPGA TAP sub-module processes the debugging command according to an IEEE 1149.1 state machine, and the command can be downloaded to the internal logic of the FPGA or directly returned to the debugging state, so that the complete data flow of the cascade debugging chain is realized.

3. Cascade test link establishment

In cascade mode, the entire debug chain is ordered from TDI of the external debug tool to RISCVDAP to FPGATAP to TDO of the external debug tool.

After switching to cascade mode, the multiplexer connects the TDO output of RISC-V DAP directly with the TDI input of FPGA TAP, while ensuring that The Clock (TCK) and mode select signal (TMS) in the link are delivered consistently to each module.

4. Debug command delivery and data return

The external debugging tool sends debugging command through JTAG chain, RISC-V DAP submodule receives and analyzes the command (such as read-write register, single step execution), stores the processing result in internal register and outputs through TDO, the signal is dynamically routed to TDI input of FPGA TAP submodule through internal multiplexer, after the FPGA TAP submodule processes the debugging command according to IEEE 1149.1 state machine, the result is output through its TDO and returned to TDO interface of external debugging tool through cascade chain. The debugging state monitoring module monitors the working state, signal integrity and data transmission delay of each node in real time, and ensures the integrity and low delay of link transmission.

In cascade mode, the main signals of the JTAG interface include TCK, TMS, TDI and TDO. The connection and routing of the signals is as follows:

TCK and TMS signals

The TCK (clock) and TMS (mode selection) signals provided by the external debugging tool are simultaneously distributed to the RISC-V DAP and FPGA TAP submodules by the internal distributor, so that synchronous work of the two parts is ensured. To ensure signal integrity, buffers and level shifters are typically added to the input of each module to accommodate different voltage domain requirements.

Cascade connection of TDI signals

In cascade mode, the TDI signal of the external debug tool is first fed into the TDI input of the RISC-V DAP sub-module. After the RISC-V DAP submodule processes the debugging command (analyzes the source of JTAG instruction), the TDO signal is output through the TDI input of the FPGA TAP submodule, and the TDO signal is automatically routed to the TDI input of the FPGA TAP submodule through an internal multiplexer. This connection procedure requires that the TDO signal transmission be guaranteed to be delay-free in timing, so a short path and appropriate clock buffer design is typically employed in internal signal routing.

Return of TDO signal

After receiving the debugging command, the FPGA TAP submodule outputs the debugging processing result through the TDO thereof, and the TDO output signal is directly sent back to a TDO interface of an external debugging tool. In the whole link, the transmission between each module TDO and TDI adopts cascade connection, so that the continuity of the data link is ensured.

The JTAG signal connection in cascade mode can be as shown in FIG. 6, the TDI signal of the external debugging tool firstly enters the RISC-V DAP sub-module, the TDO output of the DAP module is transmitted to the TDI input of the FPGA TAP sub-module after being routed by the multiplexer, and the TDO signal output after being processed by the FPGA TAP sub-module is returned to the external debugging tool to form a complete cascade debugging chain.

In an exemplary embodiment, the FPGA TAP submodule debugs RISC-V according to the parsed first sub-debugging command and debugs the FPGA according to the second sub-debugging command by a serial debugging mode and a parallel debugging mode;

The serial debugging mode is that the FPGA TAP sub-module firstly debugs the RISC-V according to the parsed first sub-debugging command, and then debugs the FPGA according to the second sub-debugging command after the RISC-V is debugged, or debugs the FPGA according to the second sub-debugging command, and then debugs the RISC-V according to the parsed first sub-debugging command after the FPGA is debugged;

The parallel debugging mode is that the FPGA TAP sub-module firstly debugs the RISC-V according to the parsed first sub-debugging command and debugs the FPGA according to the second sub-debugging command in the process of debugging the RISC-V, or debugs the FPGA according to the second sub-debugging command and debugs the RISC-V according to the parsed first sub-debugging command in the process of debugging the FPGA.

In an illustrative example, as shown in FIG. 2, the debug system further includes a debug status monitoring module 13;

The debug status monitoring module 13 is configured to detect the integrity of the debug link and monitor the status of the debug link.

The debugging state monitoring module monitors the working states of the RISC-V DAP and the FPGA TAP, signal integrity and data transmission delay in real time, captures error information and time sequence abnormality, and assists developers in quick positioning. The module is internally provided with a monitoring register and a counter, records key time sequence parameters and error events, feeds back monitoring data to a debugging tool through a JTAG additional channel or a UART and other special interfaces, and supports an error recovery mechanism of automatic retry or manual intervention.

In one illustrative example, as shown in FIG. 2, the debug system further includes buffer isolation circuitry 14;

The buffer isolation circuit 14 is used for isolating different power domains of a RISC-V side and an FPGA side, is also used for adding a low jitter clock buffer to TCK with frequency higher than a preset frequency threshold value, and is also used for adding edge alignment logic to parallel TDI/TMS at an input end.

In an illustrative example, as shown in FIG. 2, the debug system further includes synchronizer circuit 15;

The synchronizer circuit 15 is configured to synchronize TMS and TDI of the first JTAG interface to an FPGA side clock domain before the parsed first sub-debug command is transmitted to the FPGA TAP sub-module.

The hardware architecture of the RISC-V DAP sub-module in the debugging system of the RISC-V and FPGA system level chip provided by the embodiment of the application can be shown as shown in figure 7 based on hierarchical modular design, and comprises a command analysis and control logic, a data processing unit, a high-speed bus interface, a JTAG standard signal, a main stream debugging tool seamless docking, wherein the command analysis and control logic is realized by adopting a finite state machine and is used for analyzing JTAG commands of an external debugging tool and controlling the state of a kernel, the data processing unit is used for supporting register read-write and memory access with the RISC-V kernel, the FIFO buffer and the internal register are used for storing and buffering debugging data to ensure transmission stability, the high-speed bus interface is used for realizing high-speed data exchange with the kernel through an AXI Lite or a special debugging bus and is used for providing TDI, TDO, TCK and TMS standard signals, the JTAG standard interface is completely compatible with the RISC-V Debug specification and supporting the seamless docking with the main stream debugging tools, such as OpenOCD and GDB.

The structure of the FPGA TAP sub-module in the debugging system of the RISC-V and FPGA system level chip provided by the embodiment of the application adopts a modularized design, supports high-efficiency and low-delay boundary scanning operation, realizes the on-line capturing of the internal signals of the FPGA, and ensures the seamless connection with the RISC-V DAP sub-module in a cascade debugging mode. The architecture of the FPGA TAP sub-module may be as shown in fig. 8, including a TAP controller based on IEEE 1149.1 standard for controlling state management and command processing, supporting state transitions of Test-Logic-Reset, run-Test/Idle, shift-DR, capture-DR, update-DR, and the like, a signal capturing unit integrating a boundary scan register and SCAN CHAIN for capturing and transmitting FPGA Logic signals, a dedicated signal buffer and isolation circuit for securing stability of debug data in a cascade mode, and a standard JTAG interface (TDI, TDO, TCK, TMS for connecting an external debug tool and RISC-V DAP sub-module.

In the related art, the debugging system of the SOC often has the following drawbacks:

1. Individual debug mode

The existing scheme is to design independent JTAG interfaces for RISC-V kernel and FPGA respectively, and the debugging of each module is convenient, but occupies more pins and resources in the actual product, and lacks unified view in the debugging process.

2. Cascading debug schemes but lacks flexibility

Some designs attempt to connect RISC-V with FPGA with fixed JTAG DAISY CHAIN, but it is difficult to compromise the compatibility of two different debug protocols (RISC-V DAP and FPGA TAP) with signal integrity, and debug mode is not flexibly switchable.

3. Insufficient standard compatibility

When the RISC-V debugging is realized by the current part of systems, the RISC-V Debug specification cannot be completely met, and meanwhile, the TAP design on the FPGA side also has the problem of poor butt joint with the industry standard, so that the debugging tool compatibility and the debugging efficiency are low.

The debugging system provided by the embodiment of the application designs a flexible and efficient debugging system aiming at a multi-core RISC-V and FPGA SoC platform, and comprises the following components:

1. multiplexer and mode control unit design

The system provides two debugging link connection modes of independent mode and cascade mode. In the cascade mode, the two debugging interfaces are connected in series and share a group of JTAG signal lines, so that the whole SoC platform is accessed through a single port. For this purpose, a dynamically switchable Multiplexer (MUX) and mode control logic are designed, in that firstly a mode selection pin or register (mode input/register) is added to the hardware, and the current operating mode is determined after a system reset or after control by software. The mode select signal drives an internal multiplexer, routing external JTAG signals (TCK, TMS, TDI) to different configurations of RISC-V side DAP and FPGA side TAP:

Independent mode-MUX enables JTAG port on FPGA side to be directly communicated with external debugger, RISC-V side DAP is isolated from external link, and independent channel is exposed to external for use by second debug chain. At this time, the respective debugging interfaces work independently, and the software can configure the DAP and the TAP respectively, so that compatibility with a single-device debugging tool is ensured.

Cascade mode-MUX connects RISC-V side DAP and FPGA side TAP in series, only one set of JTAG pins are open to external connections. For example, it can be designed as RISC-V DAP as the front end of the chain, FPGA TAP as the back end of the chain, and the TDI is accessed from outside to enter the DAP in turn to enter the TAP and finally output through the TDO. The link structure follows the IEEE 1149.1 daisy chain rules, ensuring that one interface can access debug ports on multiple chips.

In hardware implementation, the multiplexer may employ a tri-state buffer or a decode control gateway mode, where when the modes are switched to independent, the JTAG path of the RISC-V side DAP is opened or placed in bypass mode, the FPGA side TAP path is closed, and otherwise the two are interconnected. The mode control unit contains a simple state machine that upon receipt of a mode switch command, pauses the JTAG clock (TCK), resets the debugger chains (via TRST signals), then updates the MUX select bits, and finally re-enables the clock to resume communication. The mechanism for switching in the idle period prevents the race or damage of signals and ensures the compatibility and stable switching of interfaces. The mode can be determined by a hardware pin when reset is released, and can also be dynamically switched by a software write register, and all relevant TAPs/DAPs enter a safe bypass state in the switching process, so that undefined behaviors are avoided at the switching moment. In addition, to support the multi-core processor, link selection control logic can be introduced in front of the multiplexer, namely a link selection instruction register, a decoder and a multiplexer structure are added in the SoC chip, and the cores to be activated can be selected through specific JTAG instructions or command words. Thus, one JTAG port can debug a plurality of RISC-V cores in turn in a multiplexing mode, and the software and hardware coordinated debugging multiplexing is realized.

2. Cascade JTAG link structure design

In the cascade mode, a Debugging Access Port (DAP) on the RISC-V side and a Testing Access Port (TAP) on the FPGA side are physically connected in series through a JTAG link, so that a single port accesses the whole SoC platform. In particular routing, external JTAG plugs (CPU_TCK, CPU_TMS, CPU_TDI input, and CPU_TDO output) are connected to JTAG I/O pads on the FPGA side (e.g., FPGA_TCK, FPGA_TMS, FPGA_TDI, FPGA_TDO). In the internal design, the FPGA side TAP and the RISC-V side DAP are logically cascaded, wherein an FPGA side TDI signal is connected to the TDI input of the RISC-V DAP, the TDO of the RISC-V DAP is sent to an FPGA side TMS/TDI path through a MUX, and finally the TDO of the RISC-V DAP and the TDI of the FPGA TAP are connected in series to form an integral link. The clock TCK and mode TMS signals are fed directly from the outside both (distributed by MUX) and can be driven in parallel where necessary to ensure that the signals are delivered to both stages simultaneously. All JTAG chains share a group of clock and data lines, and all can be accessed by only one test port according to the daisy chain configuration of IEEE 1149.1 standard.

To ensure signal integrity and electrical compatibility, dedicated level isolation/buffer units are employed in the link design. Such as adding level shifters or cache drivers at the cross-domain connections to match signal standards between different supply voltages or domains and to ensure adequate drive capability. The clock lines (TCKs) are distributed with particular low offset clock buffers, avoiding transmission delays and timing skew. Meanwhile, proper resistors are added on the signal lines, so that impedance matching is realized, and reflection is reduced. The reset signal TRST may be two-stage isolated, i.e., external low level active reset is buffered by a set of flip-flops and then drives the reset pins of the DAP and TAP, respectively, to ensure that the cells recover to a known state during reset.

And the cascade link unified distribution mechanism is that external TCK and TMS inputs are firstly fed into RISC-V DAP and FPGA TAP in parallel through distribution logic. The TDO of RISC-V DAP is used as the intermediate node of serial chain and is transmitted to the TDI of FPGA TAP by internal MUX, while the TDO of FPGA TAP is used as the final output of whole chain and sent to callback tester. The entire link may also be configured with a link select ID or BYPASS register, allowing the debug tool to locate the devices of each layer in turn. After the design, no matter how many debugging ends (a plurality of DAPs of multi-core RISC-V or a plurality of TAPs inside an FPGA) are contained in the SoC, the debugging ends can be mapped into a serial JTAG chain (each stage of TAPs are sequentially linked through BYPASS or IDCODE) so as to realize single-port debugging access.

3. Signal isolation and link stabilization mechanism

In the cascade mode, the debugging signal passes through multiple sections of logic and power domains, and the risk of signal attenuation and timing mismatch is high. Therefore, a special buffer and isolation circuit and a timing adjustment mechanism are designed to improve the reliability. The method specifically comprises the steps of firstly isolating different power domains by using a bidirectional buffer or a digital isolator when TCK/TMS/TDI is transmitted in a cross-domain mode, avoiding power supply noise interference, and adding a low-jitter clock buffer for TCK with higher frequency to enhance driving capability and minimize clock skew. For parallel TDI/TMS data lines, edge alignment logic can be additionally arranged at the input end, so that the relative phase of TMS/TDI when entering each TAP can be adjusted, and race caused by different path time sequence differences can be avoided.

4. To solve the problem of synchronization across clock domains, a synchronization trigger (dual D trigger synchronizer) is added at the critical signal entry. Asynchronous JTAG command signals (e.g., chain select pulses) may be sample synchronized with a two-stage D flip-flop. The synchronizer circuit includes an SR latch that captures an input signal pulse and then resynchronizes to the local clock domain via a cascade of two D flip-flops, thereby generating a control pulse that is aligned with the local clock. The synchronization scheme ensures transparent conversion of JTAG control signals to the internal logic clock of the processor, and meta steady state is avoided.

5. In order to further enhance the link reliability, the system integrates a state monitoring module, and is responsible for detecting and debugging the link integrity and the TAP state on line. The module periodically sends IDCODE read or BYPASS diagnostic commands to the link and checks whether the IDCODE value returned by each level TAP matches a pre-configured expected value, quickly locating a link outage or equipment loss. At the same time, it can poll the state machine state of each TAP (by scanning the TMS sequence into a different TAP state for each TAP) to ensure that it is not in a no-response or error state. Upon detecting an exception (e.g., a link interrupt, TAP freeze, or return value error), the monitoring module reports the error to the master or debug management unit via an interrupt or status register, triggering a rollback measure (e.g., resetting the link, reestablishing the debug session).

The debugging system provided by the embodiment of the application realizes two debugging modes by integrating the DAP module of RISC-V standard and the TAP module of the FPGA side in the same SoC platform and adopting a flexible multiplexer and a mode control unit:

1. An independent debugging mode, namely debugging RISC-V and FPGA respectively, so that independent development and maintenance are facilitated;

2. and in the cascade debugging mode, a unified JTAG chain is formed through serially connecting debugging signals, and an external debugging tool is allowed to carry out integral debugging on the system through a single interface.

Wherein the mode switch control logic can be summarized as:

1. Configuration detection

The control unit reads the configuration register value or the external jumper state when the system is started to determine whether the debug mode is independent debug or cascade debug.

2. Signal switching

In cascade mode, the multiplexer is controlled to connect TDO of RISC-V DAP with TDI of FPGA TAP, and simultaneously distribute TCK and TMS signals to two modules in parallel.

In the switching process, the current debug chain state is reported to the upper layer debug software in real time through a built-in state feedback register, so that no signal loss or interference is ensured in the switching process.

3. On-line dynamic adjustment

The system supports the dynamic adjustment of the mode switching parameters through the debugging software in the running process, and adapts to different debugging requirements. For example, in the initial stage of system operation, the cascade mode is adopted to carry out overall debugging, and when a subsystem needs to be debugged respectively later, the system can be temporarily switched to the independent debugging mode.

The debugging system provided by the embodiment of the application has the following characteristics:

1. The flexible and efficient debugging capability is that two modes of independent debugging and unified cascade debugging of RISC-V and FPGA are supported, the development requirement of the system is met, the whole debugging of the system is facilitated, and the debugging efficiency and the system maintainability are greatly improved.

2. And in the cascade mode, the unified debugging of PS and PL can be realized by only a single debugging port, and the debugging pin and hardware resource consumption is effectively reduced.

3. Standard compatibility and usability that the system debugging module completely accords with RISC-V Debug standard and IEEE 1149.1 standard, supports mainstream debugging tools (such as OpenOCD, J-Link and the like) and improves the compatibility and usability of the debugging system.

4. The built-in debugging state monitoring and error detecting module can quickly feed back information when a debugging chain fails, and automatically start a retransmission or isolation mechanism, so that the stability and reliability of a debugging process are ensured.

5. Dynamic debugging mode switching and online optimization, namely supporting online dynamic switching of the debugging mode through a multiplexer and a mode control unit, adapting to different debugging scenes and facilitating later system upgrading and debugging strategy optimization.

The debugging system provided by the embodiment of the application can support a remote debugging mode based on a network and can replace the traditional single JTAG physical interface. The system adopts a networked debugging architecture through an integrated high-speed Ethernet interface, encapsulates debugging data and transmits the debugging data through a standard network protocol. The on-chip embedded Debug Agent is responsible for collecting Debug information of each module in the SoC and forwarding the Debug information to the Debug software of the host end through the network communication module, so that real-time monitoring, fault diagnosis and performance analysis of the running state of the chip are realized, the flexibility and remote accessibility of debugging are remarkably improved, and the method is particularly suitable for development and maintenance requirements of the complex SoC in the FPGA prototype verification or embedded deployment scene.

The debugging system provided by the embodiment of the application can also support a mixed debugging mode combined with a software debugging agent, and breaks through the limitation of the traditional pure hardware debugging modules (such as DAP and TAP). On the basis of maintaining a standard hardware debug interface, the system can integrate a software-implemented debug agent or debug middleware to provide debug functionality through a standard system interface (e.g. memory mapped I/O or dedicated communication channel). In the mode, the debugging command sent by the host end is transmitted to the software debugging agent embedded in the chip through the communication link, and the agent is responsible for analyzing the command and distributing the command to the corresponding debugging module, so that the operations of breakpoint control, register access, memory read-write, running state monitoring and the like of the target system are realized. The soft-hard cooperative debugging framework not only reduces the dependence on special hardware resources, but also improves the flexibility and expandability of the debugging function, and is suitable for complex SoC systems with limited resources or needing dynamic configuration.

The debugging system provided by the embodiment of the application can adopt a dynamic switching architecture based on programmable logic in the aspect of debugging signal routing, and breaks through the design limitation of the traditional fixed multiplexer. The reconfigurable characteristic of the FPGA is fully utilized, the fully soft nucleated debugging signal path configuration is realized through the programmable logic, and the connection topology and the working mode of the debugging chain are supported to be dynamically adjusted through software instructions during running. Specifically, the reconfigurable logic IP core can be deployed to replace a traditional static multiplexer, so that the routing of the debugging signals has the online reconfiguration capability, and flexible interconnection among different debugging modules, testing nodes or functional units is realized. The scheme remarkably improves the adaptability and the resource utilization rate of the debugging system, supports the remote debugging requirements of multiple scenes and modes, and provides highly customizable observability support for the complex SoC in different development and maintenance stages.

Corresponding to the debugging system of the RISC-V and the FPGA system-level chip, the embodiment of the application also provides a debugging method of the RISC-V and the FPGA system-level chip. As shown in fig. 9, the debugging method for RISC-V and FPGA system-level chip provided by the embodiment of the present application includes:

step 200, a control module acquires a debugging mode and sends a debugging link configuration instruction corresponding to the debugging mode to a multiplexer;

Step 210, the multiplexer configures the signal routing path of the RISC-V DAP sub-module and the signal routing path of the FPGA TAP sub-module according to the debugging link configuration instruction to form a debugging link;

Step 220, when the debug link routes the debug command to the submodule to carry out RISC-V debugging, the RISC-V is debugged according to the RISC-V debug function contained in the debug command, and a debug result is generated;

step 230, when the debug link routes the debug command to the submodule to debug the FPGA, the FPGA TAP submodule invokes the included FPGA debug function according to the debug command to debug the FPGA and generate a debug result.

Step 220 and step 230 belong to the relation of selecting execution or parallel execution, when the debug link routes the debug command to the submodule for RISC-V debugging, step 220 is executed, when the debug link routes the debug command to the submodule for FPGA debugging, step 230 is executed, when the debug bar routes the debug command to the submodule for RISC-V debugging, and steps 220 and 230 are executed when the debug command to the submodule for FPGA debugging.

In an exemplary embodiment, the RISC-V DAP submodule comprises a first JTAG interface, the FPGA TAP submodule comprises a second JTAG interface, the debugging modes comprise an independent debugging mode and a cascading debugging mode, when the debugging modes are independent debugging modes, the leading-out modes of the first JTAG interface and the second JTAG interface comprise a first leading-out mode and a second leading-out mode, the first leading-out mode refers to a mode in which the first JTAG interface and the second JTAG interface are led out, and the second leading-out mode refers to a mode in which the first JTAG interface is not led out and the second JTAG interface is led out;

Under the condition that the debugging mode is an independent debugging mode and the leading-out modes of the first JTAG interface and the second JTAG interface are the first leading-out modes, the debugging link configuration instruction is a first independent debugging link configuration instruction;

Under the condition that the debugging mode is an independent debugging mode and the leading-out modes of the first JTAG interface and the second JTAG interface are second leading-out modes, the debugging link configuration instruction is a second independent debugging link configuration instruction;

And under the condition that the debugging mode is a cascade debugging mode, the debugging link configuration instruction is a cascade debugging link configuration instruction.

In an exemplary embodiment, when the debug link configuration instruction is a first independent debug link configuration instruction, the first JTAG interface is used for connecting with a first debug tool, the second JTAG interface is used for connecting with a second debug tool, and the debug command comprises a first debug command initiated by the first debug tool for debugging RISC-V and a second debug command initiated by the second debug tool for debugging the FPGA;

The multiplexer configures the signal routing path of the RISC-V DAP sub-module and the signal routing path of the FPGA TAP sub-module according to the debug link configuration instruction to form a debug link, comprising:

The multiplexer configures a signal routing path conducted between the first JTAG interface and the first debugging tool and a signal routing path conducted between the second JTAG interface and the second debugging tool according to the first independent debugging link configuration instruction so as to form a debugging link;

The debugging link routes a first debugging command to the RISC-V DAP sub-module through a first JTAG interface so that the RISC-V DAP sub-module debugs the RISC according to the first debugging command, and routes a second debugging command to the FPGA TAP sub-module through a second JTAG interface so that the FPGA TAP sub-module debugs the FPGA according to the second debugging command.

In an exemplary embodiment, when the debug link configuration instruction is a second independent debug link configuration instruction, the second JTAG interface is used for connecting a third debug tool and a fourth debug tool, and the debug commands comprise a third debug command initiated by the third debug tool for debugging RISC-V and a fourth debug command initiated by the fourth debug tool for debugging the FPGA;

The multiplexer configures the signal routing path of the RISC-V DAP sub-module and the signal routing path of the FPGA TAP sub-module according to the debug link configuration instruction to form a debug link, comprising:

the multiplexer is connected with the first JTAG interface and the second JTAG interface in series according to the second independent debugging link configuration instruction, and configures a signal routing path conducted between the second JTAG interface and the third debugging tool and the fourth debugging tool so as to form a debugging link;

The debug link will route the third debug command to the RISC-V DAP sub-module through the second JTAG interface to cause the RISC-V DAP sub-module to debug the RISC according to the third debug command, and route the fourth debug command to the FPGA TAP sub-module through the second JTAG interface to cause the FPGA TAP sub-module to debug the FPGA according to the fourth debug command.

In an exemplary embodiment, when the debug link configuration command is a cascade debug link configuration command, the FPGA TAP submodule further includes a plurality of RISC-V debug functions, and when the debug link routes a debug command to the submodule to perform RISC-V debugging, the FPGA TAP submodule is further configured to invoke the included RISC-V debug functions according to the debug command to debug the RISC-V and generate a debug result;

The second JTAG interface is used for connecting a fifth debugging tool, wherein the debugging command comprises a fifth debugging command which is initiated by the fifth debugging tool and used for debugging RISC-V and FPGA, and the fifth debugging command comprises a first sub-debugging command and a second sub-debugging command, wherein the first sub-debugging command is used for debugging RISC-V, and the second sub-debugging command is used for debugging FPGA;

The multiplexer configures the signal routing path of the RISC-V DAP sub-module and the signal routing path of the FPGA TAP sub-module according to the debug link configuration instruction to form a debug link, comprising:

The multiplexer is connected with the TDI of the fifth debugging tool and the TDI of the first JTAG interface according to the cascade debugging link configuration instruction, and is connected with the TDO of the first JTAG interface and the TDI of the second JTAG interface and is connected with the TDO of the second JTAG interface and the TDO of the fifth debugging tool to form a debugging link;

The debugging link is used for routing a fifth debugging command to the RISC-V DAP sub-module through the second JTAG interface so that the RISC-V DAP sub-module analyzes the first sub-debugging command, and routing the analyzed first sub-debugging command and the analyzed second sub-debugging command to the FPGA TAP sub-module so that the FPGA TAP sub-module debugs the RISC-V according to the analyzed first sub-debugging command and debugs the FPGA according to the second sub-debugging command.

In an exemplary embodiment, the FPGA TAP submodule is used for debugging RISC-V according to the parsed first sub-debugging command and is used for debugging the FPGA according to the second sub-debugging command in a serial debugging mode and a parallel debugging mode;

The serial debugging mode is that the FPGA TAP sub-module firstly debugs the RISC-V according to the parsed first sub-debugging command, and then debugs the FPGA according to the second sub-debugging command after the RISC-V is debugged, or debugs the FPGA according to the second sub-debugging command, and then debugs the RISC-V according to the parsed first sub-debugging command after the FPGA is debugged;

The parallel debugging mode is that the FPGA TAP sub-module firstly debugs the RISC-V according to the parsed first sub-debugging command and debugs the FPGA according to the second sub-debugging command in the debugging process of the RISC-V, or debugs the FPGA according to the second sub-debugging command and debugs the RISC-V according to the parsed first sub-debugging command in the debugging process of the FPGA.

In an exemplary embodiment, the debug system further comprises a debug status monitoring module, the method further comprising:

the debug status monitoring module detects the integrity of the debug link and monitors the status of the debug link.

In an exemplary embodiment, the debug system further comprises a buffer isolation circuit, the method further comprising:

The buffer isolation circuit isolates different power domains of a RISC-V side and an FPGA side, adds a low jitter clock buffer to TCK with frequency higher than a preset frequency threshold, and adds edge alignment logic to parallel TDI/TMS at an input end.

In an exemplary embodiment, the debug system further comprises a synchronizer circuit, the method further comprising:

the synchronizer circuit synchronizes TMS and TDI of the first JTAG interface to the clock domain of the FPGA side before the parsed first sub-debugging command is transmitted to the FPGA TAP sub-module.

Those of ordinary skill in the art will appreciate that all or some of the steps, systems, functional modules/units in the apparatus, and methods disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components, for example, one physical component may have a plurality of functions, or one function or step may be cooperatively performed by several physical components. Some or all of the components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term "computer storage media" includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as known to those skilled in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. Furthermore, as is well known to those of ordinary skill in the art, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media.

Claims (10)

1. The debugging system of the RISC-V and FPGA system level chip is characterized by comprising a control module, a multiplexer, a debugging module and a JTAG interface, wherein the debugging module comprises a RISC-V DAP submodule containing multiple RISC-V debugging functions and an FPGA TAP submodule containing multiple FPGA debugging functions;

the control module is used for acquiring a debugging mode and sending a debugging link configuration instruction corresponding to the debugging mode to the multiplexer;

the multiplexer is used for configuring a signal routing path of the RISC-V DAP sub-module and a signal routing path of the FPGA TAP sub-module according to the debugging link configuration instruction so as to form a debugging link;

The RISC-V DAP submodule is used for debugging RISC-V according to the RISC-V debugging function which is contained in the debugging command when the debugging link routes the debugging command to the submodule to carry out RISC-V debugging, and debugging RISC-V and generating a debugging result;

The FPGA TAP sub-module is used for debugging the FPGA according to the debugging command when the debugging link routes the debugging command to the sub-module to debug the FPGA, and the FPGA is debugged according to the debugging command to generate a debugging result.

2. The debug system of claim 1, wherein the RISC-V DAP submodule comprises a first JTAG interface, the FPGA TAP submodule comprises a second JTAG interface, the debug modes comprise an independent debug mode and a cascaded debug mode, when the debug mode is the independent debug mode, the extraction modes of the first JTAG interface and the second JTAG interface comprise a first extraction mode and a second extraction mode, the first extraction mode is a mode in which the first JTAG interface and the second JTAG interface are both extracted, and the second extraction mode is a mode in which the first JTAG interface is not extracted and the second JTAG interface is extracted;

when the debug mode is the independent debug mode and the lead-out modes of the first JTAG interface and the second JTAG interface are the first lead-out modes, the debug link configuration instruction is a first independent debug link configuration instruction;

when the debug mode is the independent debug mode and the lead-out mode of the first JTAG interface and the second JTAG interface is the second lead-out mode, the debug link configuration instruction is a second independent debug link configuration instruction;

and under the condition that the debugging mode is the cascade debugging mode, the debugging link configuration instruction is a cascade debugging link configuration instruction.

3. The debug system of claim 2, wherein when the debug link configuration instruction is a first independent debug link configuration instruction, the first JTAG interface is used for connecting a first debug tool, the second JTAG interface is used for connecting a second debug tool, and the debug command comprises a first debug command initiated by the first debug tool for debugging RISC-V and a second debug command initiated by the second debug tool for debugging the FPGA;

the multiplexer configures the signal routing path of the RISC-V DAP sub-module and the signal routing path of the FPGA TAP sub-module according to the debug link configuration instruction to form a debug link, comprising:

The multiplexer configures a signal routing path conducted between the first JTAG interface and a first debugging tool and a signal routing path conducted between the second JTAG interface and a second debugging tool according to the first independent debugging link configuration instruction so as to form the debugging link;

the debugging link is used for routing the first debugging command to the RISC-V DAP sub-module through the first JTAG interface so that the RISC-V DAP sub-module can debug RISC according to the first debugging command, and routing the second debugging command to the FPGA TAP sub-module through the second JTAG interface so that the FPGA TAP sub-module can debug FPGA according to the second debugging command.

4. The debug system of claim 2, wherein when the debug link configuration instruction is a second independent debug link configuration instruction, the second JTAG interface is used for connecting a third debug tool and a fourth debug tool, and the debug command comprises a third debug command initiated by the third debug tool for debugging RISC-V and a fourth debug command initiated by the fourth debug tool for debugging the FPGA;

the multiplexer configures the signal routing path of the RISC-V DAP sub-module and the signal routing path of the FPGA TAP sub-module according to the debug link configuration instruction to form a debug link, comprising:

The multiplexer is connected with the first JTAG interface and the second JTAG interface in series according to the second independent debugging link configuration instruction, and configures a signal routing path conducted between the second JTAG interface and the third debugging tool and the fourth debugging tool so as to form the debugging link;

The debugging link is used for routing the third debugging command to the RISC-V DAP sub-module through the second JTAG interface so that the RISC-V DAP sub-module can debug RISC according to the third debugging command, and routing the fourth debugging command to the FPGA TAP sub-module through the second JTAG interface so that the FPGA TAP sub-module can debug FPGA according to the fourth debugging command.

5. The debug system of claim 2, wherein when the debug link configuration command is a cascading debug link configuration command, the FPGA TAP submodule further comprises a plurality of RISC-V debug functions, and wherein the FPGA TAP submodule is further configured to, when the debug link routes the debug command to the submodule for RISC-V debugging, invoke the included RISC-V debug functions according to the debug command, debug RISC-V and generate a debug result;

The second JTAG interface is used for connecting a fifth debugging tool, and the debugging command comprises a fifth debugging command initiated by the fifth debugging tool and used for debugging RISC-V and FPGA, wherein the fifth debugging command comprises a first sub-debugging command and a second sub-debugging command, the first sub-debugging command is used for debugging RISC-V, and the second sub-debugging command is used for debugging FPGA;

the multiplexer configures the signal routing path of the RISC-V DAP sub-module and the signal routing path of the FPGA TAP sub-module according to the debug link configuration instruction to form a debug link, comprising:

The multiplexer is connected with the TDI of the fifth debugging tool and the TDI of the first JTAG interface according to the cascade debugging link configuration instruction, is connected with the TDO of the first JTAG interface and the TDI of the second JTAG interface, and is connected with the TDO of the second JTAG interface and the TDO of the fifth debugging tool to form the debugging link;

The debug link is configured to route a fifth debug command to the RISC-V DAP sub-module through the second JTAG interface, so that the RISC-V DAP sub-module parses the first sub-debug command therein, and route the parsed first sub-debug command and the parsed second sub-debug command to the FPGA TAP sub-module, so that the FPGA TAP sub-module debugs RISC-V according to the parsed first sub-debug command, and debugs the FPGA according to the second sub-debug command.

6. The debugging system of claim 5, wherein the FPGA TAP submodule debugs RISC-V according to the parsed first subdebug command and debugs the FPGA according to the second subdebug command by a serial debug mode and a parallel debug mode;

The serial debugging mode is that the FPGA TAP sub-module firstly debugs the RISC-V according to the parsed first sub-debugging command, and then debugs the FPGA according to the second sub-debugging command after the RISC-V is debugged, or debugs the FPGA according to the second sub-debugging command, and then debugs the RISC-V according to the parsed first sub-debugging command after the FPGA is debugged;

The parallel debugging mode is that the FPGA TAP sub-module firstly debugs the RISC-V according to the parsed first sub-debugging command and debugs the FPGA according to the second sub-debugging command in the process of debugging the RISC-V, or debugs the FPGA according to the second sub-debugging command and debugs the RISC-V according to the parsed first sub-debugging command in the process of debugging the FPGA.

7. The debug system of any one of claims 1-6, wherein the debug system further comprises a debug status monitoring module;

The debugging state monitoring module is used for detecting the integrity of the debugging link and monitoring the state of the debugging link.

8. The debug system of claim 5, wherein the debug system further comprises buffer isolation circuitry;

the buffer isolation circuit is used for isolating different power domains of a RISC-V side and an FPGA side, is also used for adding a low jitter clock buffer to TCK with frequency higher than a preset frequency threshold value, and is also used for adding edge alignment logic to parallel TDI/TMS at an input end.

9. The debugging system of claim 5, wherein the debugging system further comprises a synchronizer circuit;

The synchronizer circuit is used for synchronizing TMS and TDI of the first JTAG interface to the clock domain of the FPGA side before the parsed first sub-debugging command is transmitted to the FPGA TAP sub-module.

10. A method for debugging a RISC-V and FPGA system-on-chip, applied to the RISC-V and FPGA system-on-chip debugging system according to any one of claims 1-9, said method comprising:

the control module acquires a debugging mode and sends a debugging link configuration instruction corresponding to the debugging mode to the multiplexer;

The multiplexer configures a signal routing path of the RISC-V DAP sub-module and a signal routing path of the FPGA TAP sub-module according to the debugging link configuration instruction to form a debugging link;

When the RISC-V DAP submodule routes the debugging command to the submodule to carry out RISC-V debugging, the RISC-V is debugged according to the RISC-V debugging function which is contained in the debugging command, and a debugging result is generated;

And when the FPGA TAP submodule routes the debugging command to the submodule to debug the FPGA, the FPGA TAP submodule debugs the FPGA according to the debugging command to call the contained FPGA debugging function and generates a debugging result.