CN121300918A - A method for PCIe cross-version link capability mapping and transaction data reconstruction - Google Patents
A method for PCIe cross-version link capability mapping and transaction data reconstructionInfo
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Abstract
本发明公开了一种PCIe跨版本链路能力映射与事务数据重构方法，包括以下步骤：链路协商与物理层对端模拟：跨代PCIe桥接装置模拟高版本设备行为训练并建立其与主机之间的第一链路，跨代PCIe桥接装置模拟低版本设备行为训练并建立其与低版本设备之间的第二链路；数据处理与传输：跨代PCIe桥接装置对从主机接收到的数据处理，以适配并传输至低版本设备，跨代PCIe桥接装置对从低版本设备接收到的数据处理，以适配并传输至主机；当跨代PCIe桥接装置对从低版本设备接收到的数据处理时，包括以下步骤：第二解包模块对从低版本设备接收的符号流传输单元的数据包进行协议识别，判断数据包是事务层数据包还是链路层数据包后分别解包。
This invention discloses a PCIe cross-version link capability mapping and transaction data reconstruction method, comprising the following steps: Link negotiation and physical layer peer simulation: The cross-generation PCIe bridging device simulates the behavior of a high-version device for training and establishes a first link between it and the host; the cross-generation PCIe bridging device simulates the behavior of a low-version device for training and establishes a second link between it and the low-version device; Data processing and transmission: The cross-generation PCIe bridging device processes the data received from the host to adapt and transmit it to the low-version device; the cross-generation PCIe bridging device processes the data received from the low-version device to adapt and transmit it to the host; When the cross-generation PCIe bridging device processes the data received from the low-version device, it includes the following steps: A second unpacking module performs protocol identification on the data packets of the symbol stream transmission unit received from the low-version device, determines whether the data packets are transaction layer data packets or link layer data packets, and then unpacks them accordingly.
Description
Technical Field
The invention relates to the technical field of computers, in particular to a PCIe cross-version link capability mapping and transaction data reconstruction method.
Background
In the field of high-speed interconnection and board-level system design, PCI Express (PCIe) is a mainstream high-speed serial interconnection protocol standard, and is widely applied to computing platforms, server motherboards, GPU accelerator cards, and high-performance data center interconnection architectures. As data processing demands continue to grow, PCIe protocols continue to evolve, from early Gen3 (8 GT/s) to currently mainstream Gen4 (16 GT/s), gen5 (32 GT/s), to the latest Gen6 (64 GT/s), providing higher bandwidth density and transmission efficiency for the system. However, the problem of incompatibility of protocol versions between different generations is gradually revealed, and especially in a system with high requirements for coexistence or expansibility of new and old devices, there may be multiple mismatching between the motherboard interface and the actual device, such as speed, channel number, and coding mode. For example, in a motherboard platform employing a new generation PCIe 6.0 x4 interface, if a traditional PCIe 4.0 x16 or PCIe 5.0 x8 device needs to be connected, there is often a challenge that firstly, physical channel resources are seriously wasted, the total bandwidth must be maintained by increasing the number of channels due to rate degradation, so that more PCB space and routing resources are occupied, and secondly, link negotiation mechanisms lack flexibility, that is, link training and negotiation for PCIe is highly dependent on hardware initialization flow, and once a device is identified as a low version, links are automatically degraded, so that the rate potential of an upstream interface cannot be fully utilized.
Current PCIe protocol bridging and compatibility solutions rely mainly on Switch chips, retimers, or Bridge class intermediaries to accomplish link isolation, protocol translation, and path selection. The chips are usually deployed on a main board or an intermediate expansion module and are used as independent link participation nodes to access a host PCIe topological structure, and the link training, the configuration space identification and the protocol rate negotiation are required to be participated in the system initialization stage, so that a standard enumeration mechanism of the host cannot be skipped, and the capability of reconstructing or disguising the protocol formats of a link layer and a transaction layer is not provided. In addition, since the functions of the chip are fixed and not programmable, the chip is in face of remarkable changes of PCIe protocols in terms of data packet structures, transaction management, coding mechanisms (such as PAM 4) and data formats (such as differences between link layer data packet FLIT and transaction layer data packet TLP), and lacks general capability of analyzing, reorganizing and adapting the underlying transaction packet structures, so that the chip is not capable of bridging the cross-generation protocols. More importantly, when dealing with the connection requirements of conventional devices such as PCIe 4.0 x16, such schemes still generally need to provide complete x16 physical channel support, although the upstream link may already employ a more efficient PCIe 6.0 x4 interface, the total bandwidth is not changed, but the utilization efficiency of board resources is extremely low due to the limitation of the number of physical channels, and the complexity of wiring increases. Therefore, it is difficult to realize transparent bridging, bandwidth matching and physical resource compression for the protocol between high and low generation PCIe devices without increasing hardware complexity in the prior art.
The foregoing background is only for the purpose of providing an understanding of the principles and concepts of the application and is not necessarily related to the prior art or is not necessarily taught by the present application, but is not intended to be used for the purposes of assessing the novelty and creativity of the present application without express evidence that such matter has been disclosed prior to the filing date of the present application.
Disclosure of Invention
The invention aims to provide a PCIe cross-version link capability mapping and transaction data reconstruction method.
In order to achieve the above purpose, the invention adopts the following technical scheme:
a PCIe cross-version link capability mapping and transaction data reconstruction method comprises the following steps:
Simulating high-version equipment behavior training and establishing a first link between the high-version equipment behavior training and a host by a cross-generation PCIe bridging device, and simulating low-version equipment behavior training and establishing a second link between the low-version equipment behavior training and the low-version equipment by the cross-generation PCIe bridging device;
The cross-generation PCIe bridging device processes the data received from the host to adapt and transmit to the low-version device, and the cross-generation PCIe bridging device processes the data received from the low-version device to adapt and transmit to the host;
when the cross-generation PCIe bridge device processes data received from the low-version device, the method comprises the following steps:
The second unpacking module carries out protocol identification on the data packet of the symbol stream transmission unit received from the low-version equipment, and unpacks the data packet after judging whether the data packet is a transaction layer data packet or a link layer data packet;
the mapping module restores the transit tag into an original tag according to a pre-established mapping table, and maintains a corresponding relation with the unpacked data packet;
the second reconstruction module reconstructs a header section of the data according to the requirements of the FLIT transmission unit, and the second reconstruction module comprises inserting the original tag into the header section of the corresponding data packet;
The controller encapsulates the data packet, distributes the transaction sequence number and adds the CRC check code to the data packet, and generates the data packet adapting to the FLIT transmission unit of the host;
and sending the data packet of the FLIT transmission unit to the host.
In an embodiment, wherein the high version is the PCIe Gen6 protocol and the low version is the PCIe Gen5 protocol or the PCIe Gen4 protocol.
In one embodiment, in the link negotiation and physical layer peer simulation step, the training of the first link includes the steps of:
Electrically connecting a first serializer supporting PAM4 coding with the host;
a first physical coding sublayer electrically connected with the first serializer after power-on drives a first link training and state machine to start, and the first link training and state machine drives the first link state to circulate;
After the first link is transited from the detection state to the polling state, the host sends an ordered set to the first physical coding sublayer;
the first link training and state machine confirms the capability supported by the host according to the analytic content, and the first physical coding sublayer returns the ordered set to the host;
the host confirms the capabilities supported by the cross-generation PCIe bridge device according to the parsed content,
And the first link enters a normal state, and training of the first link is completed.
In one embodiment, in the link negotiation and physical layer peer simulation step, the training of the second link includes the steps of:
Electrically connecting a second serializer supporting NRZ encoding with the low version device;
A second physical coding sublayer electrically connected with the second serializer after power-on drives a second link training and state machine to start, and the second link training and state machine drives the second link state to circulate;
When the second link is transited from the detection state to the polling state, the second physical coding sublayer transmits an ordered set to the low-version device;
The low-version equipment confirms the capability supported by the cross-generation PCIe bridging device according to the analysis content, and returns the ordered set to the cross-generation PCIe bridging device;
the second link training and state machine confirms the capabilities supported by the low-version device based on the parsed content,
And the second link enters a normal state, and training of the second link is completed.
In an embodiment, after the first link training and the second link training are completed, a configuration module is activated, and the configuration module switches a bridge operation mode according to a preset configuration instruction, and sends the bridge operation mode to a middle protocol processing module to activate a conversion path for converting a data packet between a FLIT transmission unit and a symbol stream transmission unit, where the FLIT transmission unit corresponds to a data transmission mode of a PCIe Gen6 protocol, and the symbol stream transmission unit corresponds to a data transmission mode of a PCIe Gen5 protocol or a PCIe Gen4 protocol.
In an embodiment, wherein the bridging mode of operation comprises PCIe Gen6 protocol bridging with PCIe Gen5 protocol and PCIe Gen6 protocol bridging with PCIe Gen4 protocol.
In one embodiment, the method further comprises the step of state cross sensing:
the central coordination module monitors an energy management link layer data packet sent by the host and the low-version equipment;
the central coordination module enables one of the first link and the second link to be converted into a corresponding state according to the transaction type of the energy management link layer data packet;
The central coordination module transitions the other of the first link and the second link to a respective state to enable a cooperative state transition of the host and the low-version device and a cooperative operation of the first link and the second link.
In an embodiment, the state cross sensing step further includes the central coordination module recording state circulation conditions of the first link and the second link, notifying a middle protocol processing module to prepare for the data processing and transmission step when at least one of the first link and the second link enters the normal state, and notifying the middle protocol processing module to pause the data processing and transmission step when any one of the first link and the second link enters a resume state or a sleep state.
In one embodiment, the cross-generation PCIe bridge device processes data received from the host, comprising the steps of:
the first unpacking module carries out protocol identification on the data packet of the FLIT transmission unit received from the host, and unpacks the data packet after judging whether the data packet is a transaction layer data packet or a link layer data packet;
the mapping module obtains an original tag according to the transaction sequence number in the data packet, translates the original tag to obtain a transfer tag, records the mapping relation between the original tag and the transfer tag into a mapping table, and prepares for the subsequent recovery of the original tag;
The CRC module performs CRC check on the data packet and generates a CRC check code;
the first reconstruction module reconstructs the head section of the data according to the requirements of the symbol stream transmission unit, and inserts the transit tag into the head section of the corresponding data;
The first reconstruction module splices the data packets and adds the CRC check code to generate the data packets adapting to the symbol stream transmission unit of the low-version equipment;
And sending the data packet of the symbol stream transmission unit to a scheduling module and then transmitting the data packet to the low-version equipment.
In an embodiment, when the reconstruction module reconstructs the header section of the data according to the requirements of the symbol stream transmission unit, the reconstruction module specifically includes one or more of field reordering, byte alignment, bit compression and bit expansion.
In an embodiment, when the CRC module performs CRC check on the data packet, if the check is successful, a corresponding legal CRC check code is generated, and if the check fails, a reverse operation is performed, so as to generate a corresponding erroneous CRC check code.
In an embodiment, after receiving the data packet with failed verification, the low-version device automatically generates a reissue request to guide the host to resend the data packet.
In an embodiment, after the data packet of the symbol stream transmission unit is sent to a scheduling module, the data packet of the symbol stream transmission unit is transmitted to the low-version device according to a scheduling rule that the link layer data packet is prioritized over the transaction layer data packet.
In an embodiment, when the cross-generation PCIe bridge device processes the data received from the low-version device, the CRC module generates a temporary CRC for the temporary data after unpacking according to the CRC algorithm specified by the high-version device, so as to ensure reliability when the FLIT transmission unit is packaged in a data packet.
In one embodiment, when the reconstruction module reconstructs the header section of the data according to the requirements of the FLIT transmission unit, the reconstruction module specifically includes one or more of field reordering, byte alignment, bit compression, and bit expansion.
In one embodiment, it may be applied to one or more of FPGA platform, RISC platform, X86 platform, ARM platform.
The technical scheme provided by the invention has the following beneficial effects:
a. and the number of physical channels is reduced, namely physical channel resources required by a main board are obviously reduced through a link capacity mapping and data bandwidth compression mechanism under the condition of keeping the total bandwidth unchanged.
B. and the protocol format reconstruction is realized, namely the structural reorganization and the bidirectional translation of the data packets are supported among PCIe protocols with different generations, and the data consistency and the transaction integrity of cross-version communication are ensured.
C. The method bypasses the fixed configuration limit of the link, simulates the target protocol capability in the link initialization stage, avoids the forced speed reduction of the host after the identification due to the device version limit, and thus maintains the running state of the high-speed link.
D. The method can be adapted to various hardware platforms and PCIe versions, can be flexibly deployed according to actual requirements, and realizes various inter-version intercommunication and protocol adaptation scenes.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings may be obtained according to the drawings without inventive effort to those skilled in the art.
FIG. 1 is a schematic diagram of a cross-generation PCIe bridge device provided by an exemplary embodiment of the present invention;
FIG. 2 is a schematic diagram of a cross-generation PCIe bridge device provided by an exemplary embodiment of the invention;
FIG. 3 is a diagram of a cross-generation PCIe bridge device architecture for processing data received from a host, provided by an exemplary embodiment of the present invention;
FIG. 4 is a diagram of an architecture of a cross-generation PCIe bridge device for processing data received from a low-version device provided by an exemplary embodiment of the present invention.
Detailed Description
In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, apparatus, article, or device that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed or inherent to such process, method, article, or device.
1-4, In some embodiments of the present invention, a PCIe cross-version link capability mapping and transaction data reconstruction method is provided, and in particular, the method may be applied to one or more of an FPGA platform, a RISC platform, an X86 platform, and an ARM platform.
As shown in fig. 1, the method is applied to a cross-generation PCIe bridge device of an FPGA platform, where the cross-generation PCIe bridge device is located between a host and a low-version device, and the host adopts a new-generation PCIe 6.0 x4 interface, that is, a PCIe Gen6 protocol, and the low-version device adopts a PCIe 4.0 x16 interface, that is, a PCIe Gen4 protocol, and in other embodiments, the low-version device may also adopt a PCIe 5.0 x8 interface, that is, a PCIe Gen5 protocol.
The cross-generation PCIe bridge device includes a first physical layer including a first serializer (Serdes) port for electrically connecting with a host, the first serializer port supporting PAM4 encoding, which is a high speed channel conforming to PCIe 6.0 PHY requirements, electrically connected with a first physical coding sublayer ((Physical Coding Sublayer, PCS) for handling basic signal tasks such as physical pattern recognition, symbol alignment, link Recovery (CDR), etc., electrically connected with a first link training and state machine (LINK TRAINING AND Status STATE MACHINE, LTSSM) for driving a first link state stream including an overall process from a Detect (Detect) state→a poll (poll) state→a configure (Configuration) state→a Recovery (Recovery) state→an active (L0) state, wherein the first link refers to a link between the host and the first serializer port.
The cross-generation PCIe bridge device also includes a second physical layer including a second serializer (Serdes) port for electrically connecting with the low-version device, the second serializer port supporting NRZ encoding, being a high speed channel conforming to PCIe 4.0 PHY, the second serializer port being electrically connected with a second physical encoding sub-layer ((Physical Coding Sublayer, PCS) for handling basic signal tasks such as physical pattern recognition, symbol alignment, link Recovery (CDR), etc., the second physical encoding sub-layer being electrically connected with a second link training and state machine (LINK TRAINING AND Status STATE MACHINE, LTSSM) for driving a second link state stream including an overall process from a Detect (Detect) state→a poll (poll) state→a configure (Recovery) state→an active (L0) state, wherein the second physical encoding sub-layer also has a FM (Frame Generation) sub-module built therein for simulating host side behavior, wherein the second link means between the host and the second serializer port.
The cross-generation PCIe bridge device further includes a middle protocol processing module, where the middle protocol processing module is configured to process data in different formats between the first physical layer and the second physical layer, so that a data packet of a FLIT transmission unit received from the host can be converted into a data packet of a symbol stream transmission unit, so as to adapt to a low version device, and also enable a data packet of a symbol stream transmission unit received from the low version device to be converted into a data packet of the FLIT transmission unit, so as to adapt to the host, where the middle protocol processing module specifically includes the following submodules:
A first unpacking module configured to perform protocol structure identification and content unpacking of a data packet (256 Byte fixed format) of a FLIT transmission unit received from a host, determine whether the data packet is a transaction layer (TLP-FLIT) data packet or a Link layer (DLLP-FLIT) data packet, extract a TLP header field (e.g., type, length, tag, requester ID, address, etc.) if the data packet is a TLP-FLIT, extract a Link layer control field (e.g., ACK/NAK/pm_request, etc.), independently decode a header and a payload in the data packet, and strip an original CRC32 in the data packet, and add each unpacked data to an internal buffer and attach an original transaction sequence number (SeqNum) Tag.
And the second unpacking module is configured to be responsible for carrying out protocol structure identification and content unpacking on the data packet of the symbol stream transmission unit received from the low-version device, judging whether the data packet is a Transaction Layer (TLP) data packet or a link layer (DLLP) data packet, if the data packet is not modified for the DLLP data, but the packing sequence is required to be adjusted according to the packing requirement of a PCIe 6.0 input interface, and if the data packet is not compatible with PCIe 6.0 in the PCIe 4.0 format, removing the field layout in the PCIe 4.0 format for the TLP data.
And the mapping module is configured to restore the tag field in PCIe 6.0 according to the transaction serial number in the data packet of the FLIT transmission unit, record the tag field as an original tag, translate the tag field into PCIe 4.0 according to an internal coding mechanism, record the mapping relation between the original tag and the transit tag into a mapping table, and prepare for the subsequent recovery of the original tag because the length specifications of the tag (tag) fields of PCIe 6.0 and PCIe 4.0 are different, and the mapping table is required to be established in order to enable the data packet of the FLIT transmission unit received from the host to be compatible with low-version equipment and ensure the consistency of the transaction matching and the sequence.
Similarly, to make the data packet of the symbol stream transmission unit received from the low-version device compatible with the host, and ensure the consistency of transaction matching and sequence, the mapping module is further configured to restore the transit tag to the original tag according to the pre-established mapping table, and maintain the corresponding relationship with the unpacked data packet, so that the host can correctly track and match the cross-generation transaction.
The CRC module is used for ensuring the CRC consistency and the transfer effectiveness under different link standards of PCIe 6.0 and PCIe 4.0, so that transparent forwarding and error mapping under the condition of no protocol identification are realized when the CRC module is used as a relay bridging device. For the data packets of the FLIT transmission units transmitted from the host side, the CRC module is configured to perform integrity check on each received data packet of the FLIT transmission unit to obtain a result of whether the CRC check is successful, that is, whether the CRC field passes the check first, if the CRC field passes the check, a corresponding legal CRC check code is generated, if the CRC field fails the check, a reverse operation is performed to generate a corresponding erroneous CRC check code, and for the PCIe 4.0 TLP data packet obtained after the reconstruction, TLP CRC needs to be recalculated and appended. And after receiving the data packet with verification failure, the low-version equipment automatically generates a reissue request to guide the host to resend the data packet.
For the data packet of the symbol stream transmission unit transmitted from the low-version equipment side, the data packet of the symbol stream transmission unit generated by the low-version equipment comprises a standard CRC check code, but considering that the physical distance between the cross-generation PCIe bridging device and the low-version equipment is extremely short and no error-prone link exists in the middle, no CRC check or check processing is performed in any form, resource waste and processing delay are avoided, namely CRC trust forwarding is directly performed, the CRC module is configured to generate temporary CRC codes for the temporary data after unpacking according to a CRC algorithm specified by PCIe 6.0, ensure the reliability of the package packaging of the data packet of the FLIT transmission unit, and regenerate the CRC check code conforming to the PCIe 6.0 standard for the data packet after reconstruction is performed by the subsequent CRC module so as to be added when the data packet of the FLIT transmission unit is packaged.
As shown in fig. 3, for the data packet of the FLIT transmission unit transmitted from the host side, the first reconfiguration module has the core task of recombining the TLP data obtained by unpacking from the host side and the DLLP data into a format conforming to the PCIe 4.0 protocol structure, and supplementing relevant protocol fields (TAG, CRC, etc.) to ensure that the TLP data can be directly recognized and processed by the PCIe 4.0 device. The method comprises the steps of maintaining a transparent forwarding principle, not carrying out analysis of a protocol semantic layer, completing field mapping and structure adaptation only at a necessary position, enabling a first reconstruction module to firstly enter DLLP buffer areas for temporary storage of DLLP data (such as ACK/NAK, flow Control and PM information) from a host side, firstly entering TLP buffer areas for temporary storage of TLP data from the host side, enabling the DLLP to send preferentially (such as PM transaction) when needed by matching with the synchronization and arbitration scheduling of the TLP data, enabling the setting of the TLP buffer areas to ensure that data is not lost in the processes of waiting for TAG conversion, DLLP scheduling and the like, and can be combined with the DLLP correctly according to the priority order, carrying out one or more of field rearrangement, byte alignment, bit compression and bit expansion of the DLLP and the head section of the TLP data according to the requirements of a symbol stream transmission unit, such as reconstruction Type, length, requester ID, address and the like, removing special data packet fields (such as transaction sequence bit) of the FLIT transmission unit, retransmitting data packets according to the position of a corresponding bit stream transmission unit, splicing the head section of the DLLP data packets, and carrying out bit stream transmission unit splicing, and the head section splicing and the bit stream transmission unit splicing the data packets according to the position of the corresponding to the bit stream transmission unit, and the bit stream transmission unit splicing the bit section and the bit stream transmission unit.
The scheduling module is configured to, after receiving the data packet of the symbol stream transmission unit adapted to the low-version device after the first reconfiguration module is reconfigured, transmit the data packet of the symbol stream transmission unit to the low-version device according to a scheduling rule of the DLLP data packet in preference to the TLP data packet, specifically, first determine whether the data packet is the DLLP or the TLP, ensure that the power management or the link maintenance type data is prioritized, and if the data packet is the DLLP, such as the pm_enter_l1, the ACK/NACK, etc., schedule the data packet into the transmission link in priority, and if the data packet is the ordinary TLP, schedule the data packet according to the FIFO or the transaction priority sequence, and transmit all the scheduled data packet to the second serializer port of the second physical layer to the low-version device.
The second reconstruction module is used for carrying out protocol field adaptation and header reconstruction on the TLP data packet and the DLLP data packet obtained by unpacking for the data packet of the symbol stream transmission unit transmitted by the low-version equipment side, so that the protocol field adaptation and header reconstruction are in accordance with the receiving requirement of the controller, the operations of assembling the data packet, distributing transaction sequence numbers, inserting CRC and the like according to the requirement of the FLIT transmission unit are not involved in the module, and are completed by a hard core of the controller, so that the logic implementation of the second reconstruction module is relatively simple, but has a key role in cross-generation protocol adaptation, and the second reconstruction module is configured to carry out one or more of field rearrangement, byte alignment, bit compression and bit expansion on the header section of the data packet, such as rearranging the header section of a PCIe 4.0 protocol structure into a PCIe 6.0 format, arranging, removing or replacing PCIe 4.0 specific fields according to the corresponding relation between transfer labels recorded in a mapping table and original labels, and inserting the original labels into the header section of the corresponding data packet.
The controller, specifically a PCIe 6.0 controller, is configured to send the TLP/DLLP data packet directly to the PCIe 6.0 controller in a form conforming to the PCIe 6.0 interface standard after the second reconfiguration module completes the reconfiguration, and the controller completes packaging of the FLIT transmission unit, allocation of the transaction serial number and addition of the CRC check code, generates a data packet adapting to the FLIT transmission unit of the host, and sends the data packet to the first serializer port of the first physical layer to send the data packet to the host.
The cross-generation PCIe bridging device further comprises a central coordination module, wherein the central coordination module is used for monitoring the energy management link layer data packet sent by the host and the low-version equipment, and is configured to enable one of the first link and the second link to be converted into the corresponding state according to the transaction type of the energy management link layer data packet, enable the other of the first link and the second link to be converted into the corresponding state so as to realize the cooperative state conversion of the host and the low-version equipment and the cooperative operation of the first link and the second link, and further be configured to record the state flow condition of the first link and the second link, and notify that at least one of the first link and the second link enters a middle part of the state, and to enable the other of the first link and the second link to enter a sleep protocol to enter a normal processing state, and to be in preparation for the data processing, and the data processing module to resume the data processing, and the data processing module to enter a sleep protocol to enter a processing state, and the middle part of the data processing module, and the data processing module is configured to resume the data processing, and the data processing state of the data processing module is configured to be in the middle part of the data processing state of the host and the data processing device is configured to be in the data processing state of the data management module.
The cross-generation PCIe bridging device further comprises a configuration module which is activated after the first link training and the second link training are completed, and is configured to switch the bridging operation mode according to preset configuration instructions and send the bridging operation mode to the middle protocol processing module to activate a conversion path for converting the data packet between the FLIT transmission unit and the symbol stream transmission unit, wherein the FLIT transmission unit corresponds to a data transmission mode of a PCIe Gen6 protocol, the symbol stream transmission unit corresponds to a data transmission mode of a PCIe Gen5 protocol or a PCIe Gen4 protocol, wherein the bridging operation mode comprises bridging of the PCIe Gen6 protocol and the PCIe Gen5 protocol, and bridging of the PCIe Gen6 protocol and the PCIe Gen4 protocol.
In one embodiment, the PCIe cross-version link capability mapping and transaction data reconstruction method of the present invention comprises the steps of:
Simulating high-version equipment behavior training and establishing a first link between the high-version equipment behavior training and a host by using a cross-generation PCIe bridging device, and simulating low-version equipment behavior training and establishing a second link between the low-version equipment behavior training and the low-version equipment by using the cross-generation PCIe bridging device;
Data processing and transmission, namely processing data received from a host by the cross-generation PCIe bridging device to adapt and transmit the data to the low-version device, and processing data received from the low-version device by the cross-generation PCIe bridging device to adapt and transmit the data to the host, wherein the high-version is PCIe Gen6 protocol, and the low-version is PCIe Gen5 protocol or PCIe Gen4 protocol.
In the link negotiation and physical layer opposite end simulation step, training of the first link includes the following steps:
electrically connecting a first serializer supporting PAM4 coding with a host;
A first physical coding sublayer electrically connected with the first serializer after power-on drives a first link training and state machine to start, and the first link training and state machine drives a first link state to circulate;
when the first link is transited from the detection state to the polling state, the host transmits an ordered set to the first physical coding sublayer, which may be specifically a TS1/TS2 ordered set;
The first link training and state machine confirms the capability of the host to support according to the analysis content, and the first physical coding sublayer returns the ordered set to the host, specifically, the ordered set can be TS1/TS2 ordered set;
the host validates the capabilities supported by the cross-generation PCIe bridge device based on the parsed content,
The first link enters a normal state, and training of the first link is completed.
In the link negotiation and physical layer opposite end simulation step, training the second link includes the following steps:
electrically connecting a second serializer supporting NRZ encoding with the low version device;
a second physical coding sublayer electrically connected with the second serializer after power-on drives a second link training and state machine to start, and the second link training and state machine drives a second link state to circulate;
when the second link is transited from the detection state to the polling state, the second physical coding sublayer transmits an ordered set to the low-version equipment, and the ordered set can be specifically TS1/TS2 ordered set;
the low-version equipment confirms the capability supported by the cross-generation PCIe bridging device according to the analysis content, and returns the ordered set to the cross-generation PCIe bridging device, wherein the ordered set can be specifically TS1/TS2 ordered set;
The second link training and state machine confirms the capabilities supported by the low-version device based on the parsed content,
And the second link enters a normal state, and training of the second link is completed.
As shown in fig. 3, when the cross-generation PCIe bridge device processes data received from the host, the method includes the following steps:
The first unpacking module carries out protocol identification on the data packet of the FLIT transmission unit received from the host, and unpacks the data packet after judging whether the data packet is a transaction layer data packet or a link layer data packet;
The mapping module obtains an original tag according to the transaction sequence number in the data packet, translates the original tag to obtain a transfer tag, records the mapping relation between the original tag and the transfer tag into a mapping table, and prepares for the subsequent recovery of the original tag;
CRC module checks CRC of data packet and generates CRC check code;
The first reconstruction module reconstructs the head section of the data according to the requirements of the symbol stream transmission unit, and inserts the transit tag into the head section of the corresponding data;
The first reconstruction module performs splicing and CRC check code addition on the data packet to generate a data packet of a symbol stream transmission unit of the low-version equipment;
And sending the data packet of the symbol stream transmission unit to a scheduling module and then transmitting the data packet to low-version equipment.
Wherein, as shown in fig. 4, when the cross-generation PCIe bridge device processes the data received from the low-version device, the method comprises the following steps:
The second unpacking module carries out protocol identification on the data packet of the symbol stream transmission unit received from the low-version equipment, judges whether the data packet is a transaction layer data packet or a link layer data packet and unpacks the data packet respectively;
the mapping module restores the transit tag into an original tag according to a pre-established mapping table, and maintains a corresponding relation with the unpacked data packet;
The second reconstruction module reconstructs a header section of the data according to the requirements of the FLIT transmission unit, and the second reconstruction module comprises inserting an original tag into the header section of the corresponding data packet;
The controller encapsulates the data packet, distributes the transaction sequence number and adds the CRC check code to the data packet, and generates the data packet of the FLIT transmission unit of the adaptation host;
and sending the data packet of the FLIT transmission unit to the host.
Therefore, the invention adopts a modularized cross-generation protocol bridging method, and realizes transparent compatibility of a high-version PCIe interface of a host to low-version equipment and efficient utilization of physical channel resources on the premise of unchanged total bandwidth by bidirectional protocol adaptation, link capacity mapping and transaction layer data reconstruction.
Firstly, the method constructs a link capability negotiation flow compatible with PCIe 6.0 interface standard, and can declare high version rate and channel capability by simulating configuration space and key capability field in the link training process in the link initialization stage, thereby avoiding the link speed reduction caused by device version limitation and ensuring the link to operate in an expected high-speed state.
Secondly, the method designs a protocol conversion flow of the FLIT transmission unit and the symbol stream transmission unit, supports bidirectional reconstruction of a transaction layer and a link layer packet structure between PCIe 6.0 and PCIe 4.0, and comprises mapping relation processing of a transaction sequence and an original tag and a transfer tag, decoupling and regeneration of a CRC check mechanism, so that data integrity and transaction consistency are accurately transferred in cross-protocol transmission.
And the method adopts a dual-port hierarchical processing and link state independent control strategy, realizes the separated management of the links of the host side and the equipment side under the condition of not depending on the traditional Switch or Bridge topology, and simultaneously combines a central coordination module to realize the transparent response of the link state switching without additional software driving intervention.
In summary, the method realizes a PCIe cross-version protocol bridging scheme with high compatibility, high bandwidth utilization and low resource occupation through the cooperation of link capacity mapping, protocol format reconstruction, configuration space virtualization and physical resource compression mechanisms, and provides a new realization path for the intercommunication of multi-generation protocol devices and the high-speed interconnection of systems.
Compared with the prior art, in one embodiment, the technical scheme has the following beneficial effects:
1. the method allows only 4 PCIe 6.0 channels (x 4) to bear the equivalent data bandwidth of PCIe 4.0 x16 devices through a protocol analysis and bandwidth mapping mechanism, thereby greatly reducing the physical dependence of the system on the number of channels on the premise that the total data throughput is not reduced. The characteristics not only can obviously compress the area and the routing density of the PCB, reduce the cost of the layout of the connector and the channel, but also provide greater structural flexibility and integration space for the design of a high-density system;
2. Aiming at the difference between the data packet of the FLIT transmission unit of PCIe 6.0 and the data packet structure of the symbol stream transmission unit of PCIe 4.0, the method designs a complete protocol conversion flow, can analyze, reorganize and repackage the content of the transaction packet in transmission in real time, and covers the corresponding processing of a header section r format, a transaction identifier (original tag to transit tag mapping) and a CRC check mechanism. The mechanism ensures the consistency of data, the response correctness and the integrity of the flow control state in the cross-generation link, and ensures that the communication behavior is strictly aligned in protocol semantics;
3. The method simulates the target protocol capability in the link initialization stage, declares high version rate and channel parameters in the configuration space, and is matched with a link state machine response mechanism to ensure that a host always recognizes the interface as high-version equipment in the enumeration process, thereby keeping the high-speed link in a full-speed running state and avoiding the link speed reduction or bandwidth waste caused by low-version actual equipment;
4. The method has high modularization and expandability, can flexibly adapt to the intercommunication relation among a plurality of PCIe versions (such as Gen4, gen5 and Gen 6) according to actual demands, and can be deployed on a plurality of hardware platforms and application scenes, including a mainboard bridging module, a transfer card, a server back board channel compression system and the like, thereby providing reconfigurable interface compatibility and protocol expansion capability for users and improving the universality and the suitability of the system.
In summary, the technical scheme has remarkable advantages in the aspects of improving the channel resource utilization rate, realizing the cross-generation protocol conversion, ensuring the continuous operation of the high-speed link, enhancing the deployment flexibility and the like, and provides a feasible and extensible implementation path for the next-generation high-performance interconnection structure.
The foregoing is merely illustrative of the embodiments of this application and it will be appreciated by those skilled in the art that variations and modifications may be made without departing from the principles of the application, and it is intended to cover all modifications and variations as fall within the scope of the application.
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