CN121166203A - RISC-V style 8-bit reduced instruction set customization method - Google Patents

Abstract

The invention discloses a RISC-V style 8-bit reduced instruction set customizing method, which comprises the following steps of S1, screening a target instruction set from a RISC-V32I instruction set based on functions and requirements of a target application scene, selecting a data bit width, a PC width, a memory access space and a register group scale of a processor, S2, determining interrupt and abnormal processing flows according to interrupt and abnormal types supported by the instruction set, S3, reducing coding space through a register coding multiplexing strategy and optimizing register grouping to realize customizing of an addressing mode of an instruction set register, S4, classifying each instruction according to an instruction format, and S5, coding each instruction based on the format of each instruction. The customization method has simple and efficient flow, is easy to realize and deploy, does not need zero design, remarkably shortens the research and development period, can adapt to the requirements of multiple scenes, and realizes miniaturization of an instruction set, minimization of hardware resources and high efficiency of the design flow.

Description

RISC-V style 8-bit reduced instruction set customization method

Technical Field

The invention belongs to the technical field of microelectronics, and particularly relates to a RISC-V style 8-bit reduced instruction set customization method.

Background

In the field of embedded system and microprocessor design, an instruction set architecture (Instruction Set Architecture, ISA) is the basis of software-hardware interaction, and has important effects on system performance, power consumption, hardware complexity and software ecology. The RISC-V instruction set is an open-source, modular, modern instruction set architecture designed based on the RISC (reduced instruction set) principle. RISC-V follows the design principles of reduced instruction, regular encoding, fixed length (e.g., 32-bit or 64-bit), load/Store (Load/Store) architecture, etc., providing a clear and compact instruction format and efficient hardware decode logic supporting modular extensions (e.g., integer, multiply-divide, floating point, atomic operations, etc.). The instruction execution is usually single-cycle, regular and water friendly, the code density and the execution efficiency are higher, and the method has good portability and expandability, and is suitable for a wide range of scenes from an embedded microcontroller to high-performance calculation. The open source characteristic and modern design concept of RISC-V make it an important choice for academic research, chip design innovation and embedded development.

The RISC-V standard architecture (e.g., RV 32I) uses 32-bit fixed length instructions, which, while having excellent scalability and general purpose computing power, has a large instruction width (a single instruction occupies 32 bits), a large register set size (typically 32 general purpose registers, each 32 bits), resulting in a large program code size (e.g., a simple add instruction requires 4 bytes of storage, while an 8-bit instruction requires only 1 byte), and a dramatic increase in ROM/RAM capacity requirements. The power consumption pressure is high, wide instructions require longer instruction fetch cycles, more complex instruction decode logic and a wider data bus, resulting in significant increases in dynamic power consumption (especially frequent instruction fetch and instruction cache accesses). The hardware area cost is high, and a large-scale register file (32×32 bits), an high-bit-width ALU and a complex pipeline control logic are strictly required for the chip area and the manufacturing cost.

Therefore, the method shows obvious performance surplus in severe scenes such as internet of things (IoT), wearable equipment, sensor nodes and the like, and is not applicable to embedded systems (such as sensors, controllers and simple household appliances) with limited resources.

Current RISC instruction sets are mostly 32-bit or 64-bit, and some instruction sets (e.g., C-extensions of RISC-V, i.e., compressed instruction sets) are provided with 16-bit compressed instructions, but their instruction width is still too large, resulting in large volumes of program code and a dramatic increase in ROM/RAM capacity requirements. The register set has larger scale, the data bit width is higher, the areas of the computing units such as ALU and the processing units are larger, and the area cost of the processor is higher. The wide instruction needs longer instruction fetching period, more complex instruction decoding logic and wider data bus, so that dynamic power consumption is obviously increased, and the practical requirements of ultra-low resources, ultra-low power consumption and extremely-small size scenes are difficult to meet.

Disclosure of Invention

An object of the present invention is to provide a RISC-V style 8-bit reduced instruction set customization method, comprising the steps of:

s1, screening a target instruction set from a RISC-V32I instruction set based on functions and requirements of a target application scene, and selecting a data bit width, a PC width, a memory access space and a register set scale of a processor;

S2, determining interrupt and exception processing flows according to interrupt and exception types supported by an instruction set;

s3, reducing the coding space and optimizing the grouping of the registers through a register coding multiplexing strategy to realize the customization of the addressing mode of the instruction set register;

S4, classifying each instruction according to the instruction format;

S5, encoding each instruction based on the format of each instruction.

Preferably, in the step S1, the data bit width is set to 8 bits, the bit width of the memory access space is selected to 8 bits, the bit width of the register set is consistent with the data bit width, the number of registers is 8, the value of the register No. 0 is constant zero, and the range of PC width selection is 8-16 bits.

Preferably, in the step S3, the register code multiplexing strategy is to simplify the three-operand instruction into a two-operand instruction.

Preferably, in the step S3, the optimizing register group controls the encoding space of the memory number to two bits, and the optimizing register group method includes the following steps:

first, equally dividing a register group into 2 or 4 consecutive packets;

Then, classifying the instructions according to the type of operations they perform;

the sorted instructions are then assigned to corresponding register groups.

Preferably, in the step S4, the classification type comprises R-type instruction for inter-register operation, I-type instruction for load operation of short immediate and memory access, S-type instruction for memory access operation, B-type instruction for conditional jump, U-type instruction for long immediate, J-type instruction for unconditional jump.

Preferably, in the step S5, when the opcodes and the Funct of the instructions are encoded, the instructions with the same structure or type have the same or similar opcodes and Funct.

Preferably, in S5, the functions encoded by the adjacently executed instructions are identical, and the opcodes are only different in individual bits, or the opcodes encoded by the adjacently executed instructions are identical, and the functions are only different in individual bits. The state switching overhead of the decoder in the decoding stage is reduced, and the problems of hardware signal jump, power consumption and time sequence are reduced.

The invention has the following beneficial effects:

The invention provides a RISC-V8-bit reduced instruction set customizing method, which has simple and efficient flow, is easy to realize and deploy, does not need zero design, obviously shortens the research and development period and provides clear customizing steps. The customizing method is flexible and can adapt to the requirements of multiple scenes. The method realizes miniaturization of instruction sets, minimization of hardware resources and high efficiency of design flow. The method reserves the efficient and mature access mode, jump/transfer mode, basic operation type, general register use standard and interrupt and exception handling mechanism in RISC-V, and uses the instruction format classification system of RISC-V to ensure the clear and regular instruction structure. By reasonably grouping the general register sets and setting optimization strategies such as default registers, the instruction width of the customized 8-bit fixed-length simplified instruction set is smaller, the program code volume is smaller, and the required ROM/RAM capacity is also greatly reduced. At the same time, the register set area and ALU data bit width are reduced, thereby reducing the area cost of the processor. The 8-bit fixed length reduced instruction set has a smaller instruction number, so that the design and implementation of the processor are simplified, and the higher coding efficiency is realized in a limited 8-bit width. Finally, a fixed-length reduced instruction set suitable for an 8-bit hardware platform is formed.

The instruction set customized by the 8-bit reduced instruction set customization method not only has the simplicity and modularization of RISC-V, but also greatly reduces the hardware resource requirement, has fewer instruction numbers, is simpler to realize, and is more suitable for the actual requirements of ultra-low power consumption embedded application scenes such as the Internet of things, wearable equipment, sensor nodes and the like.

Drawings

FIG. 1 is a diagram of the register specifications provided by an embodiment.

FIG. 2 is an embodiment of exception types and exception codes.

FIG. 3 is a register packet corresponding to each instruction provided by an embodiment.

FIG. 4 is an instruction format classification provided by an embodiment.

Fig. 5 is an instruction set encoding scheme provided by an embodiment.

FIG. 6 is an expanded version of the pseudo-instruction provided by the embodiment.

FIG. 7 is a block diagram of the customization flow of the RISC-V style 8-bit reduced instruction set customization method of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.

Referring to fig. 7, the invention discloses a RISC-V style 8-bit reduced instruction set customizing method, which specifically comprises the following steps:

S1, selecting and counting instructions with target functions from a RISC-V32I instruction set according to application scenes and design requirements, and defining the data bit width, PC width, memory access space and register group size of a processor.

The instruction length is 8 bits, the data width can be 8 bits or 16 bits, preferably 8 bits, the width of a Program Counter (PC) can be selected from 8 bits to 16 bits, the program counter can be properly expanded according to application scenes, the bit width (namely the address bus width) of the memory access address space can be 8 bits or 16 bits, preferably 8 bits, the size of a register set can be 8 x 8 bits or 8 x 16 bits, and the bit width of the register set needs to be consistent with the data width.

Illustrating:

the instruction length and the data bit width of the instruction set designed in this embodiment are both determined to be 8 bits, the PC width is also 8 bits, the memory space is 256 bytes, and the general register set is designed to be 8 registers with 8 bits, wherein the value of the register No. 0 is constantly 0. The state control register (CSR) only holds the mtvec, mepc, mcause and mstatus registers in RISC-V and is 8 bits each. The area of the register group is reduced, and the access width can be compressed into 2 bits.

In RISC-V, the access width of the CSR is 12 bits. When the instruction set is designed, according to the use requirement, no extra expansion is needed for the CSR register, and only mtvec, mepc, mcause and mstatus registers are needed, which is equivalent to cutting CSR in RISC-V, recoding the four registers, and only two-bit access width is needed to cover the four registers.

S2, determining interrupt and exception processing flows according to interrupt and exception types supported by the instruction set.

The interrupt type may select a single-level interrupt, a multi-level interrupt, whether interrupt priority is supported, whether interrupt nesting is supported, and the like. The exception type is based on and an exception code is designed for the exception that may occur in the instruction set. Exceptions that may occur within a processor include address access exceptions, illegal instruction exceptions, breakpoint exceptions, address misalignment exceptions, and the like.

Interrupt exception handling procedures may be custom implemented or referenced to existing mature instruction set architecture and adapted to the current instruction set architecture.

In this embodiment, the instruction set supports only a single level of interrupts, and does not support interrupt nesting and preemption. The interrupt exception handling flow will take the same approach as RISC-V. The interrupt exception type and its exception code in the instruction set are shown in FIG. 2.

S3, customizing a register addressing mode of the instruction set.

For three-operand arithmetic instructions of RISC-V (e.g., rd=r1+r2), it is often necessary to allocate separate encoding bits for each register operand, with a total bit number requirement of 4 (opcode) +3 (rd) +3 (rs 1) +3 (rs 2) =13 bits. However, 13 bits have exceeded the capacity of 8-bit instructions, thus requiring a large amount of compression encoding space. To adapt the 8-bit instruction width, we will employ a register code multiplexing scheme to reduce the traditional three-operand instruction to a two-operand instruction (e.g., rd=rd+r1).

Since an 8-bit instruction directly encodes a 3-bit register number (i.e., 2^3 =8, supporting 8 registers), each operand requires at least 3 bits×2 operands=6 bits, and the remaining 2 bits cannot carry complex operation codes or addressing patterns, we need to use a register group design to control the encoding space of the register number to two bits.

In order to realize the register group design, firstly, the register group is divided into a plurality of groups, then the instructions are classified according to the operation types to be executed by the instructions, and finally, the classified instructions are distributed to the corresponding register groups.

The register grouping design is used for solving the problem that the instruction coding space is insufficient and all registers cannot be coded. The registers are thus grouped, which is to split the registers into consecutive 2 or 4 equal parts.

The instruction is classified according to the operation performed by the instruction and the characteristics thereof, in particular, the instructions which are similar in type and are suitable for using the same register group are classified into one class.

In this embodiment, the instructions are classified and grouped, and the final grouping result is shown in fig. 3. Packet 1 includes data operation type instructions, and packet 2 includes data load, access, data set, transfer, cavitation, breakpoint exception, and CSR (state control register) type instructions. In packet 1, the vast majority of instructions use register sets of x0 through x3. Specifically, the 2-bit register number in the instruction is obtained by supplementing 0 to the most significant bit, and the 3-bit register number is the actual register number. Whereas in packet 2, registers between x4 and x7, or between x2 and x5 are used, the 2-bit register number in the instruction determines the final register number by either adding 1 or adding 2.

S4, classifying each instruction according to the instruction format. The method comprises the following steps of R-type instructions for inter-register operation, I-type instructions for loading operation of short immediate and access memory, S-type instructions for access memory storage operation, B-type instructions for conditional jump, U-type instructions for long immediate and J-type instructions for unconditional jump. The classification result is shown in fig. 4.

And S5, finally, encoding each instruction based on the format of each instruction.

In this embodiment, the final encoding scheme is shown in fig. 5.

For instruction design and coding schemes, we need to analyze the implementation of instructions one by one.

Taking a data operation type add instruction as an example, in a RISC-V instruction set, the add instruction realizes an MV pseudo instruction among registers in a addi rd, rs1, 0 or add rd, x0 and rs2 form. In this case, since addi instruction cannot directly complete register transfer except opcode, function 2 and two-bit immediate imm, the add instruction is selected to implement MV pseudo-instruction. The add instruction belongs to an R-type instruction, which can only operate two registers, and the register selection space has only two bits.

Considering first the full transition between register set 1 (x 0-x 3), the corresponding instruction is an addl instruction, which requires clearing rd by an and instruction prior to use. Next consider the full transition between register set 2 (x 4-x 7), the corresponding instruction is addh, and rd needs to be cleared by the slt instruction before use. Finally, consider the transition between register set 1 and register set 2, with the corresponding instruction being addm. According to the different transfer directions, the method is divided into two cases, namely, before transferring from the register group 1 to the register group 2, the rd needs to be cleared by an and instruction, and before transferring from the register group 2 to the register group 1, the rd needs to be cleared by an slt instruction. Finally, an extended version of the MV pseudo instruction is shown in FIG. 6.

The nop pseudo-instruction is implemented in the same manner as RISC-V, in extension addi x 00, as shown in FIG. 6.

Looking at the subtraction sub instruction of the data operation type. In this embodiment, the instruction set needs to provide 16-bit addition and subtraction operations considering that the register and data width are 8 bits, and in order to support more application scenarios. For the add instruction, the carry operation of the adder is already preserved when the processor is designed, so 16-bit addition can be performed sequentially by low-order and high-order addition. While subtractors are usually implemented based on adders, subtraction operations implement addition by inverting the subtrahens and adding 1. However, this implementation cannot obtain the borrow of the last subtraction. Therefore, it is necessary to distinguish between high-order subtraction sub which adds 1 to the inverse of the subtraction and low-order subtraction subcarry which adds the carry of the low-order subtraction on the inverse of the subtraction.

The remaining data-operated instructions are mainly logical operations, performing two source register operations and writing the result back to the rd register. The data load and memory type instructions continue the lui, lw and sw instructions of RISC-V. Because the access width of the instruction set is byte, only a single byte access instruction is needed, and the problems of address misalignment and the like are not considered. Considering that the 8-bit instruction set encoding space is limited, the four-bit encoding space can only accommodate the base address of the memory access and the immediate imm, so the source register or the target register of the data loading and memory access type instruction is set to x4 by default.

The data set instruction slt sets rd to 1 if rs1 is smaller than rd by comparing the values of the source register 1 (rs 1) and the source register 2 (rd), otherwise, sets rd to 0. Based on the slt instruction, pseudo-instructions slti (less than 0 set) and sgti (greater than 0 set) may be implemented, with the extension shown in FIG. 6.

The lui instruction belongs to a U-type instruction for loading long immediate, thus requiring maximum utilization of the immediate's encoding space and default use of the x5 registers.

Beqr in the PC transfer type instruction is used for equal time register jumps, and pseudo instruction beqzr may also be implemented to implement equal to 0 register jumps. bnezr are used for register jumps when not equal to 0. jal and jalr are unconditional relative jumps and unconditional register jumps, respectively. The sPC instruction is an alternative to the auiPC instruction in RISC-V, and the sPC instruction saves encoding space due to limited instruction encoding space, and is used in combination with the addi instruction to implement the auiPC function. Because of the limitation of the coding space of the 8-bit fixed-length instruction set, all PC transfer type instructions use an x5 register as a default PC transfer register, thereby efficiently saving the coding space and increasing the number of the realizable instructions.

The breakpoint exception instruction is a special operation and can be implemented by 8-bit fixed encoding.

Csrrw in CSR type instruction is used to perform read-write operation on CSR register, and in order to save coding space, x5 register is used as CSR read-write register by default.

Finally, when encoding opcodes and function 2 for instructions, we need to optimize instruction encoding so that instructions of the same structure or type have the same or similar opcodes and function 2, which helps to optimize the decode module of the processor. Meanwhile, the codes of the instructions executed adjacently are made similar (for example, only a few bits are changed) as much as possible, so that the functions of the codes of the instructions executed adjacently are identical, and the opcodes are different only by individual bits, or the opcodes of the codes of the instructions executed adjacently are identical, and the functions are different only by individual bits. The state switching overhead of the decoder in the decoding stage is reduced, and the problems of hardware signal jump, power consumption and time sequence are reduced.

Coding similarity means that the opcode and function portions of several instructions are not identical by a few bits, such as in this embodiment, the opcode and function portions of the and instruction are 0110, the addl instruction is 0111, and there is only one bit of inconsistency.

In order to reduce decoding complexity, the present embodiment enables the instructions having the same register number section to share the same opcode and function 2 codes as much as possible according to the instruction structure and the register number section during instruction encoding. Meanwhile, due to the high frequency of use of mv pseudo instructions, the extended form thereof contains two instructions, so that sequences such as and-addl, and-addm, slt-addh, slt-addm and the like frequently occur in instruction sequences. Therefore, in the encoding design, the addl and addm instructions and the and instructions are only different by one bit, the addh and addm instructions and the slt instructions are also only different by one bit, so that the encoding bit flipping of the processor in the value and decoding stage is reduced, and the power consumption is further reduced.

The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.

Claims (7)

1. A RISC-V style 8-bit reduced instruction set customization method, comprising the steps of:

s1, screening a target instruction set from a RISC-V32I instruction set based on functions and requirements of a target application scene, and selecting a data bit width, a PC width, a memory access space and a register set scale of a processor;

S2, determining interrupt and exception processing flows according to interrupt and exception types supported by an instruction set;

s3, reducing the coding space and optimizing the grouping of the registers through a register coding multiplexing strategy to realize the customization of the addressing mode of the instruction set register;

S4, classifying each instruction according to the instruction format;

S5, encoding each instruction based on the format of each instruction.

2. The method of claim 1, wherein in S1, the data bit width is set to 8 bits, the bit width of the memory access space is selected to 8 bits, the bit width of the register set is consistent with the data bit width, the number of registers is 8, the value of register No. 0 is constant zero, and the range of PC width selection is 8-16 bits.

3. The method of claim 1, wherein in S3, the register code multiplexing strategy is to reduce a three-operand instruction to a two-operand instruction.

4. The customization method according to claim 1, wherein in S3, the optimizing register grouping controls the encoding space of the memory number to two bits, and the optimizing register grouping method includes the steps of:

first, equally dividing a register group into 2 or 4 consecutive packets;

Then, classifying the instructions according to the type of operations they perform;

the sorted instructions are then assigned to corresponding register groups.

5. The method of claim 1, wherein in S4, the class type includes R-type instructions for inter-register operations, I-type instructions for load operations of short immediate and memory accesses, S-type instructions for memory accesses, B-type instructions for conditional jumps, U-type instructions for long immediate, J-type instructions for unconditional jumps.

6. The customization method according to claim 1, wherein in S5, the opcodes and Funct of the instructions are encoded so that the same structure or type of instructions have the same or similar opcodes and Funct.

7. The method of claim 1, wherein in S5, the functions encoded by the adjacently executed instructions are made identical and the opcodes are made different only by individual bits, or the opcodes encoded by the adjacently executed instructions are made identical and the functions are made different only by individual bits.