CN121116203A - A method, apparatus, device, and medium for erasing data from a memory. - Google Patents
A method, apparatus, device, and medium for erasing data from a memory.Info
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- CN121116203A CN121116203A CN202511622033.4A CN202511622033A CN121116203A CN 121116203 A CN121116203 A CN 121116203A CN 202511622033 A CN202511622033 A CN 202511622033A CN 121116203 A CN121116203 A CN 121116203A
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Abstract
The invention provides a data erasing method, device, equipment and medium of a memory, wherein the data erasing method comprises the steps of obtaining a first average abrasion degree and a second average abrasion degree, reading corresponding mapping tables at all levels according to a logic address to be erased, determining an erasing mode according to a comparison result of the first average abrasion degree and the second average abrasion degree, determining and clearing mapping relation of a maximum mapping table item in the mapping tables at all levels according to the logic address to be erased in the first mode, updating a physical address corresponding to the logic address to be erased in the mapping relation of the mapping table item in the mapping tables at all levels to a physical address of preset invalid data in the second mode, and erasing user data and the invalid data. The data erasing method, the device, the equipment and the medium of the memory provided by the invention are used for solving the technical problem that the service lives of the mapping table block and the user data block are not synchronous.
Description
Technical Field
The present invention relates to the field of storage, and in particular, to a method, apparatus, device, and medium for erasing data in a memory.
Background
In the existing storage architecture, a mapping table of a Flash Translation Layer (FTL) and user data are stored in a mapping table block and a user data block, respectively. Since FTL mapping tables need to be updated frequently in response to host writing, trim, etc., the write amplification of mapping table blocks is much higher than that of user data blocks, making them life-time bottlenecks.
Conventional schemes attempt to alleviate this problem by optimizing Garbage Collection (GC) flow or wear leveling (WEAR LEVELING), but fail to fundamentally change the frequently updated nature of the mapping table, so that the actual wear rate of the mapping table blocks continues to be higher than the user data blocks. Because the wear rates of the mapping table blocks and the user data blocks are not consistent, life synchronization is difficult to achieve. The prior method can not ensure the performance and simultaneously lead the service lives of the mapping table blocks and the user data blocks to be cooperated to an ideal state. Therefore, there is a need for improvement.
Disclosure of Invention
The invention provides a data erasing method, device, equipment and medium of a memory, which are used for solving the technical problem that the service lives of a mapping table block and a user data block are not synchronous.
The invention provides a data erasing method of a memory, which comprises the following steps:
responding to an erasing command of a host, and acquiring first average abrasion degrees of all mapping table blocks and second average abrasion degrees of all user data blocks;
reading corresponding mapping tables at all levels from the mapping table blocks according to the logic address to be erased in the erasing command;
Determining an erasure mode according to a comparison result of the first average wear degree and the second average wear degree;
When the erasing mode is a first mode, determining and clearing the mapping relation of the maximum mapping table item in each level of mapping table according to the logic address to be erased in the erasing command, and writing the updated each level of mapping table into the corresponding mapping table block;
when the erasing mode is a second mode, updating the corresponding physical address of the logical address to be erased in the mapping relation of mapping table items in each level of mapping table to be the physical address of preset invalid data;
And erasing the corresponding user data and invalid data according to the mapping relation of the mapping table items in the updated mapping tables of all levels.
In an embodiment of the present invention, the first average wear level is an average value of the number of erasures of all physical blocks storing the mapping table, the second average wear level is an average value of the number of erasures of all physical blocks storing the user data, and the determining the erasure pattern according to the comparison result of the first average wear level and the second average wear level includes:
Comparing the first average wear degree to the second average wear degree:
determining that the erase mode is a first mode when the first average wear level is less than the second average wear level;
and when the first average wear degree is larger than or equal to the second average wear degree, determining that the erasing mode is a second mode.
In an embodiment of the present invention, determining and clearing a mapping relation of a maximum mapping table entry in each level of mapping tables according to a logical address to be erased in the erase command, and writing each level of updated mapping tables into a corresponding mapping table block includes:
determining a maximum mapping table item according to a logic address to be erased in the erasing command, wherein the maximum mapping table item is positioned in at least one mapping table;
And clearing the mapping relation of all the maximum mapping table items, and writing the updated mapping tables of all levels into the corresponding mapping table blocks.
In an embodiment of the present invention, the determining the maximum mapping table according to the logical address to be erased in the erase command includes:
according to the logic address to be erased, starting from the mapping table of the highest level, performing screening operation step by step downwards, and determining the maximum mapping table item;
wherein the filtering operation for the mapping table of the current hierarchy includes:
screening out a mapping table item with intersection between a logic address range of the mapping table item and the logic address to be erased, and recording the mapping table item as a item to be judged;
For each item to be determined, according to the comparison result of the logic address range and the logic address to be erased, determining the item to be the largest mapping table item or taking the item to be the entry item for executing the screening operation on the mapping table of the next level.
In an embodiment of the present invention, for each item to be determined, according to a comparison result between a logical address range and the logical address to be erased, determining the item to be the largest mapping table item or using the item to be the entry for performing the filtering operation on the mapping table of the next level includes:
For each item to be determined, determining whether the logical address range is completely within the logical address to be erased:
if yes, judging the item to be judged as the maximum mapping table item;
Otherwise, judging the item to be judged as an entry item, and executing the screening operation based on a mapping table of the next level pointed by the entry item.
In an embodiment of the present invention, updating the physical address corresponding to the logical address to be erased in the mapping relation of the mapping table items in the mapping tables of each level to the physical address of the preset invalid data includes:
Inquiring the mapping relation of mapping table items in each level of mapping table according to the logical address to be erased so as to obtain the physical address of the user data pointed by the mapping relation;
And updating a mapping table item pointing to the physical address of the user data in the mapping relation into the physical address of preset invalid data.
In an embodiment of the present invention, the updating the mapping table entry pointing to the physical address of the user data in the mapping relationship to the physical address of the preset invalid data includes:
Reading user data from the user data blocks according to the physical address of the user data, and synchronously writing corresponding invalid data into the idle user data blocks;
and acquiring the physical address of the invalid data, and updating a mapping table item pointing to the physical address of the user data in a mapping relation into a preset physical address of the invalid data according to the physical address of the user data and the corresponding physical address of the invalid data.
The invention also provides a data erasing device of the memory, and a data erasing method of the memory is applied, and the data erasing device comprises:
the data acquisition module is used for responding to an erasure command of the host computer and acquiring the first average abrasion degree of all mapping table blocks and the second average abrasion degree of all user data blocks;
The data reading module is used for reading corresponding mapping tables at all levels from the mapping table blocks according to the logic address to be erased in the erasing command;
The wear comparison module is used for determining an erasure mode according to the comparison result of the first average wear degree and the second average wear degree;
The first erasing module is used for determining and clearing the mapping relation of the maximum mapping table item in each level of mapping table according to the logic address to be erased in the erasing command when the erasing mode is the first mode, and writing the updated each level of mapping table into the corresponding mapping table block;
The second erasing module is used for updating the corresponding physical address of the logical address to be erased in the mapping relation of the mapping table items in each level of mapping table into the physical address of the preset invalid data when the erasing mode is the second mode;
and the third erasing module is used for erasing the corresponding user data and invalid data according to the mapping relation of the mapping table items in the updated mapping tables of all levels.
The invention also provides an electronic device comprising a storage device, a processor and a computer program stored in the storage device and executable on the processor, the processor executing the steps of the data erasing method of the memory.
The invention also provides a computer readable storage medium storing a computer program which when executed by a processor implements the steps of the data erasing method of the memory.
The method has the beneficial effects that by introducing a mechanism for selecting the erasing mode according to the comparison of the average abrasion degree of the mapping table block and the user data block, the problem of the reduction of the whole service life of the memory caused by unbalanced abrasion of the mapping table block and the user data block is effectively solved. When the user data block wears more severely, the first mode is adopted, write operations are guided to relatively durable mapping table blocks by clearing and updating high-level mapping table entries, and the wear of the mapping table blocks is actively accelerated to realize balance. When the mapping table block wears more severely, then the second mode is used to significantly reduce the write frequency to the mapping table block by redirecting data to the invalid data region and delaying updating the mapping table.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application. It is evident that the drawings in the following description are only some embodiments of the present application and that other drawings may be obtained from these drawings without inventive effort for a person of ordinary skill in the art.
In the drawings:
FIG. 1 is a flow chart of a method for erasing data in a memory according to an embodiment of the invention;
FIG. 2 is a schematic diagram of a data erasing apparatus of a memory according to an embodiment of the invention;
Fig. 3 is a schematic diagram of an electronic device according to an embodiment of the present invention.
The reference numerals are 100, a data acquisition module, 200, a data reading module, 300, a wear comparison module, 400, a first erasing module, 500, a second erasing module, 600, a third erasing module, 700, an electronic device, 710, a storage device, 720 and a processor.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments, and details in this specification may be modified or changed from various points of view and applications without departing from the spirit of the invention, and the following examples and features of the examples may be combined with each other without conflict.
It should be noted that the illustrations provided in the following embodiments merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complicated.
In the following description, numerous details are set forth in order to provide a more thorough explanation of embodiments of the present invention, it will be apparent, however, to one skilled in the art that embodiments of the present invention may be practiced without these specific details, in other embodiments, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the embodiments of the present invention.
The invention discloses a data erasing method of a memory, which can be applied to the memory, and two different data erasing modes are selected by dynamically sensing and comparing the abrasion states of a mapping table block and a user data block in the memory, so that the abrasion rates of the mapping table block and the user data block are actively adjusted. The service life consumption of the mapping table block and the user data block is cooperated, so that the technical problem that the service life of the whole memory is limited due to premature loss of one party is solved, and finally the durability of the memory is obviously prolonged.
Referring to FIG. 1, in some embodiments, the data erasure method may include the steps of obtaining a first average wear level of all mapping table blocks and a second average wear level of all user data blocks in response to an erasure command of a host, wherein the first average wear level is an average of erasure times of all physical blocks of a storage mapping table, and the second average wear level is an average of erasure times of all physical blocks of storage user data.
In some embodiments, after receiving an erase command of the host, the controller of the memory may obtain a first average wear level of all the mapping table blocks. Specifically, the memory has maintained therein wear statistics that record the number of erasures per physical block. The mapping table block is a physical block dedicated to storing the flash translation layer mapping table. The controller calculates a first average wear level by querying the wear statistics, accumulating the respective number of erasures for all physical blocks currently marked for storing mapping tables, and dividing by the total number of blocks of the mapping tables. The first average wear level represents the average health and life consumption level of all map blocks currently.
In some embodiments, the controller of the memory may obtain the second average wear level of all user data blocks in parallel or sequentially. The user data block is a physical block dedicated to the storage host issuing user data. The controller uses the same calculation method to inquire the wear statistics information, accumulates the respective erasure times of all the physical blocks currently marked for storing user data, and then divides the total number of the user data blocks to calculate a second average wear degree. The second average wear level represents the average health and life consumption of the entire user data block.
Referring to FIG. 1, in some embodiments, the data erasing method may further include a step S20 of reading corresponding mapping tables from the mapping table blocks according to the logical address to be erased in the erase command.
In some embodiments, the controller performs an operation of reading mapping tables of respective levels from the mapping table blocks according to the logical address to be erased carried in the erase command. Specifically, the controller first analyzes the erase command, and precisely extracts the start address and length information of the logical address range that the host requests to erase. The controller then performs a lookup from the highest level mapping table according to the mapping table tree hierarchy employed by the storage system. The controller calculates the mapping table items corresponding to the logic address range to be erased in the mapping table of the highest level, and accesses the level mapping table of the next level stored in the specific mapping table block according to the physical addresses recorded in the mapping table items.
In some embodiments, the controller repeats the above-described lookup process, traversing the mapping table hierarchy step by step deep until the mapping table to the last level is located. In this process, all the accessed mapping tables having intersections of the logical address ranges with the logical address ranges to be erased are read from the mapping table blocks stored in them and temporarily loaded into the cache.
Referring to FIG. 1, in some embodiments, the data erasing method may further include a step S30 of determining an erasing mode according to a comparison result of the first average wear level and the second average wear level.
In some embodiments, when step S30 is performed, specifically, S30 may include:
Comparing the first average wear degree to the second average wear degree:
When the first average abrasion degree is smaller than the second average abrasion degree, determining that the erasing mode is a first mode;
and when the first average wear degree is greater than or equal to the second average wear degree, determining that the erasing mode is the second mode.
In some embodiments, when the first average wear level is determined to be less than the second average wear level, it is indicated that the overall wear level of the user data block has exceeded the mapping table block at the current time. To balance both lifetimes, the controller determines the erase mode to be the first mode at this time. In the first mode, the user data block wears more severely, and a part of the write operation load or wear pressure is transferred from the user data block to a relatively good mapping table block by adopting a specific data management strategy, so that the wear rate of the mapping table block is actively accelerated to catch up with the wear progress of the user data block.
In some embodiments, when the first average wear level is determined to be greater than or equal to the second average wear level, it is indicative that the overall wear level of the mapping table block has reached or even exceeded the user data block at the current time. The controller determines the erase mode to be the second mode at this time. In the second mode, the mapping table blocks which are already at a relatively high wear level can be protected, the writing and erasing operations on the mapping table blocks are reduced as much as possible by adopting a more conservative or optimized strategy, and the further increase of the wear speed is slowed down, so that the whole memory failure caused by the premature exhaustion of the mapping table is prevented, and the long-term reliable operation of the storage system is ensured.
Referring to fig. 1, in some embodiments, the data erasing method may further include the steps of determining and clearing a mapping relationship of a maximum mapping table entry in each level of mapping tables according to a logical address to be erased in the erase command when the erase mode is the first mode, and writing the updated each level of mapping tables into the corresponding mapping table blocks.
In some embodiments, when executing step S40, specifically, S40 may include determining a maximum mapping table entry according to a logical address to be erased in the erase command, where the maximum mapping table entry is located in at least one mapping table. The maximum mapping table entry refers to a mapping table entry whose logical address range is completely contained in the logical address range to be erased and is the highest-level mapping table in the mapping table.
In some embodiments, when step S41 is performed, specifically, step S41 may include:
according to the logic address to be erased, starting from the mapping table of the highest level, performing screening operation downwards step by step, and determining the maximum mapping table item;
The filtering operation for the mapping table of the current level comprises the following steps:
Screening out a mapping table item with intersection between a logic address range of the mapping table item and a logic address to be erased, and marking the mapping table item as an item to be judged;
For each item to be determined, according to the comparison result of the logic address range and the logic address to be erased, the item is determined as the maximum mapping table item, or the item is used as an entry item for executing screening operation on the mapping table of the next level.
In some embodiments, the process of determining the largest mapping table entry may be a precise positioning process that performs a recursive or iterative lookup in the mapping table tree structure. The controller may start the lookup process from the mapping table of the highest level (e.g., the first-level mapping table) and prepare mapping tables (e.g., the second-level mapping table and the third-level mapping table) that go deep to the next level step by step, so as to screen out all the largest mapping table entries that need to be cleared of the mapping relationship.
In some embodiments, mapping table entries in which the logical address ranges of the mapping table entries intersect with the logical address to be erased are filtered out, and the mapping table entries are marked as entries to be determined, so that the checking range is reduced rapidly, only those mapping table entries which are possibly related to the logical address of the current erasing operation are concerned, and those mapping table entries in which the logical address ranges do not overlap with the address ranges to be erased are ignored, thereby improving the processing efficiency.
In some embodiments, for example, assume that the logical address range to be erased is 580 to 3000, and the total logical address range it manages is 1 to 10000 in the highest-level primary mapping table. Then, these three mapping entries representing logical address ranges 1 to 1000, 1001 to 2000, and 2001 to 3000 all intersect with the address range to be erased (580-3000), so they are all screened out as entries to be determined for the current level (primary mapping table).
In some embodiments, for each item to be determined, determining it as the largest mapping table item or as an entry for performing a screening operation on the mapping table of the next level according to the comparison result of its logical address range and the logical address to be erased may include:
For each item to be determined, determining whether the logical address range is completely within the logical address to be erased:
if yes, judging the item to be judged as the maximum mapping table item;
otherwise, the item to be determined is determined to be the entry item, and the screening operation is executed based on the mapping table of the next level pointed by the entry item.
In some embodiments, for each item to be determined that is screened out, a controller checks each item to be determined one by one to determine whether the full logical address range managed by the controller is completely within the logical address range to be erased.
In some embodiments, if the logical address range of a certain to-be-determined item is completely contained in the to-be-erased logical address range, the controller may immediately determine that the to-be-determined item is the largest mapping table item to be searched. That is, the entire logical address space managed by the mapping table entry needs to be erased, so that it can be directly processed as a whole without further looking down the low-level mapping table pointed to by the mapping table entry.
In some embodiments, for example, in the above example, the primary mapping table represents mapping entries 1001 to 2000 and 2001 to 3000, whose entire address range lies in the range 580 to 3000 to be erased, and thus can be determined directly as the largest mapping entry.
In some embodiments, if the logical address range of a certain to-be-determined entry is not completely within the logical address range to be erased, the controller determines that the to-be-determined entry is not the largest mapping table entry of the hierarchy, but is an entry.
In some embodiments, the role of the entry is to provide an access path, and the controller will again perform the filtering operations of the above embodiments based on the next level mapping table to which this entry points, so that the largest mapping table entry continues to be found at a finer address granularity.
In some embodiments, for example, a mapping table of 1 to 1000 is represented in the primary mapping table, with only a portion (580-1000) of the address range (1-1000) lying within the range (580-3000) to be erased, and another portion (1-579) not being located therein, so that it cannot be determined as the largest mapping table entry, but rather as the entry. The controller then accesses the secondary mapping table (assuming its management address is 1-100,101-200, a.the.m., 901-1000) to which the entry points. In this secondary mapping table, the mapping entries representing 601-700,701-800,801-900,901-1000 have address ranges well within the 580-3000 range to be erased, so they are determined as the largest mapping entries in the secondary mapping table. While the mapping table entries representing 501-600 have their address ranges partially overlapping the range to be erased (580-600 being in range, 501-579 not) so that it becomes a new entry at this level, directing the controller to continue accessing the tertiary mapping table to which it points, the mapping table entries that are fully within the range to be erased, such as 581-590, being the largest mapping table entries, are finalized in the finer address management unit (e.g., 1-10,11-20,..) as the mapping table entries.
In some embodiments, step S40 may further include step S42 of clearing mapping relation of all maximum mapping table items, and writing the updated mapping tables of each level into corresponding mapping table blocks.
In some embodiments, flushing the mapping relationship of all largest mapping entries refers to placing physical block address information recorded internally of those specific mapping entries, which points to stored user data, into an invalid state, e.g., those mapping entries may be marked as an idle or invalid state bit, or the physical address value to which they point may be set to a specific, invalid or unmapped value.
In some embodiments, for example, once the mapping entry representing logical addresses 1001 through 2000 and 2001 through 3000 in the primary mapping table is determined to be the largest mapping entry, the mapping relationship of these two entries is immediately emptied. Likewise, in the secondary mapping table, mapping entries representing 601 to 700, 701 to 800, 801 to 900, and 901 to 1000 are also emptied. In the three-level mapping table, the mapping entries representing logical addresses 581 to 590 and 582 to 600 (the specific range depends on the granularity division) are also cleared of their mapping relationship. For entry entries like 1 to 1000 in the primary mapping table, the mapping relationship itself is not cleared in this step, because the logical address range managed by it is not completely covered by the to-be-erased range, and the clearing operation is strictly limited to those maximum mapping entries whose all logical addresses need to be erased.
In some embodiments, after completing the clearing of the mapping relationship of all the identified maximum mapping table entries, the operation of writing the updated mapping tables of each level into the corresponding mapping table blocks may be performed. Since the above-described flushing operation changes the contents of the mapping table, these changes must be persisted to the non-volatile storage medium to ensure consistency of the mapping information. The controller writes the changed mapping tables from the cache to the corresponding mapping table blocks.
In some embodiments, it is emphasized that in storage media such as NAND flash memory, the write operation described above requires programming the updated entire mapping table page or entire mapping table block to a new physical page in a pre-erased, free mapping table block, since in-place overwrite is not supported. The metadata is then updated to reflect the latest storage locations of these mapping tables. The process can cause the actual writing operation to the mapping table block, when the average abrasion degree of the mapping table block is lower than that of the user data block, the writing load of the mapping table block is actively increased, the abrasion degree of the mapping table block is improved, the abrasion level of the user data block is gradually approximated, and finally the equalization of the abrasion degree of the storage medium is realized.
Referring to fig. 1, in some embodiments, the data erasing method may further include the steps of updating a physical address corresponding to a logical address to be erased in a mapping relationship of mapping entries in each level of mapping table to a physical address of preset invalid data when the erasing mode is the second mode, and writing each level of updated mapping table into a corresponding mapping table block after a preset duration.
In some embodiments, when executing step S50, step S50 may specifically include the step of querying the mapping relationship of the mapping entries in each level of mapping table according to the logical address to be erased to obtain the physical address of the user data pointed to by the mapping relationship.
In some embodiments, the controller needs to traverse all of the mapping levels associated with the logical address to be erased. The controller starts from the mapping table of the highest level, searches downwards step by step according to the logic address range to be erased, and locates all the mapping table items of which the logic addresses in the mapping table of the lowest level fall into the range to be erased. The mapping entries of these lowest level mapping tables directly contain the physical addresses where the user data is stored.
In some embodiments, the step S50 may further include the step S52 of updating the mapping table entry pointing to the physical address of the user data in the mapping relationship to the physical address of the preset invalid data.
In some embodiments, when step S52 is performed, specifically, S52 may include the following steps:
Reading user data from the user data blocks according to the physical addresses of the user data, and synchronously writing corresponding invalid data into the idle user data blocks;
And acquiring the physical address of the invalid data, and updating a mapping table item pointing to the physical address of the user data in the mapping relation into the preset physical address of the invalid data according to the physical address of the user data and the corresponding physical address of the invalid data.
In some embodiments, the controller first reads the original user data content from the corresponding user data block into the cache according to the physical address of the acquired user data. Next, the controller does not simply discard the data, but rather performs a specific write operation by writing a predefined invalid data pattern representing the erased state (e.g., all 0s, all 1 s, or a specific identifier) onto the new physical page in the free user data block. The essence of this operation is to replace and fix the data originally stored in the old physical location corresponding to the logical address to be erased to the new physical location, and the content stored in the new location is unified invalid data.
In some embodiments, after successful writing of invalid data into the free user data block, the controller will obtain the specific physical address of these newly written invalid data in the free user data block. Subsequently, the controller performs updating of the mapping relation. By traversing the physical address of each user data to be processed, finding the corresponding mapping table entry in the mapping table, and modifying the physical address recorded in the table entry from the old physical address originally pointed to the user data to the new physical address newly obtained and storing invalid data. Through the operation, when the host reads the logical address later, the physical position for storing invalid data is directly accessed according to the updated mapping relation, so that the erasing state is returned, the logical erasing effect is realized, and the time-consuming physical block erasing is not needed immediately.
In some embodiments, step S50 may further include the step of writing the updated mapping tables of each level into the corresponding mapping table blocks after the preset time period in step S53.
In some embodiments, after the mapping updates are completed, the updates are temporarily held in a cache and are not immediately written to the non-volatile mapping table blocks. At this point, the controller may start a timer waiting for a preset period of time. During this period, subsequent write operations to the same or adjacent logical addresses that may occur during this period are allowed to merge with the map updates generated by the present erase operation. After the preset time length is reached, the controller writes the final mapping tables of all levels, which accumulate the multiple updating results, into the mapping table blocks corresponding to the final mapping tables at one time. The delay merging writing mechanism remarkably reduces the actual writing times and frequency of mapping table blocks, and effectively slows down the increase of the abrasion speed.
Referring to fig. 1, in some embodiments, the data erasing method may further include step S60 of erasing the corresponding user data and invalid data according to the mapping relation of the mapping table entries in the updated mapping tables.
In some embodiments, according to the mapping relation of the mapping table items in the updated mapping tables of each level, it can be accurately identified which user data blocks contain invalid data that can be erased. The controller systematically scans the mapping tables at each level, particularly the lowest level, and analyzes the physical address pointers recorded by each mapping table entry. The goal of the controller is to find out those physical blocks whose data contents are no longer referenced by any valid logical addresses.
In some embodiments, in the first mode erase operation, when the mapping relation of the largest mapping entries is cleared, the user data blocks, to which the entries were originally directed, storing user data, become invalid data, because they are no longer accessible through the mapping table.
In some embodiments, in the second mode erase operation, although the mapping is updated to point to the new physical address where the invalid data is stored, the data at the old physical address where the valid user data was originally stored also becomes invalid data. By comparing the mapping table with the actual data of the user data block, a list can be constructed containing all these invalid data physical addresses.
In some embodiments, after accurately identifying all physical addresses storing invalid data, an operation of erasing the corresponding user data and invalid data may be performed. Here, the erase refers to a physical erase operation of a physical block of the NAND flash memory, i.e., a garbage collection operation. The controller may initiate an erase command for a user data block containing invalid data. If all pages within a block of user data store invalid data, then the block may be erased in its entirety. If one user data block contains valid data and invalid data at the same time, the controller usually performs data moving operation first, reads out the remaining valid data in the block and writes it into a new idle user data block, and updates the corresponding mapping relationship at the same time, so as to ensure that the valid data cannot be lost. After that, this user data block, which originally stores valid and invalid data in a mixed manner, becomes invalid in its entirety, so that the entire physical erasure can be performed securely. This physical erase operation resets the entire user data block to an initial, reprogrammable state, and the reclaimed free block is then added to the free block pool waiting for new user data or map data to be stored.
Therefore, in the scheme, a mechanism for selecting the erasing mode according to the comparison of the average abrasion degree of the mapping table block and the user data block is introduced, so that the problem of the reduction of the whole service life of the memory caused by unbalanced abrasion of the mapping table block and the user data block is effectively solved. When the user data block wears more severely, the first mode is adopted, write operations are guided to relatively durable mapping table blocks by clearing and updating high-level mapping table entries, and the wear of the mapping table blocks is actively accelerated to realize balance. When the mapping table block wears more severely, then the second mode is used to significantly reduce the write frequency to the mapping table block by redirecting data to the invalid data region and delaying updating the mapping table. By starting from the internal wear state of the memory, the data management strategy is dynamically adjusted, and the wear balance between the mapping table block and the user data block is autonomously realized under the condition of not depending on host intervention, so that the overall service life of the memory is prolonged.
Referring to fig. 2, the present invention also discloses a data erasing device of the memory, and the data erasing method can be applied to the data erasing device. The data erasing apparatus may include a data acquisition module 100, a data reading module 200, a wear comparison module 300, a first erasing module 400, a second erasing module 500, and a third erasing module 600.
In some embodiments, the data acquisition module 100 may be configured to acquire a first average wear level of all mapping table blocks and a second average wear level of all user data blocks in response to an erase command of the host;
in some embodiments, the data reading module 200 may be configured to read the mapping tables of the respective levels from the mapping table blocks according to the logical address to be erased in the erase command;
in some embodiments, the wear comparison module 300 may be configured to determine the erasure pattern based on a comparison of the first average wear level and the second average wear level;
In some embodiments, when the erase mode is the first mode, the first erase module 400 may be configured to determine and empty a mapping relationship of a maximum mapping table entry in each level of mapping tables according to a logical address to be erased in the erase command, and write the updated each level of mapping tables into the corresponding mapping table blocks;
in some embodiments, the second erasing module 500 may be configured to update a physical address corresponding to a logical address to be erased in a mapping relationship of mapping entries in each level of mapping tables to a physical address of preset invalid data when the erasing mode is the second mode;
In some embodiments, the third erasing module 600 may be configured to erase the corresponding user data and the invalid data according to the mapping relationship of the mapping entries in the updated mapping tables.
For specific limitations of the data erasing apparatus, reference may be made to the above limitations of the data erasing method, and the description thereof will not be repeated here. The respective modules in the above-described data erasing apparatus may be implemented in whole or in part by software, hardware, and combinations thereof. The modules can be embedded in or independent of a storage device in the electronic device in a hardware form, and can also be stored in the storage device in the electronic device in a software form, so that the storage device can call and execute operations corresponding to the modules.
Referring to fig. 3, in some embodiments, an electronic device 700 may include a memory device 710, a processor 720, and a bus, and may also include a computer program stored in the memory device 710 and executable on the processor 720, such as a program of a data erasure method of a memory.
In some embodiments, storage device 710 comprises at least one type of readable storage medium including flash memory, a removable hard disk, a multimedia card, a card-type storage device (e.g., SD or DX storage device, etc.), a magnetic storage device, a magnetic disk, an optical disk, etc. The storage device 710 may in some embodiments be an internal storage unit of the electronic device 700, such as a removable hard disk of the electronic device 700. The storage device 710 may also be an external storage device of the electronic device 700 in other embodiments, such as a plug-in mobile hard disk, a smart memory card (SMART MEDIA CARD, SMC), a Secure Digital (SD) card, a flash memory card (FLASH CARD) or the like, which are provided on the electronic device 700. Further, the storage device 710 may also include both internal and external storage units of the electronic device 700. The storage device 710 may be used not only to store application software installed in the electronic device 700 and various types of data, such as codes of a data erasing method of a memory, etc., but also to temporarily store data that has been output or is to be output.
In some embodiments, the processor 720 may be comprised of integrated circuits, such as a single packaged integrated circuit, or may be comprised of multiple integrated circuits packaged with the same or different functions, including one or more central processing units (Central Processing unit, CPU), microprocessors, digital processing chips, graphics processors, various control chips, and the like. The processor 720 is a Control Unit (Control Unit) of the electronic device 700, connects the respective components of the entire electronic device 700 using various interfaces and lines, and executes various functions of the electronic device 700 and processes data by running or executing programs or modules (e.g., programs of a data erasing method of a memory, etc.) stored in the storage device 710 and calling data stored in the storage device 710.
In some embodiments, processor 720 executes an operating system of electronic device 700 as well as various types of applications installed. Processor 720 executes an application program to implement the steps in the data erasure method of the memory described above.
In some embodiments, the computer program may be split into one or more modules, which are stored in the storage device 710 and executed by the processor 720 to complete the present application. One or more of the modules may be a series of computer program instruction segments capable of performing particular functions to describe the execution of the computer program in the electronic device 700. For example, the computer program may be divided into a data acquisition module 100, a data reading module 200, a wear comparison module 300, a first erase module 400, a second erase module 500, a third erase module 600, and so on.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (10)
1. A method for erasing data in a memory, comprising:
responding to an erasing command of a host, and acquiring first average abrasion degrees of all mapping table blocks and second average abrasion degrees of all user data blocks;
reading corresponding mapping tables at all levels from the mapping table blocks according to the logic address to be erased in the erasing command;
Determining an erasure mode according to a comparison result of the first average wear degree and the second average wear degree;
When the erasing mode is a first mode, determining and clearing the mapping relation of the maximum mapping table item in each level of mapping table according to the logic address to be erased in the erasing command, and writing the updated each level of mapping table into the corresponding mapping table block;
when the erasing mode is a second mode, updating the corresponding physical address of the logical address to be erased in the mapping relation of mapping table items in each level of mapping table to be the physical address of preset invalid data;
And erasing the corresponding user data and invalid data according to the mapping relation of the mapping table items in the updated mapping tables of all levels.
2. The method of claim 1, wherein the first average wear level is an average of the number of erasures of all physical blocks of the memory map, and the second average wear level is an average of the number of erasures of all physical blocks of the memory user data, and wherein determining the erase pattern based on the comparison of the first average wear level and the second average wear level comprises:
Comparing the first average wear degree to the second average wear degree:
determining that the erase mode is a first mode when the first average wear level is less than the second average wear level;
and when the first average wear degree is larger than or equal to the second average wear degree, determining that the erasing mode is a second mode.
3. The method for erasing data of a memory according to claim 1, wherein determining and clearing mapping relation of maximum mapping table item in each level of mapping table according to the logical address to be erased in the erase command, and writing the updated each level of mapping table into the corresponding mapping table block comprises:
determining a maximum mapping table item according to a logic address to be erased in the erasing command, wherein the maximum mapping table item is positioned in at least one mapping table;
And clearing the mapping relation of all the maximum mapping table items, and writing the updated mapping tables of all levels into the corresponding mapping table blocks.
4. The method for erasing data in a memory according to claim 3, wherein said determining a maximum mapping table according to the logical address to be erased in said erase command comprises:
according to the logic address to be erased, starting from the mapping table of the highest level, performing screening operation step by step downwards, and determining the maximum mapping table item;
wherein the filtering operation for the mapping table of the current hierarchy includes:
screening out a mapping table item with intersection between a logic address range of the mapping table item and the logic address to be erased, and recording the mapping table item as a item to be judged;
For each item to be determined, according to the comparison result of the logic address range and the logic address to be erased, determining the item to be the largest mapping table item or taking the item to be the entry item for executing the screening operation on the mapping table of the next level.
5. The method according to claim 4, wherein for each item to be determined, determining it as the largest mapping table item or as the entry item for performing the filtering operation on the mapping table of the next hierarchy according to the comparison result of the logical address range and the logical address to be erased, comprises:
For each item to be determined, determining whether the logical address range is completely within the logical address to be erased:
if yes, judging the item to be judged as the maximum mapping table item;
Otherwise, judging the item to be judged as an entry item, and executing the screening operation based on a mapping table of the next level pointed by the entry item.
6. The method for erasing data of a memory according to claim 1, wherein updating the physical address corresponding to the logical address to be erased in the mapping relation of the mapping table items in each level of mapping table to the physical address of the preset invalid data comprises:
Inquiring the mapping relation of mapping table items in each level of mapping table according to the logical address to be erased so as to obtain the physical address of the user data pointed by the mapping relation;
And updating a mapping table item pointing to the physical address of the user data in the mapping relation into the physical address of preset invalid data.
7. The method for erasing data in a memory according to claim 6, wherein updating the mapping table entry pointing to the physical address of the user data in the mapping relationship to the physical address of the preset invalid data comprises:
Reading user data from the user data blocks according to the physical address of the user data, and synchronously writing corresponding invalid data into the idle user data blocks;
and acquiring the physical address of the invalid data, and updating a mapping table item pointing to the physical address of the user data in a mapping relation into a preset physical address of the invalid data according to the physical address of the user data and the corresponding physical address of the invalid data.
8. A data erasing apparatus of a memory, wherein the data erasing apparatus of the memory according to any one of claims 1 to 7 is applied, the data erasing apparatus comprising:
the data acquisition module is used for responding to an erasure command of the host computer and acquiring the first average abrasion degree of all mapping table blocks and the second average abrasion degree of all user data blocks;
The data reading module is used for reading corresponding mapping tables at all levels from the mapping table blocks according to the logic address to be erased in the erasing command;
The wear comparison module is used for determining an erasure mode according to the comparison result of the first average wear degree and the second average wear degree;
The first erasing module is used for determining and clearing the mapping relation of the maximum mapping table item in each level of mapping table according to the logic address to be erased in the erasing command when the erasing mode is the first mode, and writing the updated each level of mapping table into the corresponding mapping table block;
The second erasing module is used for updating the corresponding physical address of the logical address to be erased in the mapping relation of the mapping table items in each level of mapping table into the physical address of the preset invalid data when the erasing mode is the second mode;
and the third erasing module is used for erasing the corresponding user data and invalid data according to the mapping relation of the mapping table items in the updated mapping tables of all levels.
9. An electronic device comprising a storage device, a processor and a computer program stored in the storage device and executable on the processor, characterized in that the processor implements the steps of the data erasure method of a memory according to any of claims 1-7 when the computer program is executed by the processor.
10. A computer-readable storage medium storing a computer program, wherein the computer program when executed by a processor implements the steps of the data erasing method of the memory according to any one of claims 1 to 7.
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