CN121076007A - Manufacturing method of semiconductor structure, semiconductor structure and image sensor - Google Patents
Manufacturing method of semiconductor structure, semiconductor structure and image sensorInfo
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- CN121076007A CN121076007A CN202511574687.4A CN202511574687A CN121076007A CN 121076007 A CN121076007 A CN 121076007A CN 202511574687 A CN202511574687 A CN 202511574687A CN 121076007 A CN121076007 A CN 121076007A
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Abstract
The invention discloses a manufacturing method of a semiconductor structure, the semiconductor structure and an image sensor, and belongs to the technical field of semiconductors; the method comprises the steps of forming a substrate, etching the substrate, forming a plurality of concave parts on the substrate, forming convex parts on the substrate adjacent to the concave parts, forming a barrier layer on the side wall of the convex parts, synchronously etching the substrate at the bottom of the concave parts and the substrate at the top of the convex parts, forming a first groove at the position of the concave parts, forming a second groove at the position of the convex parts, wherein the depth of the first groove is larger than that of the second groove, and filling media in the first groove and the second groove to form a first groove isolation structure and a second groove isolation structure. The manufacturing method of the semiconductor structure, the semiconductor structure and the image sensor can save the manufacturing cost.
Description
Technical Field
The present invention relates to semiconductor technology, and more particularly, to a method for manufacturing a semiconductor structure, and an image sensor.
Background
In some semiconductor processes, to meet the requirements of the semiconductor devices formed, deep trench isolation structures and shallow trench isolation structures having different depths are required to be formed on the substrate. For example, when the back-illuminated image sensor is formed, a deep trench isolation structure and a shallow trench isolation structure are formed on the photoelectric sensing region to reflect or refract incident light, so that the light conversion efficiency is improved.
However, when forming the deep trench isolation structure and the shallow trench isolation structure, one photomask is used to form the deep trench isolation structure, and another Zhang Guangzhao is needed to form the shallow trench isolation structure. Although the light conversion efficiency can be improved, the process cost can be greatly increased.
Disclosure of Invention
The invention aims to provide a manufacturing method of a semiconductor structure, the semiconductor structure and an image sensor, which can solve the problem of high manufacturing cost when forming a deep trench isolation structure and a shallow trench isolation structure.
In order to solve the technical problems, the invention is realized by the following technical scheme:
the invention provides a manufacturing method of a semiconductor structure, which comprises the following steps:
providing a substrate;
Forming a patterned hard mask layer on the substrate, etching the substrate, forming a plurality of recesses on the substrate, and forming protrusions on the substrate between adjacent recesses;
depositing an oxide layer on the substrate, the oxide layer covering the concave portion and the convex portion;
etching part of the oxide layer at the bottom of the concave part and the oxide layer at the top of the convex part, and reserving the oxide layer on the side wall of the convex part, wherein the oxide layer on the side wall of the convex part forms a barrier layer;
simultaneously etching the substrate at the bottom of the concave part and the substrate at the top of the convex part, forming a first groove at the position of the concave part, and forming a second groove at the position of the convex part, wherein the depth of the first groove is larger than that of the second groove;
And filling media in the first groove and the second groove to form a first groove isolation structure and a second groove isolation structure.
In an embodiment of the invention, the barrier layer covers the sidewalls of the protrusion and a portion of the bottom wall of the recess.
In one embodiment of the invention, the substrate at the bottom of the recess and the substrate at the top of the protrusion are etched simultaneously using a tetramethylammonium hydroxide solution.
In an embodiment of the present invention, as the depth of the first trench increases, the greater the width of the barrier layer, the greater the spacing between the first trench isolation structure and the second trench isolation structure.
In an embodiment of the present invention, the cross-sections of the first groove and the second groove are inverted triangles.
In an embodiment of the present invention, the medium filled in the first trench and the second trench is a high dielectric constant material.
The invention also provides a semiconductor structure formed by the manufacturing method of the semiconductor structure, and the semiconductor structure comprises the following steps:
A substrate;
the first groove isolation structure and the second groove isolation structure are arranged in the substrate, and the depth of the first groove isolation structure is larger than that of the second groove isolation structure.
The present invention also provides an image sensor including:
A circuit wiring layer;
a photodiode provided on one side of the circuit wiring layer;
the semiconductor structure as described above, provided on a side of the photodiode away from the circuit wiring layer;
The optical filter is arranged on one side of the semiconductor structure, which is far away from the photodiode;
And the micro lens is arranged on one side of the optical filter away from the semiconductor structure.
In an embodiment of the present invention, in a growth direction of the image sensor, the second trench isolation structure in the semiconductor structure is located on a connection line between the microlens and the photodiode.
In an embodiment of the present invention, for each of the first trench isolation structures, a radial dimension of the first trench isolation structure gradually decreases as a depth of the first trench isolation structure increases, and for each of the second trench structures, a radial dimension of the second trench isolation structure gradually decreases as a depth of the second trench isolation structure increases.
In summary, the manufacturing method of the semiconductor structure, the semiconductor structure and the image sensor provided by the invention have the unexpected effects that when the first groove and the second groove are formed, concave parts are formed on the substrate, convex parts are formed between the concave parts, then a barrier layer is formed on the side wall of the concave part, the substrate at the bottom of the concave part and the substrate at the top of the convex part are etched by taking the barrier layer as a mask, the first groove and the second groove with different depths are synchronously formed on the substrate, and finally, the first groove and the second groove are filled with media to form the first groove isolation structure and the second groove isolation structure with different depths. At this time, a photomask can be used to form the first trench isolation structure and the second trench isolation structure with different depths, so that one photomask is saved, and the manufacturing cost is greatly saved. When the formed semiconductor structure is arranged on the back-illuminated image sensor, the semiconductor structure is arranged between the micro lens and the photodiode, so that the photoelectric conversion efficiency is increased. Meanwhile, the radial dimension of the groove isolation structure is gradually reduced along with the increase of the depth of the groove isolation structure, so that the reflection and refraction of light are further increased, the light conversion efficiency is further improved, and the performance of the image sensor is improved.
Of course, it is not necessary for any one product to practice the invention to achieve all of the advantages set forth above at the same time.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram illustrating a structure of forming a pad oxide layer, a pad nitride layer and a photoresist layer according to an embodiment.
FIG. 2 is a schematic diagram of a structure for forming a recess in an embodiment.
FIG. 3 is a schematic diagram of an embodiment of forming an oxide layer.
FIG. 4 is a schematic diagram of a structure for forming a barrier layer according to an embodiment.
Fig. 5 is a schematic structural diagram of forming a first trench and a second trench in an embodiment.
Fig. 6 is a schematic structural diagram of a first trench and a second trench filled with a medium according to an embodiment.
Fig. 7 is a schematic structural diagram of forming a first trench isolation structure and a second trench isolation structure in an embodiment.
Fig. 8 is a schematic structural diagram of an image sensor in an embodiment.
Description of the reference numerals:
101. Substrate, 1011, concave portion, 1012, convex portion, 102, hard mask layer, 1021, pad oxide layer, 1022, pad nitride layer, 103, photoresist layer, 1031, opening, 104, oxide layer, 1041, barrier layer, 1051, first trench, 1052, second trench, 106, dielectric layer, 1061, first trench isolation structure, 1062, second trench isolation structure, 201, circuit wiring layer, 202, photodiode, 203, filter layer, 204, microlens.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
In the present application, it should be noted that, as terms such as "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., appear, the indicated orientation or positional relationship is based on that shown in the drawings, only for convenience of description and simplification of the description, and does not indicate or imply that the apparatus or element in question must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the application. Furthermore, the terms "first," "second," and the like, as used herein, are used for descriptive and distinguishing purposes only and are not to be construed as indicating or implying a relative importance.
As shown in fig. 8, microlenses 204 and photodiodes 202 of the conventional front-illuminated sensor are disposed on both sides of the circuit wiring layer 201. In operation of the front-illuminated sensor, light enters from the microlens 204, passes through the circuit wiring layer 201 between the microlens 204 and the photodiode 202, and reaches the photodiode 202 for photoelectric conversion. At this time, light is affected by the circuit wiring layer 201, which causes light loss and affects the photographing effect. The back-illuminated image sensor is characterized in that the position of the photodiode 202 is changed, the photodiode 202 is arranged between the micro lens 204 and the circuit wiring layer 201, and light enters the photodiode 202 directly after entering from the micro lens 204 to be subjected to photoelectric conversion, so that the exposure area of the photodiode 202 is increased, the loss of the light when passing through the circuit wiring layer 201 is reduced, the light efficiency is obviously improved, and the shooting effect is improved. However, in the low-light environment, the back-illuminated image sensor still has low photoelectric conversion efficiency due to weak light, and the present application forms a trench isolation structure with different depths between the photodiode 202 and the microlens 204, so as to reflect or refract the light, increase the energy of the light, and improve the light conversion efficiency.
Referring to fig. 1 to 7, the present application provides a method for fabricating a semiconductor structure, which comprises forming a patterned hard mask layer 102 on a substrate 101, etching the substrate 101, forming a plurality of recesses 1011 on the substrate 101, and forming protrusions 1012 on the substrate 101 between adjacent recesses 1011. Thereafter, an oxide layer 104 is formed over the substrate 101, and the oxide layer 104 is etched, leaving the oxide layer 104 on the sidewalls of the projections 1012, forming a barrier layer 1041. Next, the substrate 101 on the bottom 104 of the concave portion 1011 and the top of the convex portion 1012 is simultaneously etched using the barrier layer 1041 as a mask, and a first trench 1051 is formed at the position of the concave portion 1011 and a second trench 1052 is formed at the position of the convex portion 1012. Finally, a dielectric is deposited within the first trench 1051 and the second trench 1052, forming a first trench isolation structure 1061 and a second trench isolation structure 1062. The method for manufacturing a semiconductor structure provided by the application uses a photomask to form a first trench isolation structure 1061 and a second trench isolation structure 1062 with different depths.
Specifically, referring to fig. 1, in an embodiment of the present invention, a substrate 101 is provided, and the substrate 101 is, for example, a silicon substrate for forming a semiconductor structure. The material of the substrate 101 may be selected from undoped monocrystalline silicon, doped monocrystalline silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator (S-SiGeOI), silicon-on-insulator (SiGeOI), germanium-on-insulator (GeOI), and the like. In this embodiment, the substrate 101 is a single crystal silicon substrate, and is undoped single crystal silicon.
Referring to fig. 1 and 2, in one embodiment of the present invention, a patterned hard mask layer 102 is formed on a substrate 101 during formation of a semiconductor structure. In this embodiment, the hard mask layer 102 includes, for example, a pad oxide layer 1021 and a pad nitride layer 1022, the pad oxide layer 1021 is disposed on the substrate 101, and the pad nitride layer 1022 is disposed on the pad oxide layer 1021.
Referring to fig. 1, in an embodiment of the present invention, when forming the patterned hard mask layer 102, a pad oxide layer 1021 is formed on the substrate 101, and the pad oxide layer 1021 is used as a buffer layer to improve the stress between the substrate 101 and the pad nitride layer 1022 formed later. The pad oxide layer 1021 is, for example, a dense silicon oxide or other material, and the pad oxide layer 1021 may be formed by any one of a dry oxygen oxidation method, a wet oxygen oxidation method, an in-situ vapor growth method, or the like.
Referring to fig. 1, in an embodiment of the present invention, after forming a pad oxide 1021, a pad nitride 1022 is formed on the pad oxide 1021. The pad nitride layer 1022 is, for example, a silicon nitride layer, and may be formed by, for example, low pressure chemical vapor deposition. The pad nitride layer 1022 serves as a mask during subsequent shallow trench isolation formation to protect the substrate 101 from damage during etching of the substrate 101.
Referring to fig. 1, in an embodiment of the present invention, after forming the pad nitride layer 1022, a patterned photoresist layer 103 is formed on the pad nitride layer 1022, and a plurality of openings 1031 are disposed on the patterned photoresist layer 103, wherein the openings 1031 are used to define the positions of the recesses 1011 on the substrate 101. Specifically, a photoresist may be coated on the pad nitride layer 1022, and the photoresist over the recess 1011 to be formed is removed using an alkaline solution wet process or an ashing process using a dry process, and the coated photoresist is patterned to form the patterned photoresist layer 103.
Referring to fig. 1 to 2, after forming the patterned photoresist layer 103, the pad nitride layer 1022 and the pad oxide layer 1021 at the bottom of the opening 1031 are sequentially etched to form the patterned mask layer 102 in an embodiment of the invention. Then, the patterned photoresist layer 103 is removed, and the substrate 101 is etched using the pad nitride layer 1022 and the pad oxide layer 1021 as masks, thereby forming a plurality of recesses 1011 in the substrate 101.
Referring to fig. 1 to 2, in an embodiment of the present invention, since the pad nitride layer 1022, the pad oxide layer 1021 and the substrate 101 are made of different materials, two or more etches are required during etching. In some embodiments, dry etching may be used when etching the pad nitride layer 1022 and the pad oxide layer 1021, and the pad nitride layer 1022 and the pad oxide layer 1021 under the opening 1031 may be removed by one etching process using a mixed gas of CF 4 and CHF 3. In other embodiments, the pad nitride 1022 and the pad oxide 1021 may be etched by a wet etch process, such as a hot phosphoric acid at a temperature in the range of 140-200 ℃ to etch the pad nitride 1022 and a hydrofluoric acid at a concentration of 1-10% to etch the pad oxide 1021.
Referring to fig. 1-2, in one embodiment of the present invention, the etched substrate 101 may be dry etched using one or more of SF 6、CF4、CF4/H2、CHF3、CF4/O2 and HBr, such as HBr and CF 4, to form the recess 1011. After forming the recess 1011, the pad nitride layer 1022 and the pad oxide layer 1021 are removed in sequence.
Referring to fig. 2 to 7, in an embodiment of the present application, a plurality of concave portions 1011 extend from the surface of the substrate 101 into the substrate 101, and the substrate 101 in two adjacent concave portions 1011 forms convex portions 1012. The present application is not limited to the shape of the recess 1011, and in the present embodiment, the recess 1011 is rectangular in cross section. In other embodiments, the recess 1011 may have other cross-sections, such as a trapezoid, or a rectangle with rounded corners, a trapezoid, etc.
It should be noted that, as shown in fig. 2 to 7, the depth of the recess 1011 is not limited by the present application, and the depth of the recess 1011 is linearly related to the depth difference between the finally formed first trench isolation structure 1061 and the second trench isolation structure 1062. The greater the depth of the recess 1011, the greater the depth difference between the first trench isolation structure 1061 and the second trench isolation structure 1062 formed, and the smaller the depth of the recess 1011, the smaller the depth difference between the first trench isolation structure 1061 and the second trench isolation structure 1062 formed. In the present embodiment, the depth of the concave portion 1011 is less than 0.5um, specifically, for example, 0.4um, 0.3um, or 0.2um. The width of the recess 1011 and the width of the protrusion 1012 are also not limited by the present application, and the width of the recess 1011 and the width of the protrusion 1012 are related to the width of the finally formed first trench isolation structure 1061, the width of the second trench isolation structure 1062, and the width of the space between the first trench isolation structure 1061 and the second trench isolation structure 1062. The larger the width of the recess 1011, the larger the sum of the width of the first trench isolation structure 1061 and the width of the space between the first trench isolation structure 1061 and the second trench isolation structure 1062 is formed, and the smaller the width of the recess 1011, the smaller the sum of the width of the first trench isolation structure 1061 and the width of the space between the first trench isolation structure 1061 and the second trench isolation structure 1062 is formed. The larger the width of the protrusion 1012, the larger the width of the second trench isolation structure 1062, and the smaller the width of the protrusion 1012, the smaller the width of the second trench isolation structure 1062.
Referring to fig. 2 to 4, in one embodiment of the present invention, after forming the recess 1011, a barrier 1041 is formed on the sidewall of the protrusion 1012. In this embodiment, an oxide layer 104 may be deposited on the substrate 101, and the oxide layer 104 covers the concave portions 1011 and the convex portions 1012 of the surface of the substrate 101. Thereafter, portions of the oxide layer 104 at the bottom of the recess 1011 and the oxide layer 104 at the top of the protrusion 1012 are etched, leaving the oxide layer 104 on the sidewalls of the protrusion 1012, and the oxide layer 104 on the sidewalls of the protrusion 1012 forms a barrier 1041.
Referring to fig. 2 to 3, in an embodiment of the present invention, after forming the recess 1011, a silicon oxide layer is deposited on the substrate 101 by chemical vapor deposition (Chemical Vapor Deposition, CVD) or high-density plasma chemical vapor deposition (HIGH DENSITY PLASMA-Chemical Vapor Deposition, HDP-CVD) to form the oxide layer 104. Oxide layer 104 fills recess 1011 and covers protrusion 1012.
Referring to fig. 3 to 4, in an embodiment of the present invention, after forming the oxide layer 104, a portion of the oxide layer 104 at the bottom of the concave portion 1011 and the oxide layer 104 at the top of the convex portion 1012 are removed by a dry etching method, so that the oxide layer 104 on the sidewall of the convex portion 1012 remains, and the oxide layer 104 on the sidewall of the convex portion 1012 forms a barrier layer 1041. Specifically, the oxide layer 104 in the middle portion of the bottom of the concave portion 1011 and the oxide layer 104 on the top of the convex portion 1012 may be etched using a fluorine-containing gas such as CHF 3、CF4、SF6、C2F6 or C 3F4.
Referring to fig. 4, in one embodiment of the present application, a barrier 1041 is formed to cover the sidewalls of the protrusion 1012 (also the sidewalls of the recess 1011) and a portion of the bottom wall of the recess 1011. The application is not limited to the size of the barrier layer 1041 formed, and the width of the barrier layer 1041 on the sidewalls of the protrusions 1012 is related to the spacing between the first trench isolation structure 1061 and the second trench isolation structure 1062, and the greater the width of the barrier layer 1041 on the sidewalls of the protrusions 1012, the greater the width of the spacing between the first trench isolation structure 1061 and the second trench isolation structure 1062, and the smaller the width of the barrier layer 1041 on the sidewalls of the protrusions 1012, the smaller the width of the spacing between the first trench isolation structure 1061 and the second trench isolation structure 1062. In the present embodiment, the thickness of the barrier 1041 on the sidewall of the protrusion 1012 is, for example, 0.15um to 0.3um, specifically, for example, 0.2um. In this embodiment, the thickness of the barrier layer 1041 is perpendicular to the thickness direction of the substrate 101.
It should be noted that, as shown in fig. 4 and 7, if the layout of the first trench isolation structure 1061 and the second trench isolation structure 1062 is changed, the layout of the first trench isolation structure 1061 and the second trench isolation structure 1062 may be adjusted by changing the position of the barrier layer 1041. For example, a barrier layer 1041 is disposed in the recess 1011, forming an adjacent first trench isolation structure 1061. A barrier layer 1041 is disposed on the protrusions 1012, forming adjacent second trench isolation structures 1062.
Referring to fig. 4 to 5, in an embodiment of the invention, after forming the barrier layer 1041, the substrate 101 at the bottom of the recess 1011 and the substrate 101 at the top of the protrusion 1012 are etched simultaneously by using the barrier layer 1041 as a mask, the first trench 1051 is formed at the position of the recess 1011, the second trench 1052 is formed at the position of the protrusion 1012, and the depth of the first trench 1051 is greater than the depth of the second trench 1052.
Referring to fig. 4 to 5, in an embodiment of the present invention, in forming the first trench 1051 and the second trench 1052, the substrate 101 is etched by wet etching, and specifically, the substrate 101 may be etched by an acidic etching solution or the substrate 101 may be etched by an alkaline etching solution. The acidic etching liquid is, for example, a mixed liquid of hydrofluoric acid and nitric acid, and the alkaline solution is, for example, a potassium hydroxide solution, an ammonium hydroxide solution, a tetramethylammonium hydroxide ( TMAH) solution, or the like. In this embodiment, the substrate 101 is etched using a tetramethylammonium hydroxide solution as an etching liquid. Since wet etching of a tetramethylammonium hydroxide solution has anisotropy, a material can be preferentially etched in a specific direction. When the substrate 101 is wet etched using a tetramethylammonium hydroxide solution, the radial dimension of the first trenches 1051 gradually decreases as the depth of the first trenches 1051 increases for each first trench 1051 and the radial dimension of the second trenches 1052 gradually decreases as the depth of the second trenches 1052 increases for each second trench 1052 due to the blocking of the blocking layer 1041.
Referring to fig. 5, in an embodiment of the present invention, the first trenches 1051 and the second trenches 1052 are formed with inverted triangular cross sections. In other embodiments, the cross-sections of the first and second trenches 1051, 1052 may also be arranged in an inverted trapezoid.
Referring to fig. 6 and 7, in an embodiment of the present invention, after forming the first trench 1051 and the second trench 1052, a medium is filled in the first trench 1051 and the second trench 1052 to form the medium layer 106. The dielectric layer 106 fills the first trench 1051 and the second trench 1052. Thereafter, the dielectric layer 106 and the barrier layer 1041 above the surface of the substrate 101 are polished away by a chemical mechanical polishing (CHEMICAL MECHANICAL Polish) process, where the dielectric in the first trench 1051 forms a first trench isolation structure 1061 and the dielectric in the second trench 1052 forms a second trench isolation structure 1062.
Referring to fig. 6 and 7, in an embodiment of the present application, the medium filled in the first trench 1051 and the second trench 1052 is a high dielectric constant material, such as aluminum oxide (Al 2O3) or tantalum pentoxide (Ta 2O5). The trench isolation structure and the second trench isolation structure 1062 formed using the high dielectric constant material do not affect light absorption when applied in an image sensor. In other embodiments, when the semiconductor structure provided by the present application is applied to other devices, the medium filled in the first trench 1051 and the second trench 1052 may include silicon dioxide, silicon nitride, silicon oxynitride, and the like.
Referring to fig. 7, the semiconductor structure formed in the present invention includes a substrate 101, and a first trench isolation structure 1061 and a second trench isolation structure 1062 disposed in the substrate 101, wherein a depth of the first trench isolation structure 1061 is greater than a depth of the second trench isolation structure 1062, and a radial dimension of the first trench isolation structure 1061 is gradually reduced as a depth of the first trench isolation structure 1061 is increased for each first trench isolation structure 1061, and a radial dimension of the second trench isolation structure 1062 is gradually reduced as a depth of the second trench isolation structure 1062 is increased for each second trench isolation structure 1062.
Referring to fig. 8, in an embodiment of the present application, when the semiconductor structure formed in the present application is disposed in a backside illuminated image sensor, the image sensor includes a circuit wiring layer 201, a photodiode 202 disposed on the circuit wiring layer 201, a semiconductor structure disposed on the photodiode 202, a light filter 203 disposed on the semiconductor structure, and a microlens 204 disposed on the light filter 203. The semiconductor structure is disposed between the optical filter 203 and the photodiode 202, and a second trench isolation structure 1062 in the semiconductor structure is located on a wiring between the microlens 204 and the photodiode 202 in a growth direction of the image sensor. When light enters the micro lens 204, the light is reflected and refracted by the second trench isolation structure 1062 and the first trench isolation structure 1061, so that the spectral absorption range can be widened, and the optical efficiency can be enhanced. To further increase the reflection and refraction of light, the first and second trench isolation structures 1061 and 1062 are arranged such that, for each first trench isolation structure 1061, the radial dimension of the first trench isolation structure 1061 gradually decreases as the depth of the first trench isolation structure 1061 increases, and for each second trench isolation structure 1062, the radial dimension of the second trench isolation structure 1062 gradually decreases as the depth of the second trench isolation structure 1062 increases.
In summary, the present invention provides a method for manufacturing a semiconductor structure, a semiconductor structure and an image sensor, wherein the method for manufacturing a semiconductor structure includes providing a substrate; forming a hard mask layer on a substrate, etching the substrate, forming a plurality of concave parts on the substrate, forming convex parts on the substrate between the adjacent concave parts, depositing an oxide layer on the substrate, wherein the oxide layer covers the concave parts and the convex parts, etching partial oxide layer at the bottom of the concave parts and the oxide layer at the top of the convex parts, reserving the oxide layer on the side wall of the convex parts, forming a barrier layer on the oxide layer on the side wall of the convex parts, synchronously etching the substrate at the bottom of the concave parts and the substrate at the top of the convex parts, forming a first groove at the position of the concave parts, forming a second groove at the position of the convex parts, wherein the depth of the first groove is larger than that of the second groove, and filling media in the first groove and the second groove to form a first groove isolation structure and a second groove isolation structure. The manufacturing method of the semiconductor structure, the semiconductor structure and the image sensor have the unexpected effects that when the first groove and the second groove are formed, concave parts are formed on the substrate, convex parts are formed between the concave parts, then a blocking layer is formed on the side wall of the concave part, the blocking layer is used as a mask, the substrate at the bottom of the concave part and the substrate at the top of the convex part are etched, the first groove and the second groove with different depths are synchronously formed on the substrate, and finally, the first groove and the second groove are filled with media to form the first groove isolation structure and the second groove isolation structure with different depths. At this time, a photomask can be used to form the first trench isolation structure and the second trench isolation structure with different depths, so that one photomask is saved, and the manufacturing cost is greatly saved. When the formed semiconductor structure is arranged on the back-illuminated image sensor, the semiconductor structure is arranged between the micro lens and the photodiode, so that the photoelectric conversion efficiency is increased. Meanwhile, the radial dimension of the groove isolation structure is gradually reduced along with the increase of the depth of the groove isolation structure, so that the reflection and refraction of light are further increased, the light conversion efficiency is further improved, and the performance of the image sensor is improved.
The embodiments of the invention disclosed above are intended only to help illustrate the invention. The examples are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best understand and utilize the invention. The invention is limited only by the claims and the full scope and equivalents thereof.
Claims (10)
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| CN118099212A (en) * | 2024-02-19 | 2024-05-28 | 华虹半导体(无锡)有限公司 | LDMOS device and method for manufacturing the same |
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