CN1209800C - Method of preparing SON type field-effect transistor - Google Patents

Abstract

The invention provides a new method for preparing a SON type field effect transistor, comprising the following steps: (1) forming an active region; (2) forming a cavity layer under the active region by using helium or hydrogen-helium combined implantation and annealing; 3) Prepare the gate dielectric, gate electrode, source-drain expansion region, and sidewall; (4) Dope the source and drain by ion implantation; (5) Make the volume expansion of the source and drain regions fill the void layer under the source and drain; (6) Complete Subsequent steps until the SON device is fabricated. In the preparation method of the present invention, the technology of helium or hydrogen helium injection to form a cavity and the technology of material volume expansion are used to naturally form the structure of the SON device, and the process is simple and easy to realize circuit integration. At the same time, it can be fully compatible with conventional CMOS technology, which is convenient for transplantation to industrial production, reduces process complexity, and improves production efficiency.

Description

A kind of method for preparing the silicon field-effect transistor on the layer of cavity

Technical field:

The invention belongs to cmos vlsi manufacturing technology field, relate in particular to the preparation method of silicon (Silicon-On-Nothing the is called for short SON) field-effect transistor (MOSFET) on the layer of cavity.

Background technology:

The demand for development MOSFET device size of cmos vlsi technology constantly dwindles, and short channel effect (causing potential barrier such as leakage reduces) causes the subthreshold region leakage current of device to increase, and causes that the circuit quiescent dissipation increases, and on-off ratio reduces.

Problem at device subthreshold region leakage current increases has proposed some new construction devices and has been improved in the document.According to the prediction of ITRS2002, ultra-thin body SOI, FinFET, vertical channel device, planar double-gated devices is the alternative structure that solves short channel effect.From the compatibility and the integrated easy degree of technology, ultra-thin body SOI device is the most possible at present device architecture of realizing suitability for industrialized production.

The design feature of ultra-thin body SOI device is device preparation in the top silicon surface of sandwich structure (silicon fiml/bury oxygen/substrate), and wherein the thickness of silicon fiml is much smaller than the raceway groove width of depletion region.Such structure makes the electric charge between source drain depletion region and the raceway groove depletion region share to reduce, can effectively suppress short channel effect; The coupling of interfacial potential makes sub-threshold slope near ideal value before and after the silicon fiml.Therefore, the subthreshold region leakage current of ultra-thin body SOI device can access effective inhibition.

But the inferior position of ultra-thin body SOI device is that ON state current is very little.Because the oxygen that buries in its sandwich structure is not hot good conductor, the Joule heat that device is operated in the generation of following time of ON state current state is not easy to scatter and disappear, and causes lattice scattering to increase, and channel mobility descends, and ON state current descends.Simultaneously, the increase of lattice heat also makes the reliability of device reduce.

Therefore keep the good subthreshold value characteristic of ultra-thin body and improve between its heat dispersion existing contradiction.Document 1 (Malgorzata Jurczak, Thomas Skotnicki, M.Paoli, B.Tormen, etc., " Silicon-on-Nothing (SON)-an Innovative Process for Advanced CMOS ", IEEE Trans.Elec.Dev., pp.2179, Vol.47, No.11,2000) at this contradiction, proposed a kind of only with the so-called SON device architecture of channel region preparation on the layer of cavity, as shown in Figure 1.This structure keeps the ultra-thin raceway groove of device on the layer of cavity, and the source is leaked and is connected with substrate.Cavity layer play with ultra-thin body SOI in bury oxygen effect, therefore can keep good subthreshold value characteristic, simultaneously, leak in the source and the heat radiation that directly is connected to device of substrate provides good path.According to document 2[S.Monfray, T.Skotnicki, Y.Morand, etc., " First 80nm SON (Silicon-On-Nothing) MOSFETs with perfect morphology and high electrical performance ", IEDM, pp.645,2001] experimental study, the performance of this structure are better than body silicon and SOI device, can reach good balance between off-state current and ON state current.

At document 2[S.Monfray, T.Skotnicki, Y.Morand, etc., " First 80nm SON (Silicon-On-Nothing) MOSFETs with perfect morphology and high electrical performance ", IEDM, pp.645,2001] in, SON preparation of devices method mainly is to utilize selective epitaxial technology and lateral encroaching technology.Its preparation scheme is as follows:

1, utilize the shallow-trench isolation technology to be formed with after the source region, selective epitaxial SiGe layer and Si layer on active area;

2, finish up to the LDD injection according to the conventional cmos prepared then;

3, form Si ₃N ₄With the double-deck side wall of TEOS, Si ₃N ₄In the side wall inboard;

4, be hard mask with side wall, the downward etching source-drain area of autoregistration, and guarantee that the SiGe layer exposes the cross section;

5, utilize selectivity lateral encroaching technology that the SiGe layer is eroded, form one and be buried in the cavity layer that raceway groove adds the side wall below;

6, successively utilize RTO/HTO silicon dioxide and silicon nitride filling cavity layer then;

7, anisotropic etching silicon nitride removes the silicon nitride on the source-drain area, only keeps the silicon nitride in the cavity;

8, utilize HF that the corrosion of RTO/HTO silicon dioxide layer is clean, the source that is is leaked the expansion area and is exposed;

9, leak on the part extension in the source that utilizes the selective epitaxial technology to expose, and formation can be drawn the source-drain area of contact;

10, heavy doping forms drain contact district, source, and is later on the same with conventional cmos technology;

Because adopted epitaxy technology and selectivity sideetching technology in this technology, and these two technology and conventional CMOS processing compatibility are bad, therefore be applied to industrial integrated easy degree and production efficiency all poor.

In order to utilize the good electric property of SON device architecture, reduce process complexity simultaneously, enhance productivity, propose preparation method a kind of and that conventional cmos technology is compatible fully and have very big meaning.

Summary of the invention:

The new method that the purpose of this invention is to provide a kind of SON of preparation type field-effect transistor, this method and conventional cmos process compatible are convenient to be transplanted to the device preparation method on the industrial production.

Technical scheme of the present invention is as follows:

A kind of method for preparing SON type field-effect transistor comprises following steps:

(1) is formed with the source region;

(2) utilize helium or hydrogen helium to unite injection and below active area, form the cavity layer through annealing;

(3) expansion area, side wall are leaked in preparation gate medium, gate electrode, source;

(4) ion injects the source leakage is mixed;

(5) make the cavity layer of the side of leaking down, source-drain area volumetric expansion filling source;

(6) finish subsequent step, finish until the SON element manufacturing.

The preparation of source leakage expansion area is to utilize polysilicon solid-state diffusion method in the described a kind of method for preparing the SON device, step (3), can be referring to Chinese patent 02146376.X, and publication number is CN1416168A.

Described a kind of method for preparing the SON device; the method that step (5) adopts can be: utilize heavy dose of to source-drain area injection heavy ion; the silicon of source-drain area is destroyed; cause non-crystallization region; can be leaked down in the source cavity layer of face of the volumetric expansion that non-crystallization region causes is filled; make the silicon layer on the layer of cavity directly be connected, and the cavity below grid structure and the side wall remain because be protected, so form the SON device architecture with following silicon substrate.Described heavy ion can be As or Si.

Described a kind of method for preparing the SON device; the method that step (5) adopts can also be: in the silicide in preparation drain contact district, source; make the silicide volumetric expansion; have thorough grasp the leak down cavity of face, source; make drain contact district, source be connected with substrate; and the cavity below grid structure and the side wall remains because be protected, so form the SON device architecture.

Among the preparation method of the present invention, utilized helium or hollow cavity forming by H-He injecting technology and material volume expansion technique to come nature to form the SON device architecture, technology is easy, is easy to realize that circuit is integrated.In the method, key technology is step (2) and step (5), and promptly helium or hydrogen helium are united injection formation cavity layer technology and volumetric expansion filling technique.Other steps can adopt conventional CMOS technology to finish, thereby can be compatible fully with conventional cmos technology, are convenient to be transplanted on the industrial production, reduce process complexity, enhance productivity.

In the method for the present invention, helium or hydrogen helium are united the empty technology of injection formation and are widely used in semi-conducting material preparation technology.The present invention has carried out some experiments, proves that this technology can effectively form buried cavity layer.Also carry out the experiment of volumetric expansion simultaneously, proved the cavity layer that the decrystallized volumetric expansion that causes really can the side of leaking down, filling source.Below set forth.

1, hydrogen helium injects and forms cavity layer experiment

The silicon dioxide of heat growth one deck 2000 injects H earlier as screen on P type body silicon materials substrate ₂ ⁺, inject He then ⁺Sample is annealed in 1180 ℃ of high temperature nitrogen environment.Remove silicon dioxide layer then.The TEM photo of sample shows that can form continuous distribution under silicon layer, size is even, and periphery does not have the cavity layer of stress, as shown in Figure 2; Also carried out the device preparation on this cavity layer, electrical testing shows that injection of hydrogen helium and high-temperature annealing process do not damage for the quality of the silicon layer on the cavity, and device can keep normal electrology characteristic, even is better than conventional body silicon device, as shown in Figure 3.Electron diffraction pattern Fig. 4 shows that also hydrogen helium injects later silicon layer quality near monocrystalline.

2, heavy ion injects decrystallized formation volumetric expansion experiment

On the basis of experiment 1, photoetching forms a series of step, and step is formed by polysilicon.Be mask then with the polysilicon, heavy dose of As and Si are injected in autoregistration, are enough to make the monocrystalline silicon lattice destroyed, form non-crystallization region.TEM tests demonstration, and the zone of being sheltered by step is not subjected to decrystallized destruction, and the decrystallized migration that causes silicon atom that the zone of exposing forms makes that buried cavity layer is obviously filled, as shown in Figure 5.

The volumetric expansion of the silicide checking that do not experimentize, but at present as an extensive use mature technique, proved that silicide can cause serious volumetric expansion.This explanation, the volumetric expansion technology is feasible.

Above experiment shows that the method that the present invention proposes has the reliable technique basis, is that a kind of feasible SON device prepares scheme.

Description of drawings:

Fig. 1 is a SON device architecture schematic diagram, among the figure:

The 1-gate electrode, the 2-gate medium, the 3-channel region, the 4-side wall, the expansion area is leaked in the 5-source,

Drain contact district, 6-source, 7-cavity layer promptly is positioned at the local buried regions medium under the leakage expansion area of raceway groove and source;

The 8-substrate.

Fig. 2 forms the TEM photo in cavity for hydrogen helium injection technique.Wherein the left side is to amplify 50,000 times transmission electron microscope photo, and the right side is to amplify 80,000 times transmission electron microscope photo.

Fig. 3 injects the MOSFET electric property of preparation on the cavity layer that forms and the contrast of conventional body silicon MOSFET electric property at hydrogen helium.Wherein (a) is the transfer curve contrast, (b) is the curve of output contrast.

Fig. 4 injects the electronic diffraction photo of sample for hydrogen helium.

Phenomenon is filled in the cavity that the silicon atom migration that Fig. 5 causes for the Si ion injects causes.Wherein A is the cavity layer through the injection of Si ion, and B is the empty layer that does not inject through the Si ion, and multiplication factor is 50,000 times.

Embodiment:

According to technical scheme of the present invention, a specific embodiment is carried out on four inches silicon chip, and domain is identical, as follows with common MOSFET domain:

1. dry-oxygen oxidation 300 , LPCVD 1000 silicon nitrides

2. photoetching: active area version

3.RIE etch silicon nitride keeps at least 250 silicon dioxide

4. an injection: inject B ⁺, energy is 40keV, dosage is 5 * 10 ¹⁴/ cm ²

5. the cleaning of removing photoresist

6.LOCOS oxidation 3500

7.1: 20 HF float silicon dioxide, boil silicon nitride with phosphoric acid then

8. floating silicon dioxide to active area dewaters

9.LPCVD 2400 silicon dioxide

10. at N ₂In 840 ℃ annealing 30 minutes, make silicon dioxide compact

11. photoetching: hydrogen helium injects version, and photoresist thickness surpasses 2 μ m

12. inject H ₂ ⁺, energy is 60keV, dosage is 4 * 10 ¹⁴/ cm ²

13. inject He ⁺, energy is 40keV, dosage is 5 * 10 ¹⁶/ cm ²

The cleaning 14. remove photoresist

15.N ₂Annealed 30 minutes for 1180 ℃ in the atmosphere, form empty structure

16.RIE etching silicon dioxide, remaining 350

17. transferring threshold value injects: inject B ⁺, energy is 35keV, dosage is 5 * 10 ¹³/ cm ²

18. floating silicon dioxide to active area dewaters

19. as grid oxygen sacrifice layer, floating to active area, dry-oxygen oxidation 300 dewater

20. gate oxidation 45

21.LPCVD polysilicon 2500 inject P ⁺, energy is 60keV, dosage is 1 * 10 ¹⁵/ cm ²

22.LPCVD silicon nitride 1000 , then LPCVD silica 1 000

23. sputter 3000 Metal Cr

24. photoetching: electron beam marked version

25. wet etching Cr

The cleaning 26. remove photoresist

27. electron beam exposure, the hachure part of photoetching grid

28.RIE etching 1000 silicon dioxide skip over quarter

29. de-electromation bundle glue

30. corrosion Cr is then with big water gaging flushing

31. photoetching: the bulk part of grid

32.RIE etch silicon nitride 1000 skip over quarter

33. float silicon dioxide, by 1000

34.ICP etch polysilicon 2500 skip over quarter

The cleaning 35. remove photoresist

36.LPCVD silicon dioxide 200

37.RIE etching silicon dioxide 200

38.LPCVD polysilicon 1500

39. inject P ⁺, energy is 45keV, dosage is 3 * 10 ¹⁶/ cm ²

40.RTP:N ₂Atmosphere following 1000 ℃ of 8 seconds of short annealing

41.ICP etch polysilicon 1500 carve clean

42. boil silicon nitride

43.LPCVD silica 1 000

44.RIE etching silicon dioxide 1000 form side wall

45. inject the Si atom, energy is 70keV, dosage is 6 * 10 ¹⁵/ cm ², at source-drain area filling cavity layer

46. inject As ⁺, energy is 60keV, dosage is 2 * 10 ¹⁵/ cm ²

47.N ₂In 1000 ℃ of 10 seconds of short annealing, activator impurity

48. sputter 150 Co, 680 ℃ of 20 seconds of annealing, erode remaining Co after, again with 800 ℃ of 20 seconds of annealing

49.LPCVD silicon dioxide 6000

50. photoetching: the empty version of lead-in wire

51.RIE etching silicon dioxide 6000 use the BHF wet etching clean again, form fairlead

The cleaning 52. remove photoresist

53. sputter 50～700 Ti, 1.0～1.2 μ m AlSi

54. photoetching: metal lead wire version

55.RIE etching Ti/AlSi

The cleaning 56. remove photoresist

57. alloying: N ₂+ H ₂In 430 ℃ of down annealing 30 minutes

Promptly make the SON device.

In the said method, step 36-41 can be referring to Chinese patent application 02146376.X, and publication number is CN1416168A.

Claims (3)

1. method for preparing the silicon field-effect transistor on the cavity layer is characterized in that comprising following steps:

(1) is formed with the source region;

(2) utilize helium or hydrogen helium to unite injection and below active area, form the cavity layer through annealing;

(3) expansion area, side wall are leaked in preparation gate medium, gate electrode, source;

(4) ion injects the source leakage is mixed;

(5) utilize heavy dose of method to make the cavity layer of the side of leaking down, source-drain area volumetric expansion filling source to source-drain area injection heavy ion;

(6) finish subsequent step, the silicon device on the layer of cavity is made and is finished.

2. the method for the silicon field-effect transistor on the layer of preparation as claimed in claim 1 cavity is characterized in that the preparation that the expansion area is leaked in described source is to utilize polysilicon solid-state diffusion method.

3. the method for the silicon field-effect transistor on the layer of preparation as claimed in claim 1 cavity is characterized in that described heavy ion is As or Si.

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