CN120896819A - A signal preprocessing method, a digital front-end device, and a storage medium - Google Patents

Abstract

The invention discloses a signal preprocessing method, a digital front-end device and a storage medium, wherein the method comprises the steps of obtaining signal frequency of data to be processed, determining two adjacent frequency indexes in a preset compensation coefficient table according to the signal frequency, determining target compensation coefficients of the data to be processed based on compensation coefficients corresponding to the frequency indexes in the preset compensation coefficient table, and performing data compensation on the data to be processed based on the target compensation coefficients. The embodiment of the invention can solve the problem of fixed compensation coefficient in the existing digital front-end device, can improve the determination precision of the compensation coefficient and enhance the signal processing effect of the digital front-end.

Description

Signal preprocessing method, digital front-end device and storage medium

Technical Field

The present invention relates to the field of signal processing technologies, and in particular, to a signal preprocessing method, a digital front end module, and a storage medium.

Background

As a core module of a modern communication system, a Digital Front End (DFE) has made a significant breakthrough in terms of high-rate, low-delay and multi-band compatibility in recent years. With the evolution of 5G/6G, satellite communications and terahertz technology, DFE is gradually evolving towards full digitization, software reconfiguration and intelligence. By integrating high-performance ADC/DAC, adaptive equalization (such as DFE/FFE) and real-time signal processing algorithm, the digital front end can effectively compensate channel loss, suppress noise and support flexible multi-system signal processing.

However, there is still a technical bottleneck in the digital front end that needs to be resolved. IQ compensation and RF frequency domain response compensation are key challenges among them. At present, the DFE mostly adopts a fixed compensation coefficient, and is difficult to cause the compensation accuracy to be reduced due to dynamic channel environments such as doppler shift, temperature drift or device aging. Especially in millimeter wave and terahertz frequency bands, the nonlinearity of the channel is enhanced, and the limitation of the fixed coefficient is more prominent.

Disclosure of Invention

The invention provides a signal preprocessing method, a digital front-end device and a storage medium, which are used for solving the problem of fixed compensation coefficient in the digital front-end device, improving the determination accuracy of the compensation coefficient and enhancing the signal processing effect of the digital front-end.

According to an aspect of the present invention, there is provided a signal preprocessing method, wherein the method includes:

Acquiring signal frequency of data to be processed, and determining two adjacent frequency indexes in a preset compensation coefficient table according to the signal frequency;

Determining a target compensation coefficient of the data to be processed based on the compensation coefficient corresponding to each frequency index in the preset compensation coefficient table;

and carrying out data compensation on the data to be processed based on the target compensation coefficient.

According to another aspect of the present invention, there is provided a digital front-end device, wherein the device comprises:

A digital front-end processing unit, configured to perform any one of the methods according to the embodiments of the present invention;

the register parameter configuration unit is used for providing parameter configuration for the digital front-end processing unit;

and the state machine conversion unit is used for managing the sequential logic and behavior control of the digital front-end processing unit and the register parameter configuration unit.

According to another aspect of the present invention, there is provided a computer readable storage medium storing computer instructions for causing a processor to execute a signal preprocessing method according to any one of the embodiments of the present invention.

According to the technical scheme, the signal frequency of the data to be processed is obtained, two adjacent frequency indexes are determined in the preset compensation coefficient table according to the signal frequency, the target compensation coefficient of the data to be processed is determined according to the compensation coefficient corresponding to the frequency index in the preset compensation coefficient table, the data to be processed is compensated according to the target compensation coefficient, the granularity of the data compensation can be enhanced through the preset compensation coefficient table which is configured in a diversified mode, the precision of the data compensation in the data processing process can be improved, the target compensation coefficient is determined based on the adjacent frequency indexes, the adaptation degree of the compensation coefficient and the signal frequency of the data to be processed can be enhanced, and the data processing effect is improved.

It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the invention or to delineate the scope of the invention. Other features of the present invention will become apparent from the description that follows.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a flowchart of a signal preprocessing method according to a first embodiment of the present invention;

Fig. 2 is a flowchart of another signal preprocessing method according to the second embodiment of the present invention;

fig. 3 is a schematic structural diagram of a digital front-end processing unit according to a third embodiment of the present invention;

Fig. 4 is a schematic structural diagram of a digital front-end device according to a fourth embodiment of the present invention;

Fig. 5 is an application example diagram of a DFE unit according to a fifth embodiment of the present invention;

Fig. 6 is a schematic diagram of a DFE unit according to a fifth embodiment of the present invention;

Fig. 7 is a schematic structural diagram of a DFE processing unit according to a fifth embodiment of the present invention;

FIG. 8 is a flow chart of a data storage error calibration unit execution logic provided in accordance with a fifth embodiment of the present invention;

FIG. 9 is a flow chart of DC offset unit execution logic provided in accordance with a fifth embodiment of the present invention;

fig. 10 is a flowchart of a digital variable gain control unit execution logic provided according to a fifth embodiment of the present invention;

FIG. 11 is a flow chart of FIR2 unit execution logic provided in accordance with a fifth embodiment of the present invention;

Fig. 12 is a flowchart of a baseband frequency response compensation unit execution logic according to a fifth embodiment of the present invention;

FIG. 13 is a flow chart of IQ compensation unit execution logic according to a fifth embodiment of the present invention;

FIG. 14 is a flow chart of digital mixer cell execution logic provided in accordance with a fifth embodiment of the present invention;

Fig. 15 is a flowchart of logic executed by a rf frequency response compensation unit according to a fifth embodiment of the invention;

FIG. 16 is a flow chart of a pre-filter unit execution logic provided in accordance with a fifth embodiment of the present invention;

FIG. 17 is a flow chart of a resampling unit execution logic provided in accordance with a fifth embodiment of the invention;

FIG. 18 is a flow chart of FIR4 unit execution logic provided in accordance with a fifth embodiment of the present invention;

Fig. 19 is a flowchart of DC estimation unit execution logic provided in accordance with a fifth embodiment of the present invention.

Detailed Description

In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.

It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed or inherent to such process, method, article, or apparatus.

Example 1

Fig. 1 is a flowchart of a signal preprocessing method according to a first embodiment of the present invention, where the method may be applied to the case of coefficient compensation of data to be processed in a DFE unit, and the method may be performed by a digital front-end processing unit, where the digital front-end processing unit may be implemented in hardware and/or software, and the digital front-end processing unit may be deployed as a chip independently, or as an integrated unit of other chips. As shown in fig. 1, the method includes:

Step 110, obtaining the signal frequency of the data to be processed, and determining two adjacent frequency indexes in a preset compensation coefficient table according to the signal frequency.

The data to be processed may be data that needs to be preprocessed by the front end of the data, the data to be processed may be ADC data specifically, the data to be processed may be binary data after digital quantization, and the signal frequency may be a physical frequency of an original signal corresponding to the data to be processed. The preset compensation coefficient table may be a configuration table for performing coefficient compensation on data to be processed in the DFE preprocessing process, and corresponding compensation coefficients may be stored for a plurality of frequency indexes in the preset compensation coefficient table, and it may be understood that the compensation coefficients stored for different frequency indexes in the preset compensation coefficient table may be different, and the difference may be specifically different values of the compensation coefficients. The frequency index may be a frequency value associated with different compensation coefficients in a preset compensation coefficient table, the frequency index in the preset compensation coefficient table may be determined by a frequency processing range of the data to be processed, which is applicable to the DFE unit, and the frequency index may be determined by uniformly dividing or unevenly dividing the frequency processing range.

In the embodiment of the invention, the DFE can acquire the signal frequency of the data to be processed, and can search two frequency indexes with frequency indexes closest to the signal frequency in the preset compensation coefficient table, wherein the frequency difference between the frequency value corresponding to the two frequency indexes and the signal frequency of the data to be processed is smaller than the frequency difference between the frequency values corresponding to other frequency indexes in the compensation coefficient table and the signal frequency of the data to be processed. It will be appreciated that the predetermined compensation coefficient table may exist in the form of a look-up table.

Further, the preset compensation coefficient table may include a plurality of compensation coefficient tables for performing data compensation on the data to be processed, and the preset compensation coefficient table may include an IQ mismatch compensation coefficient table for performing IQ compensation on the data to be processed and a radio frequency response compensation coefficient table for performing radio frequency response compensation on the data to be processed.

And 120, determining a target compensation coefficient of the data to be processed based on the compensation coefficient corresponding to each frequency index in the preset compensation coefficient table.

The preset compensation coefficient table may be a lookup table configured in the DFE unit, and the preset compensation coefficient table may include a plurality of compensation coefficients, each of which may have a frequency index corresponding to each of the compensation coefficients, and each of which may be applied to data compensation of data to be processed having a frequency corresponding to the frequency index.

In the embodiment of the invention, the corresponding compensation coefficient can be searched in the preset compensation coefficient table according to the obtained frequency index, the target compensation coefficient of the data to be processed can be determined by the obtained compensation coefficient corresponding to the two frequency indexes, the determination can include taking the average value of the two compensation coefficients as the target compensation coefficient, or taking the weighted average value of the two compensation coefficients as the target compensation coefficient, or carrying out linear interpolation on the compensation coefficient based on the signal frequency of the data to be processed, and taking the linear interpolation result of the two compensation coefficients as the target compensation coefficient.

And 130, carrying out data compensation on the data to be processed based on the target compensation coefficient.

In the embodiment of the invention, the data to be processed can be subjected to data compensation through the obtained target compensation coefficient, for example, the target compensation coefficient can be used for carrying out multiplication compensation on the data to be processed, or the target compensation coefficient can also be used for carrying out addition compensation on the data to be processed.

According to the embodiment of the invention, the signal frequency of the data to be processed is obtained, two adjacent frequency indexes are determined in the preset compensation coefficient table according to the signal frequency, the target compensation coefficient of the data to be processed is determined according to the compensation coefficient corresponding to the frequency index in the preset compensation coefficient table, the data to be processed is subjected to data compensation according to the target compensation coefficient, the granularity of data compensation can be enhanced through the preset compensation coefficient table which is configured in a diversified manner, the precision of data compensation in the data processing process can be improved, the target compensation coefficient is determined based on the adjacent frequency indexes, the adaptation degree of the compensation coefficient and the signal frequency of the data to be processed can be enhanced, and the data processing effect is improved.

Example two

Fig. 2 is a flowchart of another signal preprocessing method according to a second embodiment of the present invention, where a process for determining a target compensation coefficient in a DFE unit is described in the embodiment of the present invention, referring to fig. 2, the method provided in the embodiment of the present invention specifically includes the following steps:

step 210, determining that the enable indication parameter of the data compensation is set to an enable state.

The enabling indication parameter may be information indicating whether to continue to perform data compensation on the data signal to be processed according to the target compensation coefficient, and it may be understood that when the enabling indication parameter is set to an enabling state, data compensation may be performed on the data signal to be processed according to the target compensation coefficient.

In the embodiment of the present invention, the DFE may check the enable indication parameter of whether to perform data compensation, determine whether the enable indication parameter is set to an enable state, if so, continue the subsequent data compensation step, and if not, end the current data compensation flow. Further, in some embodiments, when it is determined that the enable indication parameter is not set to the enable state, data compensation may not be performed on the data to be processed according to the method provided by the embodiment of the present invention, for example, data compensation may be performed on the data to be processed according to an existing data compensation manner, or data compensation may not be performed on the data to be processed.

Step 220, reading the initialization frequency parameter and the frequency step increment parameter of the register parameter configuration unit, and determining the signal frequency of the data to be processed according to the initialization frequency parameter and the frequency step increment parameter.

The register parameter configuration unit may be responsible for hardware parameter configuration, input/output format control, etc. in the DFE unit, where the register parameter configuration unit may store at least an initialization frequency parameter and a frequency step increment parameter, where the initialization frequency parameter may be a starting frequency value of a signal source corresponding to data to be processed in the DFE unit, the frequency step increment parameter may be a minimum interval or step length of the DFE unit for frequency adjustment of a signal of the signal source each time, and the initial frequency parameter and the frequency step increment parameter may jointly determine a frequency of the signal of the data to be processed.

Specifically, the DFE unit may access the register parameter configuration unit, may extract the initialized frequency parameter and the frequency step increment parameter from the register configuration unit, and may calculate the signal frequency of the data to be processed at the current time according to the initialized frequency parameter and the frequency step increment parameter, where the calculation process may be implemented by the following formula, for example:

f=sb_init+sb_step×t, where F represents the signal frequency, sb_init represents the initialization frequency parameter, and sb_step represents the frequency STEP increment parameter.

Step 230, determining two adjacent frequency indexes in the preset compensation coefficient table according to the signal frequency.

In the embodiment of the invention, two frequency indexes closest to the frequency value of the signal frequency in the preset compensation coefficient table can be searched.

For example, the working frequency range of the current DFE unit is 30-40GHz, the frequency indexes in the preset compensation coefficient table may be divided according to the working frequency of the current DFE unit, the frequency indexes may include 30GHz, 35GHz, 40GHz and the like, the obtained signal frequency is 32GHz, and the two nearest frequency indexes may be obtained in the preset compensation coefficient table as 30GHz and 35GHz.

Step 240, extracting a standard compensation coefficient corresponding to the frequency index in the preset compensation coefficient.

The standard compensation coefficient may be a compensation coefficient corresponding to each frequency index in the preset compensation coefficient, the standard compensation coefficient may be determined and generated for the signal frequency corresponding to the frequency index, and the standard compensation coefficient may be determined empirically or experimentally.

In the embodiment of the invention, the standard compensation coefficient corresponding to each frequency index can be searched in the preset compensation coefficient according to the determined two frequency indexes.

And 250, performing linear interpolation according to the signal frequency and the two standard compensation coefficients to obtain a target compensation coefficient.

Specifically, the linear interpolation calculation may be performed on the standard compensation coefficient according to the obtained signal frequency, the calculation result may be used as a target compensation coefficient, for example, the frequency difference of the corresponding frequency index may be determined for the two standard compensation coefficients, and the coefficient difference of the two standard compensation coefficients may be determined, the ratio between the coefficient difference and the frequency difference may be calculated, the frequency difference between the signal frequency and any one of the frequency indexes of the two standard compensation coefficients may be obtained, and the product of the frequency difference and the ratio may be used as the target compensation coefficient of the data to be processed. In some inventive embodiments, the process of calculating the target compensation coefficient by linear interpolation may be determined by the following formula:

Where y represents the target compensation coefficient, x represents the signal frequency, x1 and x0 represent the standard compensation coefficients, respectively, and y1 and y0 represent the determined frequency indices, respectively.

And 260, carrying out data compensation on the data to be processed based on the target compensation coefficient.

According to the embodiment of the invention, the enabling indication parameter of data compensation is set to be in an enabling state, the signal frequency of the data to be processed is calculated according to the initialized frequency parameter and the frequency stepping increment parameter of the register parameter configuration unit, two adjacent frequency indexes of the signal frequency in the preset compensation coefficient table are extracted, the standard compensation coefficient corresponding to each frequency index is obtained, linear interpolation is carried out according to the signal frequency and the standard compensation coefficient, the target compensation coefficient of the data to be processed is obtained, the data to be processed is compensated through the target compensation coefficient, flexible compensation coefficient configuration can be realized based on the preset compensation coefficient table, the adaptive compensation coefficient is determined according to the signal frequency of the data, the precision of the data compensation can be enhanced, and the preprocessing effect of the data is enhanced.

Furthermore, on the basis of the embodiment of the invention, the preset compensation coefficient table at least comprises an IQ mismatch compensation coefficient table and a radio frequency response compensation coefficient table, and the preset compensation coefficient table comprises at least two frequency indexes and standard compensation coefficients corresponding to the frequency indexes.

In the embodiment of the present invention, the preset compensation coefficient table at least includes an IQ mismatch compensation coefficient table and a radio frequency response compensation coefficient table, the IQ mismatch compensation coefficient table and the radio frequency response compensation coefficient table may be a lookup table, the IQ mismatch compensation coefficient table and the radio frequency response compensation coefficient may include at least two sets of standard compensation coefficients, the standard compensation coefficients are used for IQ mismatch compensation and radio frequency response compensation in the IQ mismatch compensation coefficient table and the radio frequency response compensation coefficient, respectively, and it is understood that the number of frequency indexes and the frequency index values corresponding to the standard compensation coefficients in the IQ mismatch compensation coefficient table and the radio frequency response compensation coefficient may be the same, that is, the IQ mismatch compensation coefficient table and the radio frequency response compensation coefficient may include the same number of standard compensation coefficients, and the frequency index values in the IQ mismatch compensation coefficient table and the radio frequency response compensation coefficient may be the same.

On the basis of the embodiment of the invention, the method further comprises the steps of obtaining the data to be processed and carrying out error correction on the data to be processed, wherein the error correction at least comprises at least one of high-low bit storage position correction, signal storage form correction and positive and negative storage position correction.

In the embodiment of the invention, when the DFE unit acquires the data to be processed, the DFE unit may perform error correction on the acquired data to be processed due to the abnormality of the data to be processed caused by the reasons of hardware wiring errors or software configuration errors and the like. Specifically, the DFE unit can detect whether the high-low storage of the data to be processed is wrong, if so, the high-low storage position of the data to be processed can be corrected to enable the high-low storage position of the data to be processed to be reversed, and if so, the DFE unit can also detect whether the positive-negative storage of the data to be processed is wrong, and if so, the DFE unit can also detect whether the real-imaginary storage of the data to be processed is wrong, and if so, the positive-negative storage position of the data to be processed is corrected to enable the real-imaginary storage of the data to be processed to be reversed.

Further, on the basis of the embodiment of the invention, the method further comprises the following steps:

and calling an equiripple filter to downsample the data to be processed according to a preset downsampling multiple.

The equiripple filter can be designed according to the maximum error minimization criterion, can be also called as a Chebyshev approximation filter, can be realized by relying on the Parks-McClellan algorithm, can realize optimal equiripple control and has the advantage of phase linearity in a passband.

In the embodiment of the invention, the data to be processed can be downsampled through the equiripple filter, and the preset downsampling multiple of the downsampling can be configured in the DFE unit in advance. For example, an equiripple filter may be invoked to downsample the data to be processed by a factor of 2.

Further, on the basis of the embodiment of the invention, the method further comprises the steps of determining a resampling interval according to the initial reference parameters and the adjustment step length parameters configured by the register parameter configuration unit, searching the corresponding fractional delay filter coefficients in the fractional delay filter coefficient table according to the resampling interval, and resampling the data to be processed according to the fractional delay filter coefficients.

In the embodiment of the invention, the DFE unit may extract the initial reference parameter and the adjustment step parameter in the register parameter configuration unit, determine the current resampling interval of the data to be processed according to the initial reference parameter and the adjustment step parameter, search the corresponding fractional delay filter coefficient in the preset fractional delay filter coefficient table according to the resampling interval, and resample the data to be processed according to the found fractional delay filter coefficient. Further, the fractional delay filter coefficient table may further include a plurality of groups of fractional delay filter coefficients, each group of fractional delay filter coefficients may correspond to a different resampling interval, adjacent target intervals may be searched in the fractional delay filter coefficient table through the resampling interval of the data to be processed, the fractional delay filter coefficients associated with the target intervals may be linearly interpolated, and the target fractional delay filter coefficients corresponding to the linear interpolation result may be resampled to the data to be processed.

Example III

Fig. 3 is a schematic structural diagram of another digital front-end processing unit according to the third embodiment of the present invention, referring to fig. 3, the digital front-end processing unit may include:

and the coefficient table unit 310 is configured to obtain a signal frequency of the data to be processed, and determine two adjacent frequency indexes in the preset compensation coefficient table according to the signal frequency.

And a coefficient determining unit 320, configured to determine a target compensation coefficient of the data to be processed based on the compensation coefficient corresponding to each frequency index in the preset compensation coefficient table.

And the compensation execution unit 330 is configured to perform data compensation on the data to be processed based on the target compensation coefficient.

Based on the above embodiment of the present invention, the coefficient determining unit 320 is specifically configured to extract a standard compensation coefficient corresponding to a frequency index in a preset compensation coefficient, and perform linear interpolation according to a signal frequency and two standard compensation coefficients to obtain a target compensation coefficient.

On the basis of the embodiment of the invention, the preset compensation coefficient table in the coefficient determining unit 320 at least comprises an IQ mismatch compensation coefficient table and a radio frequency response compensation coefficient table, and the preset compensation coefficient table comprises at least two frequency indexes and standard compensation coefficients corresponding to the frequency indexes.

On the basis of the embodiment of the invention, the digital front-end processing unit further comprises a data correction unit, a data processing unit and a data processing unit, wherein the data correction unit is used for acquiring data to be processed and performing error correction on the data to be processed, and the error correction at least comprises at least one of high-low storage position correction, signal storage form correction and positive and negative storage position correction.

On the basis of the embodiment of the invention, the digital front-end processing unit further comprises an enabling indication unit, which is used for determining that the enabling indication parameter of the data compensation is set to be in an enabling state.

On the basis of the embodiment of the invention, the digital front-end processing unit further comprises a downsampling unit, which is used for calling the equal ripple filter to downsample the data to be processed according to the preset downsampling multiple.

On the basis of the embodiment of the invention, the digital front-end processing unit acquires the signal frequency of the data to be processed, and the method comprises the steps of reading the initialization frequency parameter and the frequency stepping increment parameter of the register parameter configuration unit, and determining the signal frequency of the data to be processed according to the initialization frequency parameter and the frequency stepping increment parameter.

On the basis of the embodiment of the invention, the digital front-end processing unit further comprises a resampling unit, a fractional delay filter coefficient corresponding to the fractional delay filter coefficient table is searched according to the resampling interval, and the data to be processed is resampled according to the fractional delay filter coefficient.

The digital front-end processing unit provided by the embodiment of the invention can execute the signal preprocessing method provided by any embodiment of the invention, and has the corresponding functional modules and beneficial effects of the execution method.

Example IV

Fig. 4 is a schematic structural diagram of a digital front-end device according to a fourth embodiment of the present invention, referring to fig. 4, the digital front-end device may include:

The digital front-end processing unit 410 is configured to execute the signal preprocessing method according to any one of the embodiments of the present invention, where the method includes obtaining a signal frequency of data to be processed, determining two adjacent frequency indexes in a preset compensation coefficient table according to the signal frequency, determining a target compensation coefficient of the data to be processed based on compensation coefficients corresponding to the frequency indexes in the preset compensation coefficient table, and performing data compensation on the data to be processed based on the target compensation coefficient.

A register parameter configuration unit 420, configured to provide parameter configuration for the digital front-end processing unit.

The state machine conversion unit 430 is configured to manage sequential logic and behavior control of the digital front-end processing unit and the register parameter configuration unit.

The digital front-end device provided by the embodiment of the invention can execute the signal preprocessing method provided by any embodiment of the invention, and has the corresponding functional modules and beneficial effects of the execution method.

Example five

Fig. 5 is a diagram of an application example of a DFE unit according to an embodiment of the present invention, where the DFE unit is used as a key bridge for connecting analog signals and digital processing, and is widely used in fields requiring high-speed and high-precision signal processing, such as a wireless communication system, a radar and sensing system, high-speed data interconnection, medical and industrial equipment, consumer electronics, etc., referring to fig. 5, taking an application example in a millimeter wave radar system as an example, a radar echo signal is received by a receiving end (RX) and then first needs to pass through an amplifier (Low Noise Amplifier, LNA), the amplifier is generally a nonlinear device, the amplitude and phase frequency response of the amplifier are different from that of an ideal model, and meanwhile, the echo signals of different RX may be inconsistent due to hardware errors, space position errors, propagation errors and other reasons, so that the echo signals of different RX are inconsistent in frequency response after passing through the LNA, and the DFE module performs radio frequency response compensation to ensure that the radio frequency responses of signals of different RX are consistent.

After passing through the LNA, the echo signal needs to be mixed with a Local Oscillator (LO) signal to be down-converted to an intermediate frequency signal, the intermediate frequency signal and a high frequency signal can be generated after normal mixing, the high frequency signal can be filtered by a low-pass filter at an intermediate frequency processing end, the LO signal can leak into the radar echo signal due to limited isolation of a hardware circuit and the like, the normal echo signal and the LO signal are mixed, the self mixing of the LO signal can be caused, a Direct Current (DC) signal can be generated during the self mixing of the LO signal, the dynamic range of the intermediate frequency signal is reduced, and a DFE module is required to perform DC estimation and DC bias compensation.

The echo signals are mixed and then pass through a low-pass filter to obtain intermediate frequency signals, and then IQ quadrature sampling is carried out on the intermediate frequency signals to obtain ADC signals. Because of the non-ideal characteristics of the IQ quadrature sampling analog device, the IQ sampled signal has mismatch in amplitude and phase, and the mismatch can cause image frequency in the frequency spectrum of the ADC data, and the DFE module is required to perform IQ mismatch compensation.

When the echo signal is sampled, the sampling bandwidth is far larger than the actual bandwidth of the signal due to the requirement of adapting to the very flexible sampling rate and the condition that the sampling rate is set too high, more redundant information exists in the ADC data, and a lot of memories are occupied by invalid data during post-processing, so that the DFE module is required to resample and downsample.

After the echo signal is sampled and changed into ADC data, the amplitude of the ADC data is changed greatly because the radar echo data power is related to the distance and the scattering characteristic of the target, so that the ADC data is saturated when the amplitude is high, and the ADC data is lost when the amplitude is low. The DFE module is required to perform digital gain control to achieve a higher dynamic range for the ADC data.

After the echo signal is sampled to become ADC data, the ADC data frequency of different RX may be inconsistent due to hardware error and other reasons, and further frequency spectrum shifting may be performed on the ADC data, so that the DFE module is required to perform digital mixing to perform frequency offset compensation to make the ADC data frequency of different RX consistent and perform frequency spectrum shifting on the ADC data.

Because there may be a length difference in the hardware wires of the RX channels, the delay inconsistency of the ADC data of different RX results in the baseband frequency response inconsistency, and the DFE module is required to perform baseband frequency response compensation to ensure that the baseband frequency response of the ADC data of different RX is consistent.

When the ADC data is transmitted to the DFE module, storage errors such as high-low position inversion, sign inversion, real-imaginary part inversion and offset binary representation binary complement are generated after the ADC data is transmitted to the DFE module due to hardware wiring errors or software configuration errors and the like, and the DFE module is required to calibrate the ADC data storage errors.

Referring to fig. 6, the DFE unit provided in the embodiment of the present invention includes 5 units, which are an input format unit (Input Formatter), a DFE processing unit (DFE Process), an output format unit (Output Formatter), a register parameter configuration unit (Common REGISTER PARAMETER SET), and a state machine conversion unit (FINITE STATE MACHINE), wherein the state machine conversion unit is responsible for the overall operation of the DFE unit, and the overall operation includes start-up, loop, stop, and register parameter configuration. The register parameter configuration unit is responsible for carrying out corresponding parameter configuration on the input formatting unit, the DFE processing unit and the output formatting unit. The input formatting unit is responsible for reading data from the local memory in a configured format and sending the data to the DFE processing unit. The DFE processing unit is responsible for performing the relevant DFE operations on the input data. The output formatting unit is responsible for receiving the data of the DFE processing unit and writing the data into the local memory according to the configured format.

Referring to fig. 7, the dfe processing unit may include 19 units including a data storage error calibration unit (ADC Board Error Correction), a DC Compensation unit (DC Compensation), a Digital Variable gain control unit (Digital Variable GAIN AMPLIFIER, DVGA), a downsampling unit, a baseband frequency response Compensation unit (Baseband Frequency Response Compensation), an IQ Compensation unit (Inphase Quadrature Compensation), a Digital mixing unit (Digital Mixer), a radio frequency response Compensation unit (RF Frequency Response Compensation), a pre-filtering unit (RESAMPLER PREFILTER), a resampling unit (RESAMPLER), and the like. The data storage error calibration unit is responsible for calibrating storage errors occurring after ADC data are transmitted to the DFE module. The DC compensation unit is responsible for subtracting the DC estimated value from the ADC data to complete compensation. The digital variable gain control unit is responsible for digital gain control of the ADC data. The FIR 2 unit is a2 times downsampling unit and is responsible for carrying out anti-aliasing filtering and base 2 extraction on ADC data, and ABCDEF represents the serial number of each downsampling unit. The baseband frequency response compensation unit is responsible for performing baseband frequency response compensation on the ADC data. IQ Compensation is responsible for compensating for the amplitude and phase mismatch of the ADC data for IQ Compensation. And the digital mixing unit is responsible for carrying out frequency offset compensation and frequency spectrum shifting on the ADC data, and ABC represents the serial numbers of the digital mixing units. And the radio frequency response compensation unit is responsible for carrying out radio frequency response compensation on the ADC data. RESAMPLER PREFILTER a resampling pre-filter unit is responsible for anti-aliasing filtering of the ADC data. The RESAMPLER unit is a resampling unit and is responsible for resampling the ADC data. FIR 4 is a 4-fold downsampled unit responsible for anti-aliasing filtering and radix 4 decimation of the ADC data. DC Estimation is a direct current Estimation unit responsible for DC Estimation of ADC data.

Referring to fig. 8,ADC Board Error Correction, the unit receives input parameters and input data, and performs corresponding calibration logic based on BYPASS variables, adc_bit_reverse (high-low memory ERROR) variables, adc_ob22COMP (offset binary form memory) variables, adc_diff_error (positive-negative memory ERROR) variables, and adc_iq_swap (real-imaginary memory ERROR) variables in the input variables. If BYPASS is 1, the entire calibration logic is not executed, and if BYPASS is 0, the calibration logic is executed. If ADC_BIT_REVERSE is 1, the high and low BITs of ADC data are reversely calibrated, and if the ADC_BIT_REVERSE is 0, the high and low BITs are not calibrated. If ADC_OB22COMP is 1, which represents that the ADC data is stored in an offset binary form, the offset binary conversion is performed by performing offset binary to binary complement, and the offset binary conversion is not performed by being 0. If ADC_DIFF_ERROR is 1, the positive and negative bits are reversely calibrated, and the positive and negative bits are not calibrated when the ADC_DIFF_ERROR is 0. If ADC_IQ_SWAP is 1, the real and imaginary parts of the ADC data are in error, the real and imaginary parts are reversely calibrated, and the real and imaginary parts are not in error calibration when 0.

Referring to fig. 9,DC Compensation, the unit receives the input parameters and input data, performs DC compensation logic according to the input variable BYPASS, and the input variable DC estimate is used for DC compensation. If BYPASS is 1, no compensation logic is performed, and the DC estimate is subtracted from the ADC data by 0.

Referring to fig. 10, the dvga unit receives input parameters and input data, performs GAIN control logic according to an input variable BYPASS, and the input variable GAIN is a GAIN coefficient. If BYPASS is 1, GAIN control is not performed, and the GAIN factor GAIN is multiplied by the ADC data by 0.

Referring to fig. 11, the fir 2 unit receives the input parameters and the input data, and performs 2-fold down-sampling logic according to the input variable BYPASS. If BYPASS is 1, 2-fold down-sampling is not performed, anti-aliasing filtering and base 2 decimation are performed on the ADC data for 0.

Referring to fig. 12,Baseband Frequency Response Compensation, a unit receives input parameters and input data, performs baseband frequency response compensation logic according to an input variable BYPASS, and the input variable b_coef is a frequency response compensation filter coefficient calculated according to each Rx baseband frequency response error. If BYPASS is 1, baseband frequency response compensation is not performed, and if BYPASS is 0, baseband frequency response compensation filtering is performed on ADC data.

Referring to fig. 13,IQ Compensation, the unit receives input parameters and input data, performs IQ compensation logic according to an input variable BYPASS, the input variables sb_init and sb_step are used for calculating the frequency of the input data, the input variable GPE is a LUT table storing IQ compensation coefficients calculated by reference signals of different frequencies, if BYPASS is 1, IQ calibration is not performed, the input data frequency is obtained according to sb_init and sb_step, the frequency is found in the GPE corresponding to a frequency index section, and the IQ compensation coefficient matrix of the input signal is obtained by linear interpolation for compensation.

Referring to fig. 14, the digital mixer unit receives input parameters and input data, performs digital mixing logic according to an input variable BYPASS, and inputs variables ph_init and ph_step for calculating initial phases and frequencies of mixing. If BYPASS is 1, digital mixing is not performed, and if BYPASS is 0, the real part and the imaginary part of the mixed signal are obtained through the LUT lookup table, so that digital mixing is completed.

Referring to fig. 15,RF Frequency Response Compensation, a unit receives input parameters and input data, performs rf frequency response compensation logic according to an input variable BYPASS, and input variables sb_init and sb_step are used to calculate the frequency of the input data, and input variable buf_alpha is a LUT table storing rf frequency response compensation coefficients calculated by reference signals of different frequencies. If BYPASS is 1 and does not carry out radio frequency response compensation, obtaining input data frequency according to SB_INIT and SB_STEP, finding out the frequency corresponding to the frequency index interval in BUF_ALPHA, obtaining the input data radio frequency response compensation coefficient through linear interpolation for compensation.

Referring to fig. 16,Resample Prefilter, a unit receives input parameters and input data, and performs resampling pre-filtering logic according to the input variable BYPASS. If BYPASS is 1, no resampling pre-filtering is performed, anti-aliasing filtering is performed on the ADC data for 0.

Referring to fig. 17, the resampling unit receives input parameters and input data, performs resampling according to an input variable BYPASS, and inputs variables ph_init and ph_step are used to calculate a resampling interval. If BYPASS is 1 and resampling is not performed, 0 is obtained according to PH_INIT and PH_STEP, a corresponding delay index interval of the interval in a fractional delay filter LUT table is found, a fractional delay filter coefficient of an input signal is obtained through linear interpolation, and fractional interpolation is performed to complete resampling.

Referring to fig. 18, the fir 4 unit receives the input parameters and the input data, and performs 4-fold down-sampling logic according to the input variable BYPASS. If BYPASS is 1, 4 times down-sampling is not performed, anti-aliasing filtering and radix-4 decimation are performed on the ADC data for 0.

Referring to fig. 19, the DC estimation unit receives the input parameters and the input data, executes DC estimation logic according to the input variable BYPASS, and obtains a DC estimation value for 0 pairs of the ADC data accumulated value average value if BYPASS is 1 and DC estimation is not performed.

The embodiment of the application corrects high-low bit errors, offset binary storage, positive and negative bit errors and real and imaginary part errors caused by hardware or software problems in data transmission through the data storage error calibration unit, compensates an IQ compensation coefficient matrix calculated according to reference signals on all input signals through the IQ compensation unit, and has differences in IQ compensation coefficients of signals with different frequencies. The scheme of the application divides the whole working frequency band into a plurality of sub-bands, each sub-band corresponds to a frequency index, carries out amplitude and phase mismatch estimation on reference signals of all sub-bands, obtains a compensation coefficient matrix and stores the compensation coefficient matrix into an LUT table according to the frequency index. The method comprises the steps of obtaining an IQ compensation coefficient matrix of an input signal by linear interpolation in a frequency index interval of a LUT Table, designing an FIR filter according to an optimal equal ripple criterion aiming at the problems that a CIC filter used in the prior downsampling has non-ideal frequency response, has large passband amplitude ripple and nonlinear phase-frequency response, finding an optimal solution according to a Parks-Mcllan algorithm, obtaining the frequency response of the filter to have the advantages of passband ripple stability and intra-passband phase linearity, realizing fractional interpolation by an anti-aliasing filter and a fractional delay filter, dividing the filter into a plurality of sub-bands according to a certain fractional delay interval, calculating the fractional delay filter coefficient of all the sub-bands according to a fractional delay interval index, storing the fractional delay filter coefficient into a lookup Table (Look-Up Table, LUT), and resampling the fractional delay filter coefficient of the input signal by linear interpolation.

In some embodiments, the signal preprocessing method may be implemented as a computer program tangibly embodied on a computer readable storage medium, such as a memory, register, or cache storage, etc. In some embodiments, part or all of the computer program may be loaded and/or installed into the DFE unit or DFE apparatus. One or more steps of the signal preprocessing method described above may be performed when a computer program is loaded into a DFE unit or DFE apparatus for execution. Alternatively, in other embodiments, the DFE unit or DFE apparatus may be configured to perform the signal preprocessing method by any other suitable means (e.g., by means of firmware).

Various implementations of the systems and techniques described here above may be implemented in digital electronic circuitry, integrated circuit systems, field Programmable Gate Arrays (FPGAs), application Specific Integrated Circuits (ASICs), application Specific Standard Products (ASSPs), systems On Chip (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include being implemented in one or more computer programs that are executable and/or interpretable on a programmable system including at least one programmable processor, which may be a special or general purpose programmable processor, operable to receive data and instructions from, and to transmit data and instructions to, a storage system, at least one input device, and at least one output device.

A computer program for carrying out methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the computer programs, when executed by the DFE unit or DFE apparatus, cause the functions/operations specified in the flowchart and/or block diagram to be implemented. The computer program may execute entirely on the machine, partly on the machine, as a stand-alone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or server.

In the context of the present invention, a computer-readable storage medium may be a tangible medium that can contain, or store a computer program for use by or in connection with an instruction execution system, apparatus, or device. The computer readable storage medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. Alternatively, the computer readable storage medium may be a machine readable signal medium. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

To provide for interaction with a user, the systems and techniques described here can be implemented on an electronic device having a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user and a keyboard and a pointing device (e.g., a mouse or a trackball) by which the user can provide input to the electronic device. Other kinds of devices may also be used to provide for interaction with a user, for example, feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback), and input from the user may be received in any form, including acoustic input, speech input, or tactile input.

The systems and techniques described here can be implemented in a computing system that includes a background component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such background, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a Local Area Network (LAN), a Wide Area Network (WAN), a blockchain network, and the Internet.

The computing system may include clients and servers. The client and server are typically remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server can be a cloud server, also called a cloud computing server or a cloud host, and is a host product in a cloud computing service system, so that the defects of high management difficulty and weak service expansibility in the traditional physical hosts and VPS service are overcome.

It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps described in the present invention may be performed in parallel, sequentially, or in a different order, so long as the desired results of the technical solution of the present invention are achieved, and the present invention is not limited herein.

The above embodiments do not limit the scope of the present invention. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of the present invention.

Claims (10)

1. A method of signal preprocessing, the method comprising:

Acquiring signal frequency of data to be processed, and determining two adjacent frequency indexes in a preset compensation coefficient table according to the signal frequency;

Determining a target compensation coefficient of the data to be processed based on the compensation coefficient corresponding to each frequency index in the preset compensation coefficient table;

and carrying out data compensation on the data to be processed based on the target compensation coefficient.

2. The method according to claim 1, wherein the determining the target compensation coefficient of the data to be processed based on the compensation coefficient corresponding to each frequency index in the preset compensation coefficient table includes:

extracting standard compensation coefficients corresponding to the frequency indexes in the preset compensation coefficients;

and performing linear interpolation according to the signal frequency and the two standard compensation coefficients to obtain the target compensation coefficient.

3. The method of claim 1 or 2, wherein the predetermined compensation coefficient table at least comprises an IQ mismatch compensation coefficient table and a radio frequency response compensation coefficient table, and the predetermined compensation coefficient table comprises at least two frequency indexes and standard compensation coefficients corresponding to the frequency indexes.

4. The method as recited in claim 1, further comprising:

And acquiring the data to be processed, and performing error correction on the data to be processed, wherein the error correction at least comprises at least one of high-low storage position correction, signal storage form correction and positive and negative storage position correction.

5. The method of claim 1, wherein prior to data compensating the data to be processed based on the target compensation coefficient, further comprising:

and determining that an enabling indication parameter of the data compensation is set to an enabling state.

6. The method as recited in claim 1, further comprising:

and calling an equiripple filter to carry out downsampling on the data to be processed according to a preset downsampling multiple.

7. The method of claim 1, wherein the acquiring the signal frequency of the data to be processed comprises:

Reading an initialization frequency parameter and a frequency stepping increment parameter of a register parameter configuration unit;

And determining the signal frequency of the data to be processed according to the initialization frequency parameter and the frequency stepping increment parameter.

8. The method as recited in claim 1, further comprising:

determining a resampling interval according to the initial reference parameter and the adjustment step size parameter configured by the register parameter configuration unit;

Searching corresponding fractional delay filter coefficients in a fractional delay filter coefficient table according to the resampling interval, and resampling the data to be processed according to the fractional delay filter coefficients.

9. A digital front end device, the device comprising:

A digital front-end processing unit for performing the method of any of claims 1-8;

the register parameter configuration unit is used for providing parameter configuration for the digital front-end processing unit;

and the state machine conversion unit is used for managing the sequential logic and behavior control of the digital front-end processing unit and the register parameter configuration unit.

10. A computer readable storage medium, characterized in that the computer readable storage medium stores computer instructions for causing a processor to implement the signal preprocessing method according to any one of claims 1-8 when executed.