CN120832858A

CN120832858A - Chip post-simulation verification acceleration method, system, device and storage medium

Info

Publication number: CN120832858A
Application number: CN202510893872.3A
Authority: CN
Inventors: 侯坤; 秦刚
Original assignee: Shandong Inspur Science Research Institute Co Ltd
Current assignee: Shandong Inspur Science Research Institute Co Ltd
Priority date: 2025-06-30
Filing date: 2025-06-30
Publication date: 2025-10-24

Abstract

The application relates to the technical field of chip development and discloses a method, a system, equipment and a storage medium for accelerating simulation verification after a chip, wherein the method comprises the steps of collecting multidimensional data of a large-scale chip; collecting all module names of a given chip, establishing a mapping relation between a redundant module RTL and a corresponding gate-level netlist, ensuring complete consistency of interfaces before and after replacement, designing an automatic script recognition and processing parameterization module, setting up a post-simulation verification environment, verifying consistency of output responses before and after replacement, analyzing time delay changes of a critical path, calculating dynamic power consumption and static power consumption of each functional module before and after replacement, and generating a simulation verification result. According to the method, the mixed simulation model is built, part of gate-level netlist irrelevant to the current simulation function is replaced by RTL, so that the actual simulation scale of the chip is reduced, the problem of overlong simulation time after a large-scale integrated circuit is obviously shortened, and the simulation efficiency is effectively improved.

Description

Method, system, equipment and storage medium for accelerating simulation verification after chip

Technical Field

The application relates to the technical field of chip development, in particular to a method, a system, equipment and a storage medium for accelerating simulation verification after a chip.

Background

As integrated circuit technology continues to evolve, the scale and design complexity of chips dramatically increases, resulting in longer and longer times spent on chip design. In the design flow of large-scale integrated circuits, simulation and verification are important links, and can be divided into front simulation and back simulation. The pre-simulation is the simulation aiming at RTL, the aim is to analyze the correctness of the logic relationship of the circuit, and the simulation speed is high. The post simulation is a simulation of a gate-level netlist, is a simulation taking the connection condition between a circuit and a delay unit into consideration, and the simulation result directly influences the accuracy of power consumption evaluation and voltage drop analysis and the like.

Traditional post-simulation is to place the entire gate-level netlist into an EDA environment for simulation. And reading in a standard delay format file during simulation, and judging whether the post simulation is correct or not by applying excitation and monitoring the output and internal signals of the netlist. Although this approach can handle small and medium scale circuits well, the gate-level netlist of a large scale chip contains a huge number of logic gates, complex interconnect structures, and delay parameters of the logic gates, resulting in extremely lengthy simulation times.

Therefore, in the existing post-chip simulation verification method, the problem of low post-simulation verification efficiency exists.

It should be noted that the information disclosed in the foregoing background section is only for enhancement of understanding of the background of the application.

Disclosure of Invention

The following presents a simplified summary in order to provide a basic understanding of some aspects of the disclosed embodiments. This summary is not an extensive overview, and is intended to neither identify key/critical elements nor delineate the scope of such embodiments, but is intended as a prelude to the more detailed description that follows.

The method, the system, the equipment and the storage medium for accelerating the post-chip simulation verification provided by the embodiment of the disclosure solve the problem of low verification efficiency in the existing post-chip simulation verification method.

The method for accelerating the simulation verification after the chip in the embodiment of the disclosure comprises the following steps:

Collecting multidimensional data of a large-scale chip;

Collecting all module names of a given chip, and confirming that the names of a control channel and a data channel which are irrelevant to a verification function are defined as redundant modules RTL through pre-simulation analysis and function specification;

establishing a mapping relation between a redundancy module RTL and a corresponding gate-level netlist, ensuring that interfaces before and after replacement are completely consistent, and designing an automatic script recognition and processing parameterization module;

constructing a post-simulation verification environment, loading a gate-level netlist and RTL as a simulation file list, importing an SDF file, extracting a test case from the prior simulation environment, and running simulation;

and verifying consistency of output responses before and after replacement, analyzing time delay change of a critical path, calculating dynamic power consumption and static power consumption of each functional module before and after replacement, and generating simulation verification results.

In some embodiments, collecting multidimensional data for a large-scale chip includes:

extracting a complete RTL code from a code warehouse of a chip design project;

Processing the sorted RTL codes by using a chip design tool to generate a corresponding gate-level netlist, and operating a synthesis command after setting a target process library and synthesis constraint conditions by using a Synopsys Design Compiler tool to obtain a gate-level netlist file stored in a standard format;

Storing an SDF file and a corresponding gate-level netlist file in an associated mode, wherein the SDF file records delay information of each logic gate in the gate-level netlist under different working conditions;

and collecting and arranging a test case set used in a pre-chip simulation stage, classifying and arranging the test cases, and marking the test cases related to different functional modules.

In some embodiments, collecting all module names of a given chip, confirming that names of control paths and data paths irrelevant to verification functions are defined as redundant modules RTL through the previous simulation analysis and the function specification includes:

Defining a core function module set related to a current verification function according to a function specification of a chip, identifying control signals and data flows participating in a core path by analyzing a pre-simulation waveform, marking modules irrelevant to the core path, traversing all module names by combining a pre-simulation result, further analyzing control paths and data paths of the modules which are not included in the core function module set, and marking the corresponding modules as candidate redundant modules if the control signals of the modules do not participate in the control logic of the current verification function and the data paths of the modules do not provide effective data for the current verification function;

And using redundancy module labeling data in the historical chip design project as a training set, selecting functional description keywords of the modules, connection relations with the core modules and signal interaction frequency characteristics, training a support vector machine or a random forest classification model to predict candidate redundancy modules, and outputting a final redundancy module RTL list.

In some embodiments, the establishing a mapping relation between the redundancy module RTL and the corresponding gate level netlist ensures that the interfaces before and after replacement are completely consistent, and designing an automated script recognition and processing parameterization module includes:

developing an automation script based on rule matching by using a Python language, establishing a mapping relation between port number, names, bit widths and direction attributes of an RTL module and a gate-level netlist module by comparing, and associating the modules with different names and the same functions by establishing a mapping table;

Aiming at a parameterized module, an automation script adopts a regular expression matching module to instantiate a parameter transfer part in a sentence, extracts and records parameter values, adjusts the parameter values of corresponding modules in RTL codes according to the instantiation condition of the parameterized module in a gate-level netlist in the replacement process, avoids layering and naming conflict problems caused by inconsistent parameters, checks the nesting calling condition of the parameterized module, and recursively processes each level of parameter transfer so as to ensure the accuracy of the whole replacement process;

and extracting critical path delay data according to the SDF file, and inserting a corresponding delay unit at an interface of the RTL and the gate-level netlist.

In some embodiments, extracting critical path delay data according to the SDF file, inserting corresponding delay units at the RTL and gate-level netlist interface, includes:

analyzing delay information of redundant module interface signals in the SDF file, and calculating delay time to be compensated;

Selecting a proper delay unit type according to the delay time, and instantiating at an interface;

The time sequence adapter carries out time sequence constraint on the inserted delay unit, and ensures time sequence matching between the RTL and the gate-level netlist by setting time offset, establishing time and maintaining time constraint conditions.

In some embodiments, the post-construction simulation verification environment loads a gate-level netlist and RTL as a simulation file list and imports an SDF file, extracts test cases from a previous simulation environment and runs a simulation, including:

Creating project engineering based on a verification platform of pre-simulation, and configuring simulation environment parameters including simulator type, simulation time precision and memory allocation;

Automatically importing a gate-level netlist and RTL codes as a simulation file list through scripts, and importing SDF files into a simulation environment to ensure that a simulator can read delay information of the gate-level netlist;

Extracting test cases from a previous simulation environment, for the test cases written based on RTL codes, modifying excitation signals and monitoring signals in the test cases according to port names and signal definitions of a gate-level netlist, expanding the test cases, and increasing monitoring on interface signals of the RTL and the gate-level netlist;

And starting a simulation task through a script by utilizing a command line interface of the simulation platform, setting break points and monitoring points in the simulation process, monitoring the simulation state and the change of key signals in real time, and recording a simulation output result into a log file so as to analyze a subsequent result comparison module.

In some embodiments, verifying the consistency of the output responses before and after replacement, analyzing the time delay variation of the critical path, and calculating the dynamic power consumption and the static power consumption of each functional module before and after replacement includes:

the comparison program automatically reads the simulation output files before and after replacement, and verifies the consistency of output response by adopting a mode of combining character string matching and numerical calculation;

analyzing the time delay change of the critical path by combining the critical path delay information recorded in the SDF file and the time sequence data in the simulation result;

and calling a power consumption analysis tool, respectively carrying out dynamic power consumption analysis on simulation results before and after replacement, obtaining dynamic power consumption data of a target functional module, calculating a power consumption difference value, carrying out statistical analysis, and evaluating the influence of gate-level netlist replacement on chip power consumption by comparing power consumption ratio changes of different modules.

The post-chip simulation verification acceleration system in the embodiment of the disclosure comprises:

the multidimensional data collection module is used for collecting multidimensional data of the large-scale chip;

the redundant module determining module is used for collecting all module names of a given chip, and determining the names of a control channel and a data channel which are irrelevant to a verification function as redundant module RTL through front simulation analysis and a function specification;

The gate-level netlist replacing module is used for establishing a mapping relation between the redundancy module RTL and the corresponding gate-level netlist, ensuring that interfaces before and after replacement are completely consistent, and designing an automatic script recognition and processing parameterization module;

the post simulation verification module is used for building a post simulation verification environment, loading a gate-level netlist and RTL as a simulation file list, importing an SDF file, extracting a test case from the prior simulation environment and running simulation;

The result comparison module is used for verifying consistency of output responses before and after replacement, analyzing time delay change of a key path, calculating dynamic power consumption and static power consumption of each functional module before and after replacement, and generating simulation verification results.

An electronic device provided by an embodiment of the present disclosure includes at least one processor;

and a memory communicatively coupled to the at least one processor;

the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the post-chip emulation verification acceleration method described above.

The storage medium provided by the embodiment of the disclosure stores program instructions, and the program instructions execute the post-chip simulation verification acceleration method when running.

The method, the system, the equipment and the storage medium for accelerating the simulation verification after the chip provided by the embodiment of the disclosure can realize the following technical effects:

According to the method, the mixed simulation model is built, part of gate-level netlist irrelevant to the current simulation function is replaced by RTL, so that the actual simulation scale of the chip is reduced, the problem of overlong simulation time after a large-scale integrated circuit is obviously shortened, and the simulation efficiency is effectively improved. By replacing the gate-level netlist with RTL, the chip simulation time can be greatly shortened, and the larger the chip scale is, the more redundant modules are, the more obvious the acceleration effect is. In addition, the rapid simulation verification makes the chip design iteration more efficient, shortens the chip design period, accelerates the process from design to mass production of products, and occupies the market.

The foregoing general description and the following description are exemplary and explanatory only and are not restrictive of the application.

Drawings

One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and in which like reference numerals refer to similar elements, and in which:

FIG. 1 is a schematic flow chart of a post-chip simulation verification acceleration method provided in an embodiment of the disclosure;

FIG. 2 is a flow chart of another post-chip simulation verification acceleration method provided by an embodiment of the present disclosure;

FIG. 3 is a schematic diagram of a post-chip simulation verification acceleration system according to an embodiment of the present disclosure;

Fig. 4 is a schematic structural diagram of a post-chip simulation verification acceleration device according to an embodiment of the present disclosure.

Detailed Description

So that the manner in which the features and techniques of the disclosed embodiments can be understood in more detail, a more particular description of the embodiments of the disclosure, briefly summarized below, may be had by reference to the appended drawings, which are not intended to be limiting of the embodiments of the disclosure. In the following description of the technology, for purposes of explanation, numerous details are set forth in order to provide a thorough understanding of the disclosed embodiments. However, one or more embodiments may still be practiced without these details. In other instances, well-known structures and devices may be shown simplified in order to simplify the drawing.

The terms "first," "second," and the like in embodiments of the present disclosure are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate in order to describe embodiments of the present disclosure. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion.

The term "plurality" means two or more, unless otherwise indicated.

In the embodiment of the present disclosure, the character "/" indicates that the front and rear objects are an or relationship. For example, A/B represents A or B.

The term "and/or" is an associative relationship that describes an object, meaning that there may be three relationships. For example, A and/or B, represent A or B, or three relationships of A and B.

The term "corresponding" may refer to an association or binding relationship, and the correspondence between a and B refers to an association or binding relationship between a and B.

The chip simulation verification acceleration method, device, equipment and storage medium provided by the embodiment of the disclosure are described below with reference to the accompanying drawings.

Fig. 1 is a flow chart of a post-chip simulation verification acceleration method according to an embodiment of the disclosure.

As shown in fig. 1, the post-chip simulation verification acceleration method may include:

S101, collecting multidimensional data of a large-scale chip;

s102, collecting all module names of a given chip, and confirming that the names of a control channel and a data channel which are irrelevant to a verification function are defined as redundant modules RTL through pre-simulation analysis and function specification;

s103, establishing a mapping relation between a redundancy module RTL and a corresponding gate-level netlist, ensuring that interfaces before and after replacement are completely consistent, and designing an automatic script recognition and processing parameterization module;

s104, constructing a post-simulation verification environment, loading a gate-level netlist and RTL as a simulation file list, importing an SDF file, extracting a test case from the prior simulation environment, and running simulation;

S105, verifying consistency of output responses before and after replacement, analyzing time delay change of a critical path, calculating dynamic power consumption and static power consumption of each functional module before and after replacement, and generating simulation verification results.

extracting a complete RTL code from a code warehouse of a chip design project;

It can be seen that, aiming at the aspect of multidimensional data collection, various data of a large-scale chip are comprehensively collected, and the method is a working basis of subsequent simulation. The RTL code details the logic functions of the chip. The gate level netlist is a logic gate connection relation for converting RTL codes into concrete, and reflects the underlying circuit structure of the chip. The standard delay format SDF file records delay information for each logic gate in the gate level netlist. The module names of the gate-level netlist in a given chip, independent of the current function, are collected to locate redundant design modules.

For determining the redundant module, collecting all module names of a given chip, and confirming the names of a control path and a data path which are irrelevant to a verification function through the prior simulation analysis and the function specification to be the redundant module. The manual verification confirms the position of the redundant module in the chip architecture and the interaction relation between the redundant module and the core function.

And for the replacement of the gate-level netlist, establishing a mapping relation between the redundancy module RTL and the corresponding gate-level netlist, and ensuring that interfaces before and after the replacement are completely consistent. And designing an automation script to identify and process the parameterized module, so as to avoid layering and naming conflicts. And extracting key path delay characteristics based on the SDF file, designing a time sequence adapter of an interface, and ensuring that a proper delay unit is inserted between the RTL and the gate-level netlist.

For the post-simulation verification, a post-simulation verification environment is built, a gate-level netlist and RTL are loaded as a simulation file list, SDF files are imported, test cases are extracted from the prior simulation environment, and simulation is operated.

And aiming at result comparison, verifying consistency of output responses before and after replacement, analyzing time delay change of a critical path, and calculating dynamic power consumption and static power consumption of each functional module before and after replacement.

Fig. 2 is a flow chart of another post-chip simulation verification acceleration method provided in an embodiment of the present disclosure, and the post-chip simulation verification acceleration method in fig. 1 is further described with reference to fig. 2.

Specifically, 1. Multidimensional data collection phase

RTL code is collected by extracting complete RTL code from a code repository of chip design projects. For a large-scale chip, the RTL code may be composed of code files of multiple functional modules. These code files are sorted into a specific project directory for subsequent processing.

And (3) obtaining a gate-level netlist, namely carrying out comprehensive treatment on the sorted RTL codes by using a chip design tool to generate a corresponding gate-level netlist, and operating a comprehensive command after setting a target process library and comprehensive constraint conditions (such as area, time sequence and the like) by using a Synopsys Design Compiler tool to obtain a gate-level netlist file stored in a standard format.

And (3) sorting the SDF file, wherein the SDF file records the delay information of each logic gate in the gate-level netlist under different working conditions (such as different voltages and temperatures). And storing the SDF file and the corresponding gate-level netlist file in an associated manner, so that the subsequent simulation call is convenient.

And collecting and sorting test case sets used in the simulation stage before the chip. These test cases refer to the fact that the logic function correctness of the chip has been verified, and are usually written in a specific test platform language (such as SystemVerilog). And classifying and sorting the test cases, and marking the test cases related to different functional modules so as to be used in the post-simulation power consumption evaluation in a targeted manner.

2. Redundancy module determination stage

The redundancy module determination determines the redundancy module in a manner that combines a rule-based screening algorithm with machine learning.

First, according to the functional specification of the chip, a set of core functional modules related to the current verification function is defined. And identifying control signals and data flows participating in the core path by analyzing the pre-simulation waveform, and marking the modules irrelevant to the core path. For example, when verifying the image processing function of the chip, an image acquisition module, an image filtering module, and the like are defined as core function modules. Then, by combining the pre-simulation results, traversing all module names, and further analyzing the control paths and the data paths of the modules which are not contained in the core function module set. If the control signal of a module does not participate in the control logic of the current verification function and the data path of the module does not provide valid data for the current verification function, the module is marked as a candidate redundant module.

And (3) machine learning auxiliary screening, namely introducing a machine learning algorithm to carry out secondary screening on the candidate redundant modules in order to improve the accuracy of the determination of the redundant modules. The redundancy module labeling data in the historical chip design project is used as a training set, and the characteristics of functional description keywords, connection relation with a core module, signal interaction frequency and the like of the module are selected to train classification models such as a Support Vector Machine (SVM) or a random forest. And predicting the candidate redundant modules through the model, and outputting a final redundant module list.

3. Gate level netlist replacement phase

And establishing a mapping relation by utilizing Python language to develop an automation script based on rule matching and comparing the port number, the name, the bit width, the direction and other attributes of the RTL module and the gate level netlist module. For the modules with different names and identical functions, the modules are associated by establishing a mapping table.

The parameterization module processes that, aiming at the parameterization module, the automation script adopts the regular expression matching module to instantiate a parameter transfer part in the sentence, extracts the parameter value and records. In the replacement process, according to the instantiation condition of the parameterized module in the gate-level netlist, the parameter value of the corresponding module in the RTL code is automatically adjusted, and the layering and naming conflict problems caused by inconsistent parameters are avoided. Meanwhile, the script can check the nesting calling condition of the parameterized module, recursively process parameter transmission at all levels, and ensure the accuracy of the whole replacement process.

And (3) designing a time sequence adapter, namely inserting a proper delay unit at an interface of the RTL and the gate-level netlist according to the key path delay data extracted by the SDF file. In specific implementation, firstly, delay information of the redundant module interface signals in the SDF file is analyzed, and delay time to be compensated is calculated. Then, an appropriate delay cell type (e.g., D flip-flop, buffer, delay line, etc.) is selected based on the delay time, and instantiation is performed at the interface. In order to ensure the accuracy of the time sequence, the time sequence adapter also performs time sequence constraint on the inserted delay unit, and ensures the time sequence matching between the RTL and the gate-level netlist by setting constraint conditions such as clock offset, set-up time, retention time and the like.

4. Post-simulation verification stage

The post-simulation verification module is built based on a mainstream EDA simulation platform, and the implementation steps are as follows:

Firstly, creating project engineering based on a verification platform of previous simulation, and configuring simulation environment parameters including simulator type, simulation time precision, memory allocation and the like. Then, automatically importing the gate-level netlist and the RTL code as a simulation file list through script, and importing the SDF file into a simulation environment to ensure that the simulator can read delay information of the gate-level netlist.

And (3) extracting the test case from the front simulation environment, wherein the simulation objects of the front simulation and the rear simulation are different. For test cases written based on RTL codes, the excitation signals and the monitoring signals in the test cases need to be modified according to the port names and the signal definitions of the gate-level netlist. Meanwhile, in order to ensure that the test cases can cover the replaced hybrid simulation model, the test cases are expanded, and monitoring of RTL and gate-level netlist interface signals is increased.

And executing the simulation task, namely starting the simulation task through a script by utilizing a command line interface of the simulation platform. In the simulation process, break points and monitoring points are set, and the simulation state and the change of key signals are monitored in real time. And simultaneously, recording the simulation output result into a log file so as to analyze the subsequent result comparison module.

5. Result comparison stage

And verifying consistency of output response, namely automatically reading simulation output files before and after replacement by a comparison program, and verifying consistency of the output response by adopting a mode of combining character string matching and numerical calculation. And for the output result of the numerical value type, calculating the difference value of the output result and comparing the difference value with a preset error threshold value. If the difference is within the error threshold, the output responses are deemed consistent.

And analyzing the time delay change of the critical path by combining the time delay information of the critical path recorded in the SDF file and the time sequence data in the simulation result. The comparison program extracts the signal arrival time of each node on the critical path before and after replacement, calculates the time delay difference value, and generates a time delay change analysis report.

And (3) comparing the dynamic power consumption, namely calling a power consumption analysis tool to respectively analyze the dynamic power consumption of the simulation results before and after replacement. The comparison program obtains dynamic power consumption data of the main functional module, calculates a power consumption difference value and performs statistical analysis. And evaluating the influence of gate-level netlist replacement on chip power consumption by comparing power consumption ratio changes of different modules.

According to the method for accelerating the simulation verification after the chip, provided by the embodiment of the disclosure, the gate-level netlist which is not related to the current simulation function is replaced by RTL through constructing the hybrid simulation model, so that the actual simulation scale of the chip is reduced, the problem of overlong simulation time after a large-scale integrated circuit is obviously shortened, and the simulation efficiency is effectively improved.

The invention at least comprises the following beneficial results:

1. The simulation efficiency is accelerated, namely, the simulation time of a chip can be greatly shortened by replacing the gate-level netlist with RTL, and the larger the chip scale is, the more redundant modules are, the more obvious the acceleration effect is.

2. The development period is shortened, the chip design iteration is more efficient due to the rapid simulation verification, the chip design period is shortened, the process from design to mass production of products is accelerated, and the market is preempted.

Corresponding to the post-chip simulation verification acceleration method in fig. 1, the present disclosure further provides a post-chip simulation verification acceleration system, as shown in fig. 3, where the system may specifically include:

a multidimensional data collection module 301 for collecting multidimensional data of a large-scale chip;

The redundancy module determining module 302 is configured to collect all module names of a given chip, and confirm that names of control paths and data paths irrelevant to a verification function are defined as redundancy module RTL through pre-simulation analysis and function specification;

The gate-level netlist replacing module 303 is used for establishing a mapping relation between the redundancy module RTL and the corresponding gate-level netlist, ensuring that interfaces before and after replacement are completely consistent, and designing an automatic script recognition and processing parameterization module;

the post-simulation verification module 304 is used for building a post-simulation verification environment, loading a gate-level netlist and RTL as a simulation file list, importing an SDF file, extracting a test case from the previous simulation environment, and running simulation;

The result comparison module 305 is used for verifying consistency of output responses before and after replacement, analyzing time delay change of a key path, calculating dynamic power consumption and static power consumption of each functional module before and after replacement, and generating simulation verification results.

extracting a complete RTL code from a code warehouse of a chip design project;

As shown in connection with fig. 4, an embodiment of the present disclosure further provides a post-chip emulation verification acceleration device 400, including a processor 404 and a memory 401. Optionally, the system may also include a communication interface (Communication Interface) 402 and a bus 403. The processor 404, the communication interface 402, and the memory 401 may communicate with each other via the bus 403. The communication interface 402 may be used for information transfer. The processor 404 may invoke logic instructions in the memory 401 to perform the post-chip emulation verification acceleration method of the above-described embodiment.

Further, the logic instructions in the memory 401 described above may be implemented in the form of software functional units and may be stored in a computer readable storage medium when sold or used as a stand alone product.

The memory 401 is a computer readable storage medium, and may be used to store a software program, a computer executable program, such as program instructions/modules corresponding to the methods in the embodiments of the present disclosure. The processor 404 executes the functional application and the data processing by executing the program instructions/modules stored in the memory 401, i.e., implements the post-chip simulation verification acceleration method in the above-described embodiment.

The memory 401 may include a storage program area which may store an operating system, application programs required for at least one function, and a storage data area which may store data created according to the use of the terminal device, etc. In addition, memory 401 may include high-speed random access memory, and may also include nonvolatile memory.

Embodiments of the present disclosure provide a computer-readable storage medium storing computer-executable instructions configured to perform a post-chip emulation verification acceleration method.

The computer readable storage medium may be a transitory computer readable storage medium or a non-transitory computer readable storage medium.

Embodiments of the present disclosure may be embodied in a software product stored on a storage medium, including one or more instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of a method of embodiments of the present disclosure. The storage medium may be a non-transitory storage medium, including a usb disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or may be a transitory storage medium.

The above description and the drawings illustrate embodiments of the disclosure sufficiently to enable those skilled in the art to practice them. Other embodiments may involve structural, logical, electrical, process, and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the sequence of operations may vary. Portions and features of some embodiments may be included in, or substituted for, those of others. As used in the description of the embodiments, the singular forms "a," "an," and "(the)" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Similarly, the term "and/or" as used in this disclosure is meant to encompass any and all possible combinations of one or more of the associated listed items. Furthermore, when used in the present disclosure, the terms "comprises," "comprising," and/or variations thereof, mean that the recited features, integers, steps, operations, elements, and/or components are present, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Without further limitation, an element defined by the phrase "comprising one..+ -." does not exclude the presence of additional identical elements in a process, method or apparatus comprising the element. In this context, each embodiment may be described with emphasis on the differences from the other embodiments, and the same similar parts between the various embodiments may be referred to each other. For the methods, products, etc. disclosed in the embodiments, if they correspond to the method sections disclosed in the embodiments, the description of the method sections may be referred to for relevance.

Those of skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. The skilled person may use different methods for each particular application to achieve the described functionality, but such implementation should not be considered to be beyond the scope of the embodiments of the present disclosure. It will be clearly understood by those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, which are not described herein again.

In the embodiments disclosed herein, the disclosed methods, articles of manufacture (including but not limited to devices, apparatuses, etc.) may be practiced in other ways. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of elements may be merely a logical functional division, and there may be additional divisions when actually implemented, e.g., multiple elements or components may be combined or integrated into another system, or some features may be omitted or not performed. In addition, the coupling or direct coupling or communication connection shown or discussed with each other may be through some interface, device or unit indirect coupling or communication connection, which may be in electrical, mechanical or other form. The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of network units. Some or all of the units may be selected according to actual needs to implement the present embodiment. In addition, each functional unit in the embodiments of the present disclosure may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.

The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. In the description corresponding to the flowcharts and block diagrams in the figures, operations or steps corresponding to different blocks may also occur in different orders than that disclosed in the description, and sometimes no specific order exists between different operations or steps. For example, two consecutive operations or steps may actually be performed substantially in parallel, they may sometimes be performed in reverse order, which may be dependent on the functions involved. Each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

Various implementations of the systems and techniques described here above may be implemented in digital electronic circuitry, integrated circuit systems, field Programmable Gate Arrays (FPGAs), application Specific Integrated Circuits (ASICs), application Specific Standard Products (ASSPs), systems On Chip (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include being implemented in one or more computer programs that are executable and/or interpretable on a programmable system including at least one programmable processor, which may be a special or general purpose programmable processor, operable to receive data and instructions from, and to transmit data and instructions to, a storage system, at least one input device, and at least one output device.

Program code for carrying out methods of the present disclosure may be written in any combination of one or more programming languages. These program code may be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus such that the program code, when executed by the processor or controller, causes the functions/operations specified in the flowchart and/or block diagram to be implemented. The program code may execute entirely on the machine, partly on the machine, as a stand-alone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or server.

In the context of this disclosure, a machine-readable medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. The machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

To provide for interaction with a user, the systems and techniques described here can be implemented on a computer having a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user and a keyboard and a pointing device (e.g., a mouse or a trackball) by which the user can provide input to the computer. Other types of devices may also be used to provide interaction with the user, for example, feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback), and input from the user may be received in any form, including acoustic input, speech input, or tactile input.

The systems and techniques described here can be implemented in a computing system that includes a background component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such background, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a Local Area Network (LAN), a Wide Area Network (WAN), and the Internet.

The computer system may include a client and a server. The client and server are typically remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server may be a cloud server, a server of a distributed system, or a server incorporating a blockchain.

It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps recited in the present disclosure may be performed in parallel, sequentially, or in a different order, provided that the desired results of the technical solutions of the present disclosure are achieved, and are not limited herein.

The above detailed description should not be taken as limiting the scope of the present disclosure. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present disclosure are intended to be included within the scope of the present disclosure.

Claims

1. A chip post-simulation verification acceleration method, characterized in that the method comprises:

Collect multi-dimensional data of large-scale chips;

Collect all module names of a given chip, and confirm the names of control paths and data paths that are not related to the verification function through pre-simulation analysis and functional specifications, and define them as redundant module RTL;

Establish a mapping relationship between the redundant module RTL and the corresponding gate-level netlist to ensure that the interfaces before and after replacement are completely consistent, and design an automated script to identify and process parameterized modules;

Set up the post-simulation verification environment, load the gate-level netlist and RTL as the simulation file list and import the SDF file, extract the test cases from the pre-simulation environment and run the simulation;

Verify the consistency of output responses before and after replacement, analyze the delay changes of critical paths, calculate the dynamic power consumption and static power consumption of each functional module before and after replacement, and generate simulation verification results.

2. The method according to claim 1, wherein collecting multidimensional data of large-scale chips comprises:

Extract the complete RTL code from the code repository of the chip design project;

Use chip design tools to process the organized RTL code and generate the corresponding gate-level netlist. Use the Synopsys Design Compiler tool to run the synthesis command after setting the target process library and synthesis constraints to obtain a gate-level netlist file saved in a standard format.

Associating and storing the SDF file with the corresponding gate-level netlist file, wherein the SDF file records the delay information of each logic gate in the gate-level netlist under different working conditions;

Collect and organize the test case sets used in the pre-chip simulation stage, classify and organize the test cases, and mark the test cases related to different functional modules.

3. The method according to claim 1, wherein the step of collecting all module names of a given chip and confirming, through pre-simulation analysis and functional specifications, that the names of control paths and data paths that are not relevant to the verification function are defined as redundant module RTLs comprises:

According to the functional specifications of the chip, define the set of core functional modules related to the current verification function. By analyzing the previous simulation waveform, identify the control signals and data flows involved in the core path, mark the modules not related to the core path, and traverse all module names based on the previous simulation results. For modules not included in the core functional module set, further analyze their control paths and data paths. If the module's control signal does not participate in the control logic of the current verification function and its data path does not provide valid data for the current verification function, mark the corresponding module as a candidate redundant module.

Use redundant module annotation data from historical chip design projects as a training set, select module function description keywords, connection relationships with core modules, and signal interaction frequency characteristics, train a support vector machine or random forest classification model to predict candidate redundant modules, and output the final redundant module RTL list.

4. The method according to claim 1, wherein establishing a mapping relationship between the redundant module RTL and the corresponding gate-level netlist to ensure that the interfaces before and after replacement are completely consistent, and designing an automated script to identify and process parameterized modules, comprises:

Develop rule-based matching automation scripts using Python. Establish mapping relationships between RTL modules and gate-level netlist modules by comparing their port numbers, names, bit widths, and direction attributes. For modules with different names but the same functions, establish associations by establishing mapping tables.

For parameterized modules, the automated script uses regular expressions to match the parameter transfer portion of the module instantiation statement, extracts the parameter values, and records them. During the replacement process, the parameter values of the corresponding modules in the RTL code are adjusted based on the instantiation of the parameterized modules in the gate-level netlist, avoiding hierarchical and naming conflicts caused by inconsistent parameters. The script also checks the nested calls of the parameterized modules and recursively processes the parameter transfer at all levels to ensure the accuracy of the entire replacement process.

Extract the critical path delay data according to the SDF file and insert the corresponding delay unit at the interface between RTL and gate-level netlist.

5. The method according to claim 4, wherein extracting critical path delay data according to the SDF file and inserting corresponding delay units at the interface between the RTL and gate-level netlist comprises:

Analyze the delay information of the redundant module interface signal in the SDF file and calculate the delay time that needs to be compensated;

Select the appropriate delay unit type based on the delay time and instantiate it at the interface;

The timing adapter performs timing constraints on the inserted delay units and ensures timing matching between the RTL and gate-level netlist by setting clock offset, setup time, and hold time constraints.

6. The method according to claim 1, wherein the step of building a post-simulation verification environment, loading a gate-level netlist and RTL as a simulation file list and importing an SDF file, extracting test cases from a pre-simulation environment, and running a simulation comprises:

Create a project based on the pre-simulation verification platform and configure simulation environment parameters, including simulator type, simulation time accuracy, and memory allocation;

Automatically import the gate-level netlist and RTL code as a simulation file list through scripts, and import the SDF file into the simulation environment to ensure that the simulator can read the delay information of the gate-level netlist;

Extract test cases from the pre-simulation environment. For test cases written based on RTL code, modify the stimulus and monitoring signals in the test cases according to the port names and signal definitions of the gate-level netlist. Expand the test cases and add monitoring of the interface signals between the RTL and gate-level netlist.

Use the command line interface of the simulation platform to start the simulation task through the script. During the simulation process, set breakpoints and monitoring points to monitor the simulation status and changes in key signals in real time, and record the simulation output results in the log file for subsequent analysis by the result comparison module.

7. The method according to claim 1, wherein verifying the consistency of output responses before and after replacement, analyzing the delay change of the critical path, and calculating the dynamic power consumption and static power consumption of each functional module before and after replacement comprises:

The comparison program automatically reads the simulation output files before and after the replacement, and uses a combination of string matching and numerical calculation to verify the consistency of the output response;

Combine the critical path delay information recorded in the SDF file with the timing data in the simulation results to analyze the delay changes of the critical path;

Call the power consumption analysis tool to perform dynamic power consumption analysis on the simulation results before and after the replacement, obtain the dynamic power consumption data of the target functional module, calculate the power consumption difference, and perform statistical analysis. By comparing the changes in the power consumption proportion of different modules, the impact of gate-level netlist replacement on chip power consumption is evaluated.

8. A chip post-simulation verification acceleration system, characterized in that the system comprises:

Multi-dimensional data collection module, used to collect multi-dimensional data of large-scale chips;

The redundant module determination module is used to collect the names of all modules of a given chip, and confirm the names of control paths and data paths that are not related to the verification function through pre-simulation analysis and functional specifications as redundant module RTL;

The gate-level netlist replacement module is used to establish the mapping relationship between the redundant module RTL and the corresponding gate-level netlist, ensuring that the interfaces before and after the replacement are completely consistent, and to design an automated script to identify and process parameterized modules;

Post-simulation verification module, used to build the post-simulation verification environment, load the gate-level netlist and RTL as simulation file list and import SDF file, extract test cases from the pre-simulation environment and run simulation;

The result comparison module is used to verify the consistency of output responses before and after replacement, analyze the delay changes of critical paths, calculate the dynamic power consumption and static power consumption of each functional module before and after replacement, and generate simulation verification results.

9. An electronic device, comprising:

at least one processor;

and a memory communicatively coupled to the at least one processor;

The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 7.

10. A non-transitory computer-readable storage medium storing computer instructions, characterized in that:

The computer instructions are used to cause the computer to execute the method according to any one of claims 1 to 7.