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CN120821331A - Processing chip, chip system and electronic equipment - Google Patents

Processing chip, chip system and electronic equipment

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Publication number
CN120821331A
CN120821331A CN202410437378.1A CN202410437378A CN120821331A CN 120821331 A CN120821331 A CN 120821331A CN 202410437378 A CN202410437378 A CN 202410437378A CN 120821331 A CN120821331 A CN 120821331A
Authority
CN
China
Prior art keywords
transistor
terminal
coupled
circuit
clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202410437378.1A
Other languages
Chinese (zh)
Inventor
陈焱沁
李超男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Huawei Technologies Co Ltd
Original Assignee
Huawei Technologies Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huawei Technologies Co Ltd filed Critical Huawei Technologies Co Ltd
Priority to CN202410437378.1A priority Critical patent/CN120821331A/en
Publication of CN120821331A publication Critical patent/CN120821331A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

The embodiment of the application provides a processing chip, a chip system and electronic equipment, and belongs to the technical field of semiconductors. The processing chip comprises a clock source, an interpolator and a bias circuit. The interpolator includes a clock weight generation circuit including an interpolation circuit. The interpolation circuit includes a first transistor, a second transistor, a positive bias transistor, and a negative bias transistor. The second terminal of the first transistor is coupled to the first terminal of the forward bias transistor and the second terminal of the forward bias transistor is grounded. The second terminal of the second transistor is coupled to the first terminal of the negative bias transistor, and the second terminal of the negative bias transistor is grounded. The control end of the first transistor and the control end of the second transistor are respectively coupled with a clock source, and the second end of the first transistor and the second end of the second transistor are coupled as output ends of the interpolation circuit. The application improves the linearity of the phase of the output clock of the interpolator.

Description

Processing chip, chip system and electronic equipment
Technical Field
The present application relates to semiconductor technology, and more particularly, to a processing chip, a chip system, and an electronic device.
Background
Clock data recovery circuits (clock data recovery CDR) are widely used in various high-speed serial communications scenarios, such as optical communications, board-level, chip-level high-speed signaling, and the like. The clock data recovery circuit is used for recovering a clock signal synchronous with the received data signal. The common clock data recovery circuit may be implemented based on a phase interpolation circuit (phase interpolator, PI). Further, in order to improve accuracy of clock processing and data recovery, the phase of the output clock of the phase interpolation circuit needs to have high linearity.
Disclosure of Invention
The embodiment of the application provides a processing chip, a chip system and electronic equipment, which are used for improving the linearity of the phase of an output clock of a phase interpolation circuit.
In order to achieve the above purpose, the embodiment of the application adopts the following technical scheme:
In a first aspect, a processing chip is provided. The processing chip includes a clock source, an interpolator, and a bias circuit. The interpolator includes at least two clock weight generation circuits, each including an interpolation circuit. Each interpolation circuit comprises a first transistor, a second transistor, a positive bias transistor and a negative bias transistor, wherein the first end of the first transistor and the first end of the second transistor are respectively used for inputting a power supply voltage, the second end of the first transistor is coupled with the first end of the positive bias transistor, the second end of the positive bias transistor is grounded, the second end of the second transistor is coupled with the first end of the negative bias transistor, and the second end of the negative bias transistor is grounded. The control terminal of the positive bias transistor is coupled to the positive output terminal of the bias circuit, and the control terminal of the negative bias transistor is coupled to the negative output terminal of the bias circuit. The control end of the first transistor and the control end of the second transistor are used as the input ends of the corresponding clock weight generating circuits to be respectively coupled with the output ends of the clock sources, and the second end of the first transistor and the second end of the second transistor are used as the output ends of the corresponding clock weight generating circuits after being coupled, and the output ends of at least two clock weight generating circuits are coupled.
In the embodiment of the application, the clock source can output clocks with a plurality of phases, the bias circuit can output positive bias voltage V BN+ and negative bias voltage V BN- according to the weight code value and the phase code value, and the interpolator comprises at least two clock weight generating circuits, and the output ends of the at least two clock weight generating circuits are coupled, so that the weighted output of the clock phases is realized. The linearity of the phase of the output clock of the clock weight generation circuit directly affects the performance of the processing chip. In an embodiment of the present application, each clock weight generation circuit includes an interpolation circuit in which a control terminal of a first transistor and a control terminal of a second transistor are coupled to an output terminal of a clock source, respectively, for receiving a set of differential clocks (e.g., V IN+ and V IN-; where V IN+ and V IN- are 180 ° out of phase) from the clock source. The control terminal of the positive bias transistor in the interpolation circuit is coupled to the positive output terminal of the bias circuit for receiving the positive bias voltage V BN+. The interpolation circuit is coupled to the negative output of the bias circuit at the control terminal of the negative bias transistor for receiving a negative bias voltage V BN-. According to the circuit configuration of the interpolation circuit, the output expression function of the interpolation circuit can be expressed as: Wherein V TH is the on threshold voltage of the transistor. In the embodiment of the application, only V BN++VBN- output by the bias circuit is required to be controlled to be a constant value, so that the output of the interpolation circuit is in direct proportion to V BN+-VBN-. The bias circuit provided by the embodiment of the application realizes the control of the output value of the interpolation circuit, so that the clock weight generating circuit can realize the linear output of small signals, and further the linearity of the phase of the output clock of the interpolator is improved.
In some possible embodiments, each clock weight generation circuit includes two interpolation circuits, a positive interpolation circuit and a negative interpolation circuit, respectively. For each clock weight generating circuit, in the positive interpolation circuit, the control end of the first transistor is used as the positive input end of the corresponding clock weight generating circuit to be coupled with the positive output end of the clock source, the control end of the second transistor is used as the negative input end of the corresponding clock weight generating circuit to be coupled with the negative output end of the clock source, and the second end of the first transistor and the second end of the second transistor are used as the positive output end of the corresponding clock weight generating circuit after being coupled. For each clock weight generating circuit, in the negative interpolation circuit, the control end of the first transistor is used as the negative input end of the corresponding clock weight generating circuit to be coupled with the negative output end of the clock source, the control end of the second transistor is used as the positive input end of the corresponding clock weight generating circuit to be coupled with the positive output end of the clock source, and the second end of the first transistor and the second end of the second transistor are used as the negative output end of the corresponding clock weight generating circuit after being coupled. The positive output ends of the at least two clock weight generating circuits are coupled, and the negative output ends of the at least two clock weight generating circuits are coupled. The embodiment of the application is provided with two interpolation circuits in each clock weight generation circuit, wherein the output expression function of the positive interpolation circuit can be expressed as follows: The output expression function of the negative interpolation circuit can be expressed as: Thereby enabling the interpolator to output a differential clock.
In some possible embodiments, the bias circuit includes at least two code value conversion circuits, the at least two code value conversion circuits being in one-to-one correspondence with the at least two clock weight generation circuits. The code value conversion circuit comprises a first resistor, a second resistor, a phase switch and a power supply circuit, wherein a first end of the power supply circuit is coupled with a first end of the first resistor, a second end of the first resistor is grounded with a first end of the second resistor, and a second end of the power supply circuit is coupled with a second end of the second resistor. The first end of the phase switch is for coupling with a first power supply, the second end of the phase switch is coupled with the first end of the first resistor, and the second end of the phase switch is coupled with the second end of the second resistor. The control end of the phase switch tube is used as the phase code value input end of the corresponding code value conversion circuit, the first end of the first resistor is used as the positive output end of the corresponding code value conversion circuit and is coupled with the control end of the positive bias transistor in the corresponding clock weight generation circuit, and the second end of the second resistor is used as the negative output end of the corresponding code value conversion circuit and is coupled with the control end of the negative bias transistor in the corresponding clock weight generation circuit. In the embodiment of the application, the sum of the currents flowing through the first resistor and the second resistor can be kept constant by controlling the output current of the first power supply in the code value conversion circuit to be unchanged and the sum of the output current of the first end and the output current of the second end of the power supply circuit to be unchanged. That is, V BN++VBN- outputted from the bias circuit can be set to a constant value by the code value conversion circuit. And, the current flowing through the first resistor and the second resistor can be adjusted by the phase switch and the power supply circuit, and the value of V BN+-VBN- output by the bias circuit can be adjusted to adjust the phase weight of the clock.
In some examples, the first power supply is a first current source. The internal resistance of the current source is large relative to the load impedance, and the load impedance fluctuation does not change the current, so that the output current of the first power supply source can be ensured to be unchanged to a certain extent.
In some possible implementations, the power supply circuit includes a plurality of weight switches, a first end of each weight switch being for coupling with a corresponding second power supply, a second end of each weight switch being coupled with a first end of the first resistor, a third end of each weight switch being coupled with a second end of the second resistor. The control ends of the weight switch tubes are used as weight code value input ends of the corresponding code value conversion circuits. In the embodiment of the application, when the first end and the second end of the weight switch are conducted, the current is output from the first end of the power supply circuit through the weight transistor, and when the first end and the third end of the weight switch are conducted, the current is output from the second end of the power supply circuit through the weight transistor. The on states of the weight switches are controlled through the weight code values so as to adjust the value of V BN+-VBN- output by the bias circuit, and then the phase weight of the clock is adjusted.
In some examples, the second power supply is a second current source, where the second power supply is the second current source, so that the sum of the output current of the first end and the output current of the second end of the power supply circuit can be ensured to be unchanged to a certain extent. The number of the weight switches is N, the output current of the first current source is N of the output current of the single second current source, and therefore calculation of circuit parameters is facilitated, and circuit design is simplified.
In some possible implementations, the code value conversion circuit further includes a bias transistor having a first terminal coupled to the coupling point of the first resistor and the second resistor, a second terminal coupled to ground, and a control terminal coupled to the first terminal of the bias transistor. According to the embodiment of the application, the bias transistor can provide bias current for turning on the positive bias transistor and the negative bias transistor in the interpolation circuit. In addition, the embodiment of the application can alleviate or even overcome the problem of burrs generated by an output clock when the phase code value and the weight code value are switched through resistance-capacitance filtering formed by the parasitic capacitance (PARASITIC CAPACITANCE) of the first resistor, the second resistor and the bias transistor.
In some possible implementations, the processing chip further includes at least two integrator circuits, the at least two integrators being in one-to-one correspondence with the at least two clock weight generation circuits. The integrating circuit comprises a pull-down current source, a third transistor and a fourth transistor, wherein the first end of the third transistor and the first end of the fourth transistor are respectively used for being coupled with a power supply, the second controlled end of the third transistor is coupled with the positive electrode end of the pull-down current source, the second controlled end of the fourth transistor is coupled with the positive electrode end of the pull-down current source, and the negative electrode end of the pull-down current source is grounded. The control end of the third transistor is used as the positive input end of the integrating circuit and is coupled with the positive output end of the clock source, and the control end of the fourth transistor is used as the negative input end of the integrating circuit and is coupled with the negative output end of the clock source. The first end of the third transistor is used as the negative output end of the integrating circuit and is coupled with the negative input end of the corresponding clock weight generating circuit, and the first end of the fourth transistor is used as the positive output end of the integrating circuit and is coupled with the positive input end of the corresponding clock weight generating circuit. According to the embodiment of the application, the integrator is adopted to shape the clock into the triangular wave, and the triangular wave clock is used as the input of the interpolator, so that the linearity of the interpolator is improved.
In some possible embodiments, the pull-down current source includes a third current source and a fourth current source, the second controlled terminal of the third transistor is coupled to the positive terminal of the third current source, the second controlled terminal of the fourth transistor is coupled to the positive terminal of the fourth current source, the negative terminal of the third current source and the negative terminal of the fourth current source are grounded. The integrating circuit further comprises a voltage accelerating circuit, the voltage accelerating circuit comprises a first capacitor, a second capacitor, a fifth current source, a sixth current source, a fifth transistor and a sixth transistor, wherein the first end of the fifth transistor and the first end of the sixth transistor are respectively used for inputting a power supply voltage, the second end of the fifth transistor is coupled with the positive electrode end of the fifth current source, the second end of the sixth transistor is coupled with the positive electrode end of the sixth current source, and the negative electrode end of the fifth current source and the negative electrode end of the sixth current source are grounded. The first end of the first capacitor is coupled to the second end of the fifth transistor, the second end of the first capacitor is coupled to the second end of the third transistor, the first end of the second capacitor is coupled to the second end of the sixth transistor, and the second end of the second capacitor is coupled to the second end of the fourth transistor. The control terminal of the fifth transistor is coupled to the control terminal of the fourth transistor, and the control terminal of the sixth transistor is coupled to the control terminal of the third transistor. Since the second end of the input pair tube (i.e., the third transistor and the fourth transistor) of the integrating circuit has a parasitic capacitance to the ground, the parasitic capacitance can cause the voltage response speed of the second end of the input pair tube to be slow, so that when any one of the input pair tube is turned on, the voltage of the second end of the input pair tube is higher, the pull-down current from the output end of the integrating circuit is higher than the preset current, and the current cannot be changed back to the preset value until the voltage of the second end of the input pair tube is completely established. The triangular wave waveform output by the output end of the integrating circuit is distorted due to the influence of the large pull-down current of the output end of the integrating circuit in a short time. According to the embodiment of the application, the voltage accelerating circuit is arranged and coupled with the second ends of the third transistor and the fourth transistor, so that the voltage establishing speed of the input of the integrating circuit to the second end of the transistor is improved, the influence of parasitic capacitance on the output of the integrating circuit is weakened, the non-ideal defect of the integrating circuit is optimized, the influence of slope deviation on the linearity of the interpolator is reduced, and the linearity of the interpolator is further improved.
In some possible implementations, the integrating circuit further includes a third capacitor having a first terminal coupled to the second terminal of the third transistor and a second terminal coupled to the second terminal of the fourth transistor. Due to the defects of the process manufacturing, the third transistor and the fourth transistor have deviation of threshold voltages, which causes deviation of the conduction of the third transistor and the fourth transistor. In the embodiment of the application, the second end of the third transistor and the second end of the fourth transistor are not in direct current coupling, but are coupled through the third capacitor, and the threshold voltage deviation cannot influence the output of the integrating circuit by utilizing the characteristic of direct current open circuit of the capacitor, so that the defects of the third transistor and the fourth transistor in process manufacturing are optimized.
In some possible implementations, the interpolation circuit further includes a fourth capacitor and a fifth capacitor, a first terminal of the fourth capacitor coupled to the second terminal of the first transistor, a second terminal of the fourth capacitor coupled to the first terminal of the fifth capacitor, and a second terminal of the fifth capacitor coupled to the second terminal of the second transistor. The coupling point of the fourth capacitor and the fifth capacitor is used as the output end of the interpolation circuit. Likewise, the second end of the first transistor is coupled with the second end of the second transistor through the fourth capacitor and the fifth capacitor, so that defects of the first transistor and the second transistor in process manufacturing are optimized, and linearity of the interpolator is guaranteed.
In some possible embodiments, the interpolator is provided with one or more. When a plurality of interpolators are arranged, the input ends of the interpolators are connected in parallel. The single interpolator can realize single-channel clock output, and the embodiment of the application can realize single-channel or multi-channel output by arranging one or more interpolators.
In some possible implementations, the processing chip further includes an output amplifier, an input of the output amplifier being coupled to an output of the interpolator. According to the embodiment of the application, the clock output by the interpolator is amplified by the output amplifier and output to the post-stage circuit.
In some possible implementations, the processing chip is an interface chip or a clock processing chip.
In a second aspect, a processing chip is provided. The processing chip comprises a clock source, an integrator and an interpolator, wherein the integrator comprises at least two integrating circuits. Each integrating circuit includes a first capacitor, a second capacitor, a third current source, a fourth current source, a fifth current source, a sixth current source, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor. The first end of the third transistor and the first end of the fourth transistor are respectively used for being coupled with a power supply, the second controlled end of the third transistor is coupled with the positive electrode end of the third current source, the second controlled end of the fourth transistor is coupled with the positive electrode end of the fourth current source, and the negative electrode end of the third current source and the negative electrode end of the fourth current source are grounded. The first end of the fifth transistor and the first end of the sixth transistor are respectively used for inputting a power supply voltage, the second end of the fifth transistor is coupled with the positive electrode end of the fifth current source, the second end of the sixth transistor is coupled with the positive electrode end of the sixth current source, and the negative electrode end of the fifth current source and the negative electrode end of the sixth current source are grounded. The first end of the first capacitor is coupled to the second end of the fifth transistor, the second end of the first capacitor is coupled to the second end of the third transistor, the first end of the second capacitor is coupled to the second end of the sixth transistor, and the second end of the second capacitor is coupled to the second end of the fourth transistor. The control end of the fifth transistor is coupled with the control end of the fourth transistor and then is used as the negative input end of the integrating circuit and is coupled with the negative output end of the clock source. The first end of the third transistor is used as the positive output end of the integrating circuit to be coupled with the positive input end of the interpolator, and the first end of the fourth transistor is used as the negative output end of the integrating circuit to be coupled with the negative input end of the interpolator.
In some possible implementations, the integrating circuit further includes a third capacitor having a first terminal coupled to the second terminal of the third transistor and a second terminal coupled to the second terminal of the fourth transistor.
In a third aspect, a system on a chip is provided. The chip system comprises a PCB board and the processing chip of any one of the first aspect and the second aspect, wherein the processing chip is arranged on the PCB board.
In a fourth aspect, an electronic device is provided. The electronic device includes a device housing and the chip system of the above third aspect, part or all of the chip system being disposed within the device housing.
Drawings
Fig. 1 is a block diagram of a phase interpolation circuit according to an embodiment of the present application;
fig. 2 is a schematic circuit diagram of an interpolator according to an embodiment of the present application;
FIG. 3 is a schematic circuit diagram of a standard cell according to an embodiment of the present application;
fig. 4 is a schematic circuit diagram of another interpolator according to an embodiment of the present application;
FIG. 5 is a block diagram of an electronic device and a chip system according to an embodiment of the present application;
FIG. 6 is a block diagram of a first processing chip for single-pass output according to an embodiment of the present application;
FIG. 7 is a block diagram illustrating a first configuration of processing chip multiplexing according to an embodiment of the present application;
FIG. 8 is a block diagram illustrating a first interpolator configuration according to an embodiment of the present application;
fig. 9 is a schematic circuit diagram of an interpolation circuit according to an embodiment of the present application;
FIG. 10 is a block diagram illustrating a second interpolator configuration according to an embodiment of the present application;
FIG. 11 is a schematic diagram of a circuit structure of a positive interpolation circuit according to an embodiment of the present application;
Fig. 12 is a schematic circuit diagram of a negative interpolation circuit according to an embodiment of the present application;
FIG. 13 is a block diagram illustrating a third interpolator configuration according to an embodiment of the present application;
FIG. 14 is a block diagram of a bias circuit according to an embodiment of the present application;
Fig. 15 is a schematic circuit diagram of a code value conversion circuit according to an embodiment of the present application;
FIG. 16 is a schematic diagram showing the phase correspondence between phase code values and selected clocks according to an embodiment of the present application;
FIG. 17 is a block diagram of a second processing chip according to an embodiment of the present application;
FIG. 18 is a block diagram of an integrator according to an embodiment of the present application;
fig. 19 is a schematic circuit diagram of a first integrating circuit according to an embodiment of the present application;
FIG. 20 is a schematic diagram showing a comparison of an ideal waveform and a distorted waveform output by an integrator circuit according to an embodiment of the present application;
fig. 21 is a schematic circuit diagram of a second integrating circuit according to an embodiment of the present application;
Fig. 22 is a schematic circuit diagram of a third integrating circuit according to an embodiment of the present application;
Fig. 23 is a schematic circuit diagram of a fourth integrating circuit according to an embodiment of the present application;
FIG. 24 is a block diagram of a third processing chip according to an embodiment of the present application;
FIG. 25 is a block diagram illustrating a fourth processing chip according to an embodiment of the present application;
Fig. 26 is a schematic circuit diagram of a fifth integrating circuit according to an embodiment of the present application.
Reference numeral 100, a phase interpolation circuit; 110, phase selector; 120, an integrator; 121, first integrating circuit, 122, second integrating circuit, 130, interpolator, 131, standard cell, 132, differential pair, 133, current controller, 134, first time Zhong Quanchong generating circuit, 135, second time clock generating circuit, 136, first full differential amplifier, 137, second full differential amplifier, 140, output amplifier, 150, bias circuit, 151, first code value converting circuit, 152, second code value converting circuit, 210, first standard cell, 211, current source, 212, current source switch, 213, in-phase transistor, 214, reverse transistor, 220, second standard cell, 300, electronic device, 310, chip system, 311, processing chip, 400, clock source, 500, interpolation circuit, 510, first transistor, 520, second transistor, 530, positive bias transistor, 540, negative bias transistor, 550, fourth capacitor, 560, fifth capacitor, 610, first resistor, 620, second resistor, 630, phase switch, 640, power supply, second capacitor, third capacitor, fourth capacitor, 79720, fifth transistor, third capacitor, fourth capacitor, 7975, fourth capacitor, third capacitor, fourth capacitor, fifth capacitor, third capacitor, fourth capacitor, fifth capacitor, fourth capacitor, fifth capacitor, fourth, capacitor, fifth, capacitor, fifth, positive capacitor, fourth, capacitor, fifth, fourth, fifth, fourth, second, second, a, the second NMOS tube, 797, the third NMOS tube, 798, the fourth NMOS tube.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail with reference to fig. 1 to 26 and the embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.
The terms "first," "second," and the like, in accordance with embodiments of the present application, are used solely for the purpose of distinguishing between similar features and not necessarily for the purpose of indicating a relative importance, number, sequence, or the like.
The terms "exemplary" or "such as" and the like, as used in relation to embodiments of the present application, are used to denote examples, illustrations, or descriptions. Any embodiment or design described herein as "exemplary" or "for example" should not be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete fashion.
The terms "coupled" and "connected" in accordance with embodiments of the application are to be construed broadly, and may refer, for example, to a physical direct connection, or to an indirect connection via electronic devices, such as, for example, electrical resistance, inductance, capacitance, or other electrical devices.
The phase interpolation circuit (phase interpolator, PI) can be widely used in various interface circuits. In some examples, when the phase interpolation circuit is applied to a parallel interface, the phase interpolation circuit may cooperate with a delay-locked loop (DLL) to perform phase interpolation on adjacent phase clocks generated by the delay-locked loop. In other examples, when the interpolator is applied to a serial interface, adjacent phase clocks generated by a phase locked loop (phase locked loop, PLL) may be phase interpolated as part of a clock data recovery circuit (clock data recovery, CDR). Phase locked loops/delay locked loops often perform coarse adjustments to the clock phase, while phase interpolation circuitry may perform fine adjustments to the clock phase. For example, the phase-locked loop/delay-locked loop may output clocks with phases of 0 °, 45 °, 90 °, 135 °, 180 °, 225 °, 270 °, and 315 °, and the phase interpolation circuit may generate an additional clock with phases between 225 ° and 270 ° according to the clock with the phase of 225 ° and the clock with the phase of 270 °, so as to improve the phase adjustment accuracy, and obtain a plurality of output clocks with finer phases.
Fig. 1 shows a basic framework diagram of a phase interpolation circuit 100. As shown in fig. 1, the phase interpolation circuit 100 may include a phase selector 110, an integrator 120, an interpolator 130, and an output amplifier 140. The clocks of the multiple phases are input to the phase selector 110, and the phase selector 110 may select two clocks of different phases (e.g., clock a and clock B) to input to the integrator 120 for processing based on the phase code values. The integrator 120 inputs the processed two clocks (clock P and clock Q) to the interpolator 130. The interpolator 130 controls the weights of the two clocks after processing according to the weight code value, and supplies the weighted output clock to the output amplifier 140, and the output amplifier 140 amplifies the output clock of the interpolator 130 and transmits the amplified output clock to the subsequent circuit. Where the interpolator 130 outputs the phase of the clock=the phase of the clock p×the weight p+the phase of the clock q×the weight Q, and the weight p+the weight q=1.
Fig. 2 shows a schematic circuit configuration of the interpolator 130. As shown in fig. 2, the interpolator 130 may include a resistor R1, a resistor R2, and a plurality of standard cells 131, and the plurality of standard cells 131 may be divided into a plurality of first standard cells 210 and a plurality of second standard cells 220. As shown in fig. 3, in some embodiments, each standard cell 131 (i.e., first standard cell 210 and second standard cell 220) may include a current source 211, a current source switch 212, an in-phase transistor 213, and a reverse transistor 214 (in-phase transistor 213 and reverse transistor 214 may be referred to as differential pair transistors). The control terminal of the in-phase transistor 213 is used as a first input terminal of the standard cell 131, the first terminal of the in-phase transistor 213 is used as a first output terminal of the standard cell 131, the control terminal of the reverse transistor 214 is used as a second input terminal of the standard cell 131, and the first terminal of the reverse transistor is used as a second output terminal of the standard cell 131. The second terminal of the in-phase transistor 213 and the second terminal of the reverse transistor 214 are both coupled to the first terminal of the current source switch 212, the second terminal of the current source switch 212 is coupled to the first terminal of the current source 211, the second terminal of the current source 211 is grounded, and the control terminal of the current source switch 212 serves as the control terminal of the standard cell 131 unit.
As shown in fig. 2, the first and second inputs of the plurality of first standard cells 210 are used to input a set of differential clocks (e.g., clock p+ and clock P-, with the phase of clock p+ being 0 ° and the phase of clock P-being 180 °), that is, the first input of the first standard cell 210 is used to input clock p+ and the second input of the first standard cell 210 is used to input clock P-. The first output terminals of the plurality of first standard cells 210 are coupled to one end of a resistor R1, the other end of the resistor R1 being used for inputting a supply voltage, and the second output terminals of the plurality of first standard cells 210 are coupled to one end of a resistor R2, the other end of the resistor R2 being used for inputting a supply voltage. The control terminals of the plurality of first standard units 210 are used for inputting weight code values. The first and second inputs of the plurality of second standard cells 220 are used for inputting another set of differential clocks (e.g., clock Q + and clock Q-, with the phase of clock Q + being 90 and the phase of clock Q-being 270), that is, the first input of the second standard cell 220 is used for inputting clock Q + and the second input of the second standard cell 220 is used for inputting clock Q-. The first output terminals of the plurality of second standard cells 220 are coupled to one end of the resistor R1 and the second output terminals of the plurality of second standard cells 220 are coupled to one end of the resistor R2. The control terminals of the second standard units 220 are used for inputting weight code values.
In the interpolator 130 shown in fig. 2, the weight code value controls the current source switch 212 in each standard cell 131, thereby changing the number of on/off of the current sources 211. Illustratively, the greater the number of first standard cells 210 with current source switches 212 open (the greater the number of second standard cells 220 with current source switches 212 closed), the greater the sum of the output currents at the first output and the second output of the plurality of first standard cells 210, the greater the weights of clock p+ and clock P-, thereby achieving clock phase weighting by current addition and thus phase adjustment of the output clock.
However, when the current source switch 212 in the standard cell 131 is closed, the output capacitance of the standard cell 131 is the gate-drain capacitance of the saturation region of the differential pair transistor, and when the current source switch 212 is opened, the output capacitance of the standard cell 131 is the gate-drain capacitance of the cut-off region of the differential pair transistor. The gate-drain capacitance of the saturation region and the cut-off region may differ by 30% -100% according to the characteristics of the transistor. That is, the gate-drain capacitance of the differential pair transistor coupled to the output will change as its weight code value changes, thereby affecting the current, thereby causing the phase of the output clock to not adjust linearly with the weight code value as expected.
Fig. 4 shows a schematic circuit configuration of another interpolator 130. Unlike fig. 2, the interpolator 130 shown in fig. 4 adjusts the current levels of the four differential pairs of tubes through the current controller 133. The output current of the current controller 133 may be linearly changed according to the control signal (PI ctrl) of the interpolator 130, so as to adjust weights of currents flowing through the four pairs of differential switching tubes, so as to control weights of the clock CLK0, the clock CLK90, the clock CLK180 and the clock CLK270 in the output clocks, and the phase of the output clocks may output any phase between 0 ° and 360 °, thereby realizing the function of phase adjustment of the output clocks.
Unlike fig. 2, the differential pair of the interpolator 130 in fig. 4 basically operates in the saturation region, so that the problem of phase nonlinearity of the output clock of the interpolator 130 caused by the change of the gate-drain capacitance can be weakened or even eliminated. But since the transconductance calculation formula of the transistors in the differential pair can be expressed as: Where g m is transconductance, μ n is charge mobility, C ox is gate capacitance, W is channel width of the transistor, L is gate length of the transistor, and I ds is source leakage current of the transistor. Therefore, it is not easy to see that although the output current of the current controller 133 varies linearly with the control signal of the interpolator 130, the transconductance of the transistor cannot vary linearly with the output current of the current controller 133, so that the output current of the transistor has a problem of nonlinearity, and thus the phase of the output clock of the interpolator 130 cannot be adjusted linearly with the control signal.
As shown in fig. 5, an embodiment of the present application provides an electronic device 300, which includes a device housing (not shown in the drawings) and a chip system 310, and part or all of the chip system 310 is disposed in the device housing. The chip system 310 may include a printed circuit board (printed circuit boards, PCB) (not shown) and a processing chip 311, where the processing chip 311 is disposed on the PCB. In some examples, processing chip 311 is an interface chip, e.g., a serializer/deserializer (SerDes) interface chip. In other embodiments, the processing chip 311 is a clock processing chip, such as a phase-locked loop chip.
As shown in fig. 6, the processing chip 311 may include a clock source 400 and a phase interpolation circuit 100. The clock source 400 may output clocks of any even number of different phases equal to or greater than 4, and the phase difference between two clocks of any adjacent phases may be equal. That is, the clock source 400 may output clocks of 4 different phases including, but not limited to, 0 °, 90 °,180 °, and 270 °, and 8 different phases including, but not limited to, 0 °, 45 °, 90 °, 135 °,180 °, 225 °, 270 °, and 315 °, and the present application is not limited thereto.
The phase interpolation circuit 100 may include an interpolator 130 and a bias circuit 150. In some implementations, the interpolator 130 may be provided with one or more. When the interpolator 130 sets one, the processing chip 311 may implement a one-way clock output. As shown in fig. 7, when the interpolators 130 are provided in plural, the input terminals of the interpolators 130 are connected in parallel, and the processing chip 311 can realize multiplexing output.
The interpolator 130 may include at least two clock weight generation circuits, each having an input for inputting a set of differential clocks. The embodiment of the present application is further described by taking the example that the clock source 400 outputs clocks of different phases of 0 °,90 °, 180 ° and 270 °, and the interpolator 130 includes two clock weight generating circuits. As shown in fig. 8, the two clock weight generating circuits are a first clock Zhong Quanchong generating circuit 134 and a second clock weight generating circuit 135, respectively. An input of the first time Zhong Quanchong generation circuit 134 and an input of the second clock weight generation circuit 135 are coupled to the clock source 400, respectively. Illustratively, the input of the first time Zhong Quanchong generating circuit 134 is used to input a first differential clock (i.e., clock P+ (clock at 0 phase) and clock P- (clock at 180 phase) as shown in FIG. 8), that is, the positive input of the first time Zhong Quanchong generating circuit 134 is used to input clock P+, and the negative input of the first time Zhong Quanchong generating circuit 134 is used to input clock P-. The input terminal of the second clock weight generating circuit 135 is used for inputting a second differential clock (i.e., clock q+ (clock of 90 ° phase) and clock Q- (clock of 270 ° phase) shown in fig. 8), that is, the positive input terminal of the second clock weight generating circuit 135 is used for inputting clock q+, and the negative input terminal of the second clock weight generating circuit 135 is used for inputting clock Q-. The first time Zhong Quanchong generation circuit 134 and the second clock weight generation circuit 135 are also coupled to the bias circuit 150, respectively, to receive the bias voltage generated by the bias circuit 150. The output terminal of the first time Zhong Quanchong generating circuit 134 is coupled to the output terminal of the second clock weight generating circuit 135 to output the output clocks with various phases.
As shown in fig. 8, in some embodiments, the clock weight generation circuit 134 and the second clock weight generation circuit 135 may include one interpolation circuit 500. The positive input of the interpolation circuit 500 serves as the positive input of the first time Zhong Quanchong generation circuit 134 (or the second clock weight generation circuit 135), the negative input of the interpolation circuit 500 serves as the negative input of the first time Zhong Quanchong generation circuit 134 (or the second clock weight generation circuit 135), and the output of the interpolation circuit 500 serves as the output of the first time Zhong Quanchong generation circuit 134 (or the second clock weight generation circuit 135). So that either the first time Zhong Quanchong generation circuit 134 or the second clock weight generation circuit 135 is single ended, i.e., the output clock of the interpolator 130 shown in fig. 8 is single ended.
As shown in fig. 9, the interpolation circuit 500 may include a first transistor 510, a second transistor 520, a positive bias transistor 530, and a negative bias transistor 540. The first transistor 510, the second transistor 520, the positive bias transistor 530, and the negative bias transistor 540 are N-type transistors, for example, N-type metal-oxide-semiconductor (NMOS). A first terminal of the first transistor 510 is for inputting a supply voltage, a second terminal of the first transistor 510 is coupled to a first terminal of the positive bias transistor 530, and a second terminal of the positive bias transistor 530 is grounded. A first terminal of the second transistor 520 is for inputting a supply voltage, a second terminal of the second transistor 520 is coupled to a first terminal of the negative bias transistor 540, and a second terminal of the negative bias transistor 540 is grounded.
A control terminal of the positive bias transistor 530 is coupled to a positive output terminal of the bias circuit 150 for inputting the positive bias voltage V BN+, and a control terminal of the negative bias transistor 540 is coupled to a negative output terminal of the bias circuit 150 for inputting the negative bias voltage V BN-. The control terminal of the first transistor 510 and the control terminal of the second transistor 520 are coupled to the output terminal of the clock source 400, respectively, for inputting a set of differential clocks (e.g., clock P+ and clock P-, or clock Q+ and clock Q-). In some examples, the control terminal of the first transistor 510 serves as a positive input terminal of the first clock Zhong Quanchong generation circuit 134 (or the second clock weight generation circuit 135) for inputting the clock p+ (or the clock q+), and the control terminal of the second transistor 520 serves as a negative input terminal of the first clock Zhong Quanchong generation circuit 134 (or the second clock weight generation circuit 135) for inputting the clock P- (or the clock Q-). A second terminal of the first transistor 510 and a second terminal of the second transistor 520 are coupled as an output terminal of the interpolation circuit 500. The output expression function of the interpolation circuit 500 can be expressed as: Where VN I+ is the clock P+ (or, the clock Q+), and V TH is the on threshold voltage of the transistor.
As can be seen from the output expression function of the interpolation circuit 500, the embodiment of the present application only needs to control the sum of the positive bias voltage and the negative bias voltage (i.e. V BN++VBN-) output by the bias circuit 150 to be a constant value, so that the output of the interpolation circuit 500 will be proportional to the difference between the positive bias voltage and the negative bias voltage (i.e. V BN+-VBN-). That is, the embodiment of the present application can realize linearization of the output clock of the interpolation circuit 500 by controlling the positive bias voltage and the negative bias voltage output from the bias circuit 150. Thereby realizing linearization of the output of the first time Zhong Quanchong generation circuit 134 and the second clock weight generation circuit 135, and further improving the linearity of the phase of the output clock of the interpolator 130.
As shown in fig. 10, in other embodiments, the first time Zhong Quanchong generation circuit 134 or the second clock weight generation circuit 135 each includes two interpolation circuits 500, the two interpolation circuits 500 being a positive interpolation circuit 500A and a negative interpolation circuit 500B, respectively. As shown in fig. 11, in the positive interpolation circuit 500A, the control terminal of the first transistor 510 is used as the positive input terminal of the first time Zhong Quanchong generating circuit 134 (or the second clock weight generating circuit 135), the control terminal of the second transistor 520 is used as the negative input terminal of the first time Zhong Quanchong generating circuit 134 (or the second clock weight generating circuit 135), and the second terminals of the first transistor 510 and the second transistor 520 are coupled and used as the positive output terminal of the first time Zhong Quanchong generating circuit 134 (or the second clock weight generating circuit 135). As shown in fig. 12, in the negative interpolation circuit 500B, the control terminal of the first transistor 510 is used as the negative input terminal of the first time Zhong Quanchong generating circuit 134 (or the second clock weight generating circuit 135), the control terminal of the second transistor 520 is used as the positive input terminal of the first time Zhong Quanchong generating circuit 134 (or the second clock weight generating circuit 135), and the second terminal of the first transistor 510 and the second terminal of the second transistor 520 are coupled and then used as the negative output terminal of the first time Zhong Quanchong generating circuit 134 (or the second clock weight generating circuit 135). The output expression function of the negative interpolation circuit 500B can be expressed as: The positive output of the first time Zhong Quanchong generation circuit 134 is coupled to the positive output of the second clock weight generation circuit 135, and the negative output of the first time Zhong Quanchong generation circuit 134 is coupled to the negative output of the second clock weight generation circuit 135. So that the first time Zhong Quanchong generation circuit 134 or the second clock weight generation circuit 135 outputs the differential clock, that is, the interpolator 130 shown in fig. 10 can realize the output of the differential clock.
Due to the defect of the process, the first transistor 510 and the second transistor 520 have a deviation of threshold voltages, which may cause the first transistor 510 and the second transistor 520 to be turned on to have a deviation. Further, as shown in fig. 11 and 12, in some embodiments, the interpolation circuit 500 (i.e., the positive interpolation circuit 500A or the negative interpolation circuit 500B) may further include a fourth capacitor 550 and a fifth capacitor 560, a first terminal of the fourth capacitor 550 being coupled to the second terminal of the first transistor 510, a second terminal of the fourth capacitor 550 being coupled to the first terminal of the fifth capacitor 560, a second terminal of the fifth capacitor 560 being coupled to the second terminal of the second transistor 520, and a coupling point of the fourth capacitor 550 and the fifth capacitor 560 being the output terminal of the interpolation circuit 500. The second end of the first transistor 510 and the second end of the second transistor 520 are not coupled through direct current, but coupled through the fourth capacitor 550 and the fifth capacitor 560, and the threshold voltage deviation of the first transistor 510 and the second transistor 520 cannot affect the output of the interpolation circuit 500 by utilizing the characteristic of direct current open circuit of the capacitors, so that the defect of the first transistor 510 and the second transistor 520 in process manufacturing is optimized, and the linearity of the output of the interpolator 130 is ensured.
Further, in some embodiments, the interpolator 130 may further include a first fully differential amplifier 136 and a second fully differential amplifier 137. As shown in fig. 13, the output of the first time Zhong Quanchong generation circuit 134 is coupled to the input of the first fully differential amplifier 136, the output of the second clock weight generation circuit 135 is coupled to the input of the second fully differential amplifier 137, and the output of the first fully differential amplifier 136 is coupled to the output of the second fully differential amplifier 137.
As shown in fig. 14, the bias circuit 150 includes two code value conversion circuits, which are a first code value conversion circuit 151 and a second code value conversion circuit 152, respectively. The first code value conversion circuit 151 is coupled to the first time Zhong Quanchong generation circuit 134, and the second code value conversion circuit 152 is coupled to the second clock weight generation circuit 135.
As shown in fig. 15, the code value conversion circuit includes a first resistor 610, a second resistor 620, a phase switch 630, and a power supply circuit 640. Wherein the first end of the phase switch 630 is configured to be coupled to a first power supply 650, and in some embodiments, the first power supply 650 is a first current source, and the output current of the first current source is I 1. A second terminal of the phase switch 630 is coupled to a first terminal of the first resistor 610 and a third terminal of the phase switch 630 is coupled to a second terminal of the second resistor 620. A first end of the power supply circuit 640 is coupled to a first end of the first resistor 610, a second end of the first resistor 610 is grounded to a first end of the second resistor 620, and a second end of the power supply circuit 640 is coupled to a second end of the second resistor 620. In some embodiments, the power supply circuit 640 may include a plurality of weight switches 641, and the power supply circuit 640 includes N weight switches 641, where N is an integer greater than 1, as an example. The N weight switches 641 correspond to N second power supplies 642, and in some embodiments, the second power supplies 642 are second current sources having an output current I 2 and an output current N times the output current of a single second current source, i.e., I 1＝N×I2. The first terminal of each weight switch 641 is configured to be coupled to a corresponding second current source, the second terminal of each weight switch 641 is coupled to a first terminal of the power supply circuit 640, and the third terminal of each weight switch 641 is coupled to a second terminal of the power supply circuit 640. The first end of the first resistor 610 serves as a positive output terminal of the first code value converting circuit 151 (or the second code value converting circuit 152) and a control terminal of the positive bias transistor 530 in the first time Zhong Quanchong generating circuit 134 (or the second clock weight generating circuit 135), and the second end of the second resistor 620 serves as a negative output terminal of the first code value converting circuit 151 (or the second code value converting circuit 152) and a control terminal of the negative bias transistor 530 in the first time Zhong Quanchong generating circuit 134 (or the second clock weight generating circuit 135).
Because the internal resistance of the current source is large relative to the load impedance, the load impedance fluctuation does not change the magnitude of the current output by the current source. That is, in the embodiment of the present application, the output current of the first power supply 650 and the sum of the output current of the first terminal and the output current of the second terminal of the power supply circuit 640 are unchanged. So that the sum of the currents flowing through the first resistor 610 and the second resistor 620 is constant, i.e., V BN++VBN- is constant.
In some implementations, the code value conversion circuit further includes a bias transistor 660. As shown in fig. 15, the bias transistor 660 is an NMOS transistor, a first terminal of the bias transistor 660 is coupled to the coupling point of the first resistor 610 and the second resistor 620, a second terminal of the bias transistor 660 is coupled, and a control terminal of the bias transistor 660 is coupled to the first terminal of the bias transistor 660. In an embodiment of the present application, the bias transistor 660 may provide bias current for turning on the positive bias transistor and the negative bias transistor in the interpolation circuit 500. In addition, the present embodiment can alleviate or even overcome the problem of glitch of the output clock of the interpolator 130 when the phase code value and the weight code value are switched through the rc filter composed of the parasitic capacitances of the first resistor 610, the second resistor 620 and the bias transistor 660. It should be appreciated that in other embodiments, the parasitic capacitance of bias transistor 660 may be replaced with a capacitor.
As shown in fig. 14, the phase code value P is input to the first code value conversion circuit 151, and the phase code value Q is input to the second code value conversion circuit 152. In some embodiments, the phase code value controls the conduction of phase switch 630. Fig. 16 shows a phase correspondence relationship between the phase code value and the selected clock, and as shown in fig. 15 and 16, when the phase code value p=1, the first terminal and the second terminal of the phase switch 630 in the first code value conversion circuit 151 are turned on, the current I 1 output by the first current source is input to the first resistor 610, so that V BN+-VBN- >0, and the first code value conversion circuit 151 selects the clock p+ (i.e., the clock of 0 ° phase). When the phase code value p=0, the first terminal of the phase switch 630 in the first code value conversion circuit 151 is turned on with the third terminal, and the current I 1 output by the first current source is input to the second resistor 620, so that V BN+-VBN- <0, the first code value conversion circuit 151 selects the clock P- (i.e., the clock of 180 ° phase). Likewise, when the phase code value q=1, the second code value conversion circuit 152 selects the clock q+ (i.e., a clock of 90 ° phase), and when the phase code value q=0, the second code value conversion circuit 152 selects the clock Q- (i.e., a clock of 270 ° phase).
In some embodiments, the weight code value controls the conduction of the weight switch 641. As shown in fig. 15, the weight code value is input to the first code value conversion circuit 151 to control the weight of the clock p+ (or the clock P-), and the weight code value is inverted and input to the second code value conversion circuit 152 to control the weight of the clock q+ (or the clock Q-). When the first terminal and the second terminal of the weight switch 641 are turned on, the current I 2 outputted by the second current source is inputted to the first resistor 610 from the first terminal of the power supply circuit 640 through the weight transistor, and when the first terminal and the third terminal of the weight switch 641 are turned on, the current I 2 outputted by the second current source is inputted to the first resistor 610 from the second terminal of the power supply circuit 640 through the weight transistor. In some examples, when the weight code value is "110101", the first, second, fourth, and sixth weight switches in the first code value conversion circuit 151 are turned on at the first and second ends, and the third and fifth weight switches are turned on at the first and third ends. The weight code value is "001010" after being inverted, so that the first and second ends of the third weight switch and the fifth weight switch in the second code value converting circuit 152 are turned on, and the first and third ends of the first weight switch, the second weight switch, the fourth weight switch and the sixth weight switch are turned on.
That is, the code value converting circuit adjusts the current flowing through the first resistor 610 and the second resistor 620 through the phase switch 630 and the weight switch 641, thereby adjusting the value of V BN+-VBN- outputted from the bias circuit 150 to select a clock and adjust the weight of the selected clock.
In some examples, a clock with a 0 ° phase may be described as V (t), a clock with a 90 ° phase may be described as V (t+t ph), and an output clock may be described as V (t+Δt). Wherein t ph is the time difference corresponding to the phase difference of 0 ° -90 °, and Δt is the expected phase difference. The weight of the clock with 0 DEG phase is K P, and the weight of the clock with 90 DEG phase is K Q, the output clock after weighted normalization can be expressed as:
V(t+Δt)=KP×V(t)+KQ×V(t+tph)
wherein, since K P+KQ =1, after finishing, it is obtained:
KP×(V(t+Δt)-V(t))＝KQ×(V(t+tph)-V(t+Δt))
the above is to be satisfied at any time, and K P and K Q are necessarily not sufficiently considered to be constants, and:
That is, in order to secure linearity of the output clock phase of the interpolator 130, the differentiation of the input interpolator 130 clock over time needs to be constant. Therefore, as shown in fig. 17, the processing chip 311 may further include an integrator 120, and the clocks of the plurality of phases may be shaped into triangular wave clocks by the integrator 120 and then input to the interpolator 130.
In some embodiments, as shown in fig. 18, integrator 120 may include two integrating circuits. The two integrating circuits are a first integrating circuit 121 and a second integrating circuit 122, respectively. The positive input of the first integrating circuit 121 is coupled to a positive output of the clock source 400 for inputting the clock a +, and the negative input of the first integrating circuit 121 is coupled to a negative output of the clock source 400 for inputting the clock a- (clock a + and clock a-are square wave clocks 180 deg. out of phase). The positive output of the first integrating circuit 121 is coupled to the positive input of the first time Zhong Quanchong generating circuit 134 for outputting the clock P +, and the negative output of the first integrating circuit 121 is coupled to the negative input of the first time Zhong Quanchong generating circuit 134 for outputting the clock P- (clock P + and clock P-are triangle wave clocks 180 deg. out of phase). The positive input of the second integrating circuit 122 is coupled to the other positive output of the clock source 400 for inputting the clock B +, and the negative input of the second integrating circuit 122 is coupled to the other negative output of the clock source 400 for inputting the clock B- (clock B + and clock B are square wave clocks 180 deg. out of phase). The positive output of the second integrating circuit 122 is coupled to the positive input of the second clock weight generating circuit 134 for outputting the clock Q +, and the negative output of the second integrating circuit 122 is coupled to the negative input of the second clock weight generating circuit 134 for outputting the clock Q- (clock Q + and clock Q-are triangle wave clocks 180 ° out of phase).
As shown in fig. 19, the integrating circuit includes a pull-down current source 730, a third transistor 710, and a fourth transistor 720, wherein the third transistor 710 and the fourth transistor 720 are NMOS transistors. The first terminal of the third transistor 710 and the first terminal of the fourth transistor 720 are respectively coupled to a power supply, the second controlled terminal of the third transistor 710 is coupled to the positive terminal of the pull-down current source 730, the second controlled terminal of the fourth transistor 720 is coupled to the positive terminal of the pull-down current source 730, and the negative terminal of the pull-down current source 730 is grounded. The control terminal of the third transistor 710 is the positive input terminal of the integrating circuit and the control terminal of the fourth transistor 720 is the negative input terminal of the integrating circuit. The first terminal of the third transistor 710 serves as a negative output terminal of the integrating circuit and the first terminal of the fourth transistor 720 serves as a positive output terminal of the integrating circuit.
Since the parasitic capacitance Cpa exists between the second terminal of the third transistor 710 and the second terminal of the fourth transistor 720 in the integrating circuit and the ground, the parasitic capacitance Cpa may slow down the voltage response speed at the coupling point between the second terminal of the third transistor 710 and the second terminal of the fourth transistor 720, and the voltage at the coupling point between the second terminal of the third transistor 710 and the second terminal of the fourth transistor 720 is higher when any one of the transistors is turned on, which makes the pull-down current from the output terminal of the integrating circuit higher than the preset current, and the current will not change back to the preset value until the voltage at the coupling point between the second terminal of the third transistor 710 and the second terminal of the fourth transistor 720 is completely established. As shown in fig. 20, the triangular waveform output by the output end of the integrating circuit is distorted by the influence of the pull-down current of the output end of the integrating circuit in a short time, so that the linearity of the whole phase interpolation circuit 100 is directly affected.
Therefore, in order to reduce distortion of the triangular waveform output from the output end of the integrating circuit, in the embodiment of the present application, the pull-down current source 730 in the integrating circuit includes a third current source 731 and a fourth current source 732, the second controlled end of the third transistor 710 is coupled to the positive end of the third current source 731, the second controlled end of the fourth transistor 720 is coupled to the positive end of the fourth current source 732, and the negative end of the third current source 731 and the negative end of the fourth current source 732 are grounded. And, the integrating circuit further includes a voltage accelerating circuit 740. As shown in fig. 21, the voltage acceleration circuit 740 includes a first capacitor 741, a second capacitor 742, a fifth current source 745, a sixth current source 746, a fifth transistor 743, and a sixth transistor 744.
The fifth transistor 743 and the sixth transistor 744 are NMOS transistors. A first terminal of the fifth transistor 743 is for inputting a supply voltage, a second terminal of the fifth transistor 743 is coupled to ground through the fifth current source 745, a first terminal of the first capacitor 741 is coupled to the second terminal of the fifth transistor 743, and a second terminal of the first capacitor 741 is coupled to the second terminal of the third transistor 710. A first terminal of a sixth transistor 744 is for inputting a supply voltage, a second terminal of the sixth transistor 744 is coupled to ground via a sixth current source 746, a first terminal of a second capacitor 742 is coupled to the second terminal of the sixth transistor 744, and a second terminal of the second capacitor 742 is coupled to the second terminal of the fourth transistor 720. The control terminal of the fifth transistor 743 is coupled to the control terminal of the fourth transistor 720, that is, the control terminal of the fifth transistor 743 may serve as a negative input terminal of the integrating circuit. The control terminal of the sixth transistor 744 is coupled to the control terminal of the third transistor 710, that is, the control terminal of the sixth transistor 744 may be used as the positive input terminal of the integrating circuit. According to the embodiment of the application, the voltage accelerating circuit 740 is arranged, and the voltage accelerating circuit 740 is respectively coupled with the second ends of the third transistor 710 and the fourth transistor 720, so that the voltage establishing speed of the second ends of the third transistor 710 and the fourth transistor 720 is improved, the influence of parasitic capacitance Cpa on the output of the integrating circuit is weakened, the defect of nonideal of the integrating circuit is further optimized, the influence of waveform distortion on the linearity of the interpolator 130 is reduced, and the linearity of the output clock phase of the interpolator 130 is further improved.
To ensure that the common mode voltage output by the positive and negative outputs of the integrating circuit is unchanged, as shown in fig. 21, in some embodiments, the integrating circuit further includes a seventh transistor 750, an eighth transistor 760, and a common mode feedback circuit 770. The seventh transistor 750 and the eighth transistor 760 are P-type transistors, for example, P-type metal-oxide-semiconductor (PMOS). A first terminal of the third transistor 710 is coupled to a first terminal of the seventh transistor 750, a second terminal of the seventh transistor 750 is for inputting a supply voltage, a first terminal of the fourth transistor 720 is coupled to a first terminal of the eighth transistor 760, and a second terminal of the eighth transistor 760 is for inputting the supply voltage. A first input of the common mode feedback circuit 770 is coupled to a first terminal of the third transistor 710, a second input of the common mode feedback circuit 770 is coupled to a first terminal of the fourth transistor 720, and an output of the common mode feedback circuit 770 is coupled to a control terminal of the seventh transistor 750 and to a control terminal of the eighth transistor 760, respectively. The voltage output by the negative output terminal (i.e., the first terminal of the third transistor 710) of the common-mode feedback circuit 770 and the voltage output by the positive output terminal (i.e., the first terminal of the fourth transistor 720) of the integration circuit control the turn-on degree of the seventh transistor 750 and the eighth transistor 760, and thus control the turn-on currents of the seventh transistor 750 and the eighth transistor 760 to be constant, so as to ensure that the common-mode voltage output by the positive output terminal and the negative output terminal of the integration circuit is constant.
Because the internal resistance of the current source is large relative to the load impedance, the load impedance fluctuation does not change the magnitude of the current output by the current source. Thus, as shown in fig. 22, in other embodiments, the power supply coupled to the first terminal of the third transistor 710 is a current source, and the power supply coupled to the first terminal of the fourth transistor 720 is a current source.
As shown in fig. 23, in some embodiments, the integrating circuit further includes a third capacitor 780, a first terminal of the third capacitor 780 coupled to a second terminal of the third transistor 710, a second terminal of the third transistor 710 coupled to a second terminal of the fourth transistor 720. Due to the defect of the process, the third transistor 710 and the fourth transistor 720 have a deviation of threshold voltages, which may cause the third transistor 710 and the fourth transistor 720 to be turned on to have a deviation. In the embodiment of the application, the second end of the third transistor 710 and the second end of the fourth transistor 720 are not coupled through the third capacitor 780, and the threshold voltage deviation cannot affect the output of the integrating circuit due to the characteristic of the direct current open circuit of the capacitor, so that the defects of the third transistor 710 and the fourth transistor 720 in the process manufacturing are optimized.
Further, in some embodiments, the processing chip 311 further includes an output amplifier 140. As shown in fig. 24, an input of the output amplifier 140 is coupled to an output of the interpolator 130. In the embodiment of the application, the output amplifier 140 amplifies the clock output by the interpolator 130 and outputs the amplified clock to the subsequent-stage circuit.
The embodiment of the application also provides a processing chip. As shown in fig. 25, the processing chip 311 includes a clock source 400, an integrator 120, and an interpolator 130, and the integrator 120 includes at least two integrating circuits. As shown in fig. 18, in some embodiments, the integrator 120 includes a first integrating circuit 121 and a second integrating circuit 122, an input of the first integrating circuit 121 and an input of the second integrating circuit 122 are respectively connected to an output of the clock source 400, and an output of the first integrating circuit 121 and an output of the second integrating circuit 122 are respectively coupled to an input of the interpolator 130. As shown in fig. 21, the integrating circuit includes a first capacitor 741, a second capacitor 742, a third current source 731, a fourth current source 732, a fifth current source 745, a sixth current source 746, a third transistor 710, a fourth transistor 720, a fifth transistor 743, and a sixth transistor 744. A first terminal of the third transistor 710 is for coupling to a supply source, a second controlled terminal of the third transistor 710 is coupled to ground via a third current source 731, a first terminal of the fourth transistor 720 is for coupling to the supply source, and a second controlled terminal of the fourth transistor 720 is coupled to ground via a fourth current source 732. A first terminal of the fifth transistor 743 is for inputting a supply voltage, a second terminal of the fifth transistor 743 is coupled to ground through the fifth current source 745, a first terminal of the first capacitor 741 is coupled to the second terminal of the fifth transistor 743, and a second terminal of the first capacitor 741 is coupled to the second terminal of the third transistor 710. A first terminal of a sixth transistor 744 is for inputting a supply voltage, a second terminal of the sixth transistor 744 is coupled to ground via a sixth current 746 source, a first terminal of a second capacitor 742 is coupled to the second terminal of the sixth transistor 744, and a second terminal of the second capacitor 742 is coupled to the second terminal of the fourth transistor 720.
The control terminal of the third transistor 710 is coupled to the positive output terminal of the clock source 400 as the positive input terminal of the corresponding integrating circuit, and the control terminal of the fourth transistor 720 is coupled to the negative output terminal of the clock source 400 as the negative input terminal of the corresponding integrating circuit. The control terminal of the fifth transistor 743 is coupled to the control terminal of the fourth transistor 720, that is, the control terminal of the fifth transistor 743 may serve as a negative input terminal of the corresponding integrating circuit. The control terminal of the sixth transistor 744 is coupled to the control terminal of the third transistor 710, that is, the control terminal of the sixth transistor 744 may serve as a positive input terminal of the corresponding integrating circuit.
As shown in fig. 23, in some embodiments, the integrating circuit further includes a third capacitor 780, a first terminal of the third capacitor 780 coupled to a second terminal of the third transistor 710, a second terminal of the third transistor 710 coupled to a second terminal of the fourth transistor 720.
It should be understood that in the embodiment of the present application, the NOMS tube may be replaced by a PMOS tube, and in the embodiment of the present application, the PMOS tube may also be replaced by a NOMS tube. As an alternative embodiment of the integrating circuit, as shown in fig. 26, the integrating circuit may use a PMOS transistor and an NMOS transistor at the same time. As shown in fig. 26, the integrating circuit includes a first PMOS transistor 791, a second PMOS transistor 792, a third PMOS transistor 793, a fourth PMOS transistor 794, a first NMOS transistor 795, a second NMOS transistor 796, a third NMOS transistor 797, and a fourth NMOS transistor 798. The source of the first PMOS transistor 791 is coupled to the source of the second PMOS transistor 792 through a capacitor, and the source of the third PMOS transistor 793 is coupled to the source of the fourth PMOS transistor 794 through a capacitor. The source of the first NMOS tube 795 is coupled to the source of the second NMOS tube 796 through a capacitor, and the source of the third NMOS tube 797 is coupled to the source of the fourth NMOS tube 798 through a capacitor. The drain of the second PMOS transistor 792 and the drain of the first NMOS transistor 795 serve as the negative output terminal of the integrating circuit, and the drain of the fourth PMOS transistor 794 and the drain of the third NMOS transistor 797 serve as the positive output terminal of the integrating circuit. The gate of the second PMOS transistor 792, the gate of the third PMOS transistor 793, the gate of the first NMOS transistor 795, and the gate of the fourth NMOS transistor 798 are used as positive inputs of the integrating circuit, and the gate of the first PMOS transistor 791, the gate of the fourth PMOS transistor 794, the gate of the second NMOS transistor 796, and the gate of the third NMOS transistor 797 are used as negative inputs of the integrating circuit.
That is, the embodiment of the present application does not limit the types of transistors, and all circuits that are equivalently replaced based on the embodiment of the present application belong to the protection scope of the present application.
The embodiment of the application provides a processing chip, a chip system and electronic equipment. The processing chip comprises a clock source, an interpolator and a biasing circuit. The interpolator includes at least two clock weight generation circuits, each including an interpolation circuit. Each interpolation circuit comprises a first transistor, a second transistor, a positive bias transistor and a negative bias transistor, wherein the first end of the first transistor and the first end of the second transistor are respectively used for inputting a power supply voltage, the second end of the first transistor is coupled with the first end of the positive bias transistor, the second end of the positive bias transistor is grounded, the second end of the second transistor is coupled with the first end of the negative bias transistor, and the second end of the negative bias transistor is grounded. The control terminal of the positive bias transistor is coupled to the positive output terminal of the bias circuit, and the control terminal of the negative bias transistor is coupled to the negative output terminal of the bias circuit. The control end of the first transistor and the control end of the second transistor are used as the input ends of the corresponding clock weight generating circuits to be respectively coupled with the output ends of the clock sources, and the second end of the first transistor and the second end of the second transistor are used as the output ends of the corresponding clock weight generating circuits after being coupled, and the output ends of at least two clock weight generating circuits are coupled. In the embodiment of the application, the clock source can output clocks with a plurality of phases, the bias circuit can output positive bias voltage V BN+ and negative bias voltage V BN- according to the weight code value and the phase code value, and the interpolator comprises at least two clock weight generating circuits, and the output ends of the at least two clock weight generating circuits are coupled, so that the weighted output of the clock phases is realized. The linearity of the phase of the output clock of the clock weight generation circuit directly affects the performance of the processing chip. in an embodiment of the present application, each clock weight generation circuit includes an interpolation circuit in which a control terminal of a first transistor and a control terminal of a second transistor are coupled to an output terminal of a clock source, respectively, for receiving a set of differential clocks (e.g., V IN+ and V IN-; where V IN+ and V IN- are 180 ° out of phase) from the clock source. The control terminal of the positive bias transistor in the interpolation circuit is coupled to the positive output terminal of the bias circuit for receiving the positive bias voltage V BN+. The interpolation circuit is coupled to the negative output of the bias circuit at the control terminal of the negative bias transistor for receiving a negative bias voltage V BN-. In the embodiment of the application, only V BN++VBN- output by the bias circuit is required to be controlled to be a constant value, so that the output of the interpolation circuit is in direct proportion to V BN+-VBN-. the bias circuit provided by the embodiment of the application realizes the control of the output value of the interpolation circuit, so that the clock weight generating circuit can realize the linear output of small signals, and further the linearity of the phase of the output clock of the interpolator is improved.
In the several embodiments provided in the present application, it should be understood that the disclosed chip, chip system and electronic device may be implemented in other manners. For example, the above-described device embodiments are merely illustrative, e.g., the division of the modules is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple modules or components may be combined or integrated into another device, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be through some interface, indirect coupling or communication connection of devices or modules, electrical, mechanical, or other form.
The modules described as separate components may or may not be physically separate, and components shown as modules may or may not be physically separate, i.e., may be located in one device, or may be distributed over multiple devices. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional module in the embodiments of the present application may be integrated in one device, or each module may exist alone physically, or two or more modules may be integrated in one device.
The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (18)

1.一种处理芯片，其特征在于，包括时钟源、插值器和偏置电路；所述插值器包括至少两个时钟权重产生电路，每个所述时钟权重产生电路包括插值电路；每个所述插值电路包括第一晶体管、第二晶体管、正偏置晶体管和负偏置晶体管；其中，1. A processing chip, comprising a clock source, an interpolator, and a bias circuit; the interpolator comprising at least two clock weight generation circuits, each of which comprises an interpolation circuit; each of which comprises a first transistor, a second transistor, a positive bias transistor, and a negative bias transistor; wherein: 所述第一晶体管的第一端和所述第二晶体管的第一端分别用于输入供电电压；所述第一晶体管的第二端与所述正偏置晶体管的第一端耦合，所述正偏置晶体管的第二端接地；所述第二晶体管的第二端与所述负偏置晶体管的第一端耦合；所述负偏置晶体管的第二端接地；The first terminal of the first transistor and the first terminal of the second transistor are respectively used to input a power supply voltage; the second terminal of the first transistor is coupled to the first terminal of the positive bias transistor, and the second terminal of the positive bias transistor is grounded; the second terminal of the second transistor is coupled to the first terminal of the negative bias transistor; and the second terminal of the negative bias transistor is grounded; 所述正偏置晶体管的控制端与所述偏置电路的正输出端耦合，所述负偏置晶体管的控制端与所述偏置电路的负输出端耦合；The control terminal of the positive bias transistor is coupled to the positive output terminal of the bias circuit, and the control terminal of the negative bias transistor is coupled to the negative output terminal of the bias circuit; 所述第一晶体管的控制端和所述第二晶体管的控制端作为对应的所述时钟权重产生电路的输入端分别与所述时钟源的输出端耦合；所述第一晶体管的第二端和所述第二晶体管的第二端耦合后作为对应的所述时钟权重产生电路的输出端，所述至少两个时钟权重产生电路的输出端之间耦合。The control end of the first transistor and the control end of the second transistor are respectively coupled to the output end of the clock source as the input end of the corresponding clock weight generating circuit; the second end of the first transistor and the second end of the second transistor are coupled as the output end of the corresponding clock weight generating circuit, and the output ends of the at least two clock weight generating circuits are coupled. 2.根据权利要求1所述的处理芯片，其特征在于，每个所述时钟权重产生电路包括两个所述插值电路，两个所述插值电路分别为正插值电路和负插值电路，对于每个所述时钟权重产生电路：2. The processing chip according to claim 1, wherein each of the clock weight generation circuits comprises two interpolation circuits, the two interpolation circuits being a positive interpolation circuit and a negative interpolation circuit, and for each of the clock weight generation circuits: 在所述正插值电路中，所述第一晶体管的控制端作为对应的所述时钟权重产生电路的正输入端与所述时钟源的正输出端耦合，所述第二晶体管的控制端作为对应的所述时钟权重产生电路的负输入端与所述时钟源的负输出端耦合，所述第一晶体管的第二端和所述第二晶体管的第二端耦合后作为对应的所述时钟权重产生电路的正输出端；In the positive interpolation circuit, the control terminal of the first transistor is coupled to the positive output terminal of the clock source as the positive input terminal of the corresponding clock weight generation circuit, the control terminal of the second transistor is coupled to the negative output terminal of the clock source as the negative input terminal of the corresponding clock weight generation circuit, and the second terminal of the first transistor and the second terminal of the second transistor are coupled to serve as the positive output terminal of the corresponding clock weight generation circuit; 在所述负插值电路中，所述第一晶体管的控制端作为对应的所述时钟权重产生电路的负输入端与所述时钟源的负输出端耦合，所述第二晶体管的控制端作为对应的所述时钟权重产生电路的正输入端与所述时钟源的正输出端耦合，所述第一晶体管的第二端和所述第二晶体管的第二端耦合后作为对应的所述时钟权重产生电路的负输出端；In the negative interpolation circuit, the control terminal of the first transistor is coupled to the negative output terminal of the clock source as the negative input terminal of the corresponding clock weight generation circuit, the control terminal of the second transistor is coupled to the positive output terminal of the clock source as the positive input terminal of the corresponding clock weight generation circuit, and the second terminal of the first transistor and the second terminal of the second transistor are coupled to serve as the negative output terminal of the corresponding clock weight generation circuit; 所述至少两个时钟权重产生电路的正输出端之间耦合，所述至少两个时钟权重产生电路的负输出端之间耦合。The positive output terminals of the at least two clock weight generating circuits are coupled to each other, and the negative output terminals of the at least two clock weight generating circuits are coupled to each other. 3.根据权利要求1或2所述的处理芯片，其特征在于，所述偏置电路至少两个码值转换电路，所述至少两个码值转换电路与所述至少两个时钟权重产生电路一一对应；所述码值转换电路包括第一电阻器、第二电阻器、相位开关和供电电路；其中，3. The processing chip according to claim 1 or 2, characterized in that the bias circuit comprises at least two code value conversion circuits, and the at least two code value conversion circuits correspond one-to-one to the at least two clock weight generation circuits; the code value conversion circuit comprises a first resistor, a second resistor, a phase switch, and a power supply circuit; wherein, 所述供电电路的第一端与所述第一电阻器的第一端耦合，所述第一电阻器的第二端与所述第二电阻器的第一端接地，所述供电电路的第二端与所述第二电阻器的第二端耦合；A first terminal of the power supply circuit is coupled to a first terminal of the first resistor, a second terminal of the first resistor and a first terminal of the second resistor are grounded, and a second terminal of the power supply circuit is coupled to a second terminal of the second resistor; 所述相位开关的第一端用于与第一供电源耦合，所述相位开关的第二端与所述第一电阻器的第一端耦合，所述相位开关的第二端与所述第二电阻器的第二端耦合；The first end of the phase switch is used to couple with a first power supply, the second end of the phase switch is coupled with a first end of the first resistor, and the second end of the phase switch is coupled with a second end of the second resistor; 所述相位开关管的控制端作为对应的所述码值转换电路的相位码值输入端；所述第一电阻器的第一端作为对应的所述码值转换电路的正输出端，与对应的所述时钟权重产生电路中的所述正偏置晶体管的控制端耦合；所述第二电阻器的第二端作为对应的所述码值转换电路的负输出端，与对应的所述时钟权重产生电路中的所述负偏置晶体管的控制端耦合。The control end of the phase switch tube serves as the phase code value input end of the corresponding code value conversion circuit; the first end of the first resistor serves as the positive output end of the corresponding code value conversion circuit, and is coupled to the control end of the positive bias transistor in the corresponding clock weight generation circuit; the second end of the second resistor serves as the negative output end of the corresponding code value conversion circuit, and is coupled to the control end of the negative bias transistor in the corresponding clock weight generation circuit. 4.根据权利要求3所述的处理芯片，其特征在于，所述供电电路包括多个权重开关，每个所述权重开关的第一端用于与对应的第二供电源耦合，每个所述权重开关的第二端与所述第一电阻器的第一端耦合，每个所述权重开关的第三端与所述第二电阻器的第二端耦合；4. The processing chip according to claim 3, wherein the power supply circuit comprises a plurality of weight switches, wherein a first end of each weight switch is coupled to a corresponding second power supply source, a second end of each weight switch is coupled to a first end of the first resistor, and a third end of each weight switch is coupled to a second end of the second resistor; 所述多个权重开关管的控制端作为对应的所述码值转换电路的权重码值输入端。The control ends of the plurality of weight switch tubes serve as weight code value input ends of the corresponding code value conversion circuits. 5.根据权利要求4所述的处理芯片，其特征在于，所述第一供电源为第一电流源。5 . The processing chip according to claim 4 , wherein the first power supply is a first current source. 6.根据权利要求5所述的处理芯片，其特征在于，所述第二供电源为第二电流源，所述权重开关设置有N个，所述第一电流源的输出电流为单个所述第二电流源输出电流的N倍。6 . The processing chip according to claim 5 , wherein the second power supply is a second current source, N weight switches are provided, and an output current of the first current source is N times the output current of a single second current source. 7.根据权利要求3或6所述的处理芯片，其特征在于，所述码值转换电路还包括偏置晶体管，所述偏置晶体管的第一端与所述第一电阻器和所述第二电阻器的耦合点耦合，所述偏置晶体管的第二端接地，所述偏置晶体管的控制端与所述偏置晶体管的第一端耦合。7. The processing chip according to claim 3 or 6 is characterized in that the code value conversion circuit further includes a bias transistor, a first end of the bias transistor is coupled to a coupling point between the first resistor and the second resistor, a second end of the bias transistor is grounded, and a control end of the bias transistor is coupled to the first end of the bias transistor. 8.根据权利要求1-7任一项所述的处理芯片，其特征在于，所述处理芯片还包括至少两个积分电路，所述至少两个积分器与所述至少两个时钟权重产生电路一一对应；所述积分电路包括下拉电流源、第三晶体管和第四晶体管；其中，8. The processing chip according to any one of claims 1 to 7, characterized in that the processing chip further comprises at least two integration circuits, the at least two integrators corresponding one-to-one to the at least two clock weight generation circuits; the integration circuit comprises a pull-down current source, a third transistor, and a fourth transistor; wherein, 所述第三晶体管的第一端和所述第四晶体管的第一端分别用于与供电源耦合，所述第三晶体管的第二受控端与所述下拉电流源的正极端耦合，所述第四晶体管的第二受控端与所述下拉电流源的正极端耦合，所述下拉电流源的负极端接地；The first end of the third transistor and the first end of the fourth transistor are respectively coupled to a power supply, the second controlled end of the third transistor is coupled to the positive end of the pull-down current source, the second controlled end of the fourth transistor is coupled to the positive end of the pull-down current source, and the negative end of the pull-down current source is grounded; 所述第三晶体管的控制端作为所述积分电路的正输入端，与所述时钟源的正极输出端耦合；所述第四晶体管的控制端作为所述积分电路的负输入端，与所述时钟源的负极输出端耦合；The control terminal of the third transistor serves as the positive input terminal of the integration circuit and is coupled to the positive output terminal of the clock source; the control terminal of the fourth transistor serves as the negative input terminal of the integration circuit and is coupled to the negative output terminal of the clock source; 所述第三晶体管的第一端作为所述积分电路的负输出端，与对应的所述时钟权重产生电路的负输入端耦合，所述第四晶体管的第一端作为所述积分电路的正输出端，与对应的所述时钟权重产生电路的正极输入端耦合。The first end of the third transistor serves as the negative output end of the integration circuit and is coupled to the negative input end of the corresponding clock weight generation circuit. The first end of the fourth transistor serves as the positive output end of the integration circuit and is coupled to the positive input end of the corresponding clock weight generation circuit. 9.根据权利要求8所述的处理芯片，其特征在于，所述下拉电流源包括第三电流源和第四电流源，所述第三晶体管的第二受控端与所述第三电流源的正极端耦合，所述第四晶体管的第二受控端与所述第四电流源的正极端耦合，所述第三电流源的负极端和所述第四电流源的负极端接地；所述积分电路还包括电压加速电路，所述电压加速电路包括第一电容器、第二电容器、第五电流源、第六电流源、第五晶体管和第六晶体管；其中，9. The processing chip according to claim 8, wherein the pull-down current source comprises a third current source and a fourth current source, the second controlled terminal of the third transistor is coupled to the positive terminal of the third current source, the second controlled terminal of the fourth transistor is coupled to the positive terminal of the fourth current source, and the negative terminal of the third current source and the negative terminal of the fourth current source are grounded; the integration circuit further comprises a voltage acceleration circuit, the voltage acceleration circuit comprising a first capacitor, a second capacitor, a fifth current source, a sixth current source, a fifth transistor, and a sixth transistor; wherein, 所述第五晶体管的第一端和所述第六晶体管的第一端分别用于输入供电电压，所述第五晶体管的第二端与所述第五电流源的正极端耦合，所述第六晶体管的第二端与所述第六电流源的正极端耦合，所述第五电流源的负极端和所述第六电流源的负极端接地；The first end of the fifth transistor and the first end of the sixth transistor are respectively used to input a supply voltage, the second end of the fifth transistor is coupled to the positive terminal of the fifth current source, the second end of the sixth transistor is coupled to the positive terminal of the sixth current source, and the negative terminal of the fifth current source and the negative terminal of the sixth current source are grounded; 所述第一电容器的第一端与所述第五晶体管的第二端耦合，所述第一电容器的第二端与所述第三晶体管的第二端耦合；所述第二电容器的第一端与所述第六晶体管的第二端耦合，所述第二电容器的第二端与所述第四晶体管的第二端耦合；A first terminal of the first capacitor is coupled to the second terminal of the fifth transistor, and a second terminal of the first capacitor is coupled to the second terminal of the third transistor; a first terminal of the second capacitor is coupled to the second terminal of the sixth transistor, and a second terminal of the second capacitor is coupled to the second terminal of the fourth transistor; 所述第五晶体管的控制端与所述第四晶体管的控制端耦合，所述第六晶体管的控制端与所述第三晶体管的控制端耦合。The control terminal of the fifth transistor is coupled to the control terminal of the fourth transistor, and the control terminal of the sixth transistor is coupled to the control terminal of the third transistor. 10.根据权利要求8或9所述的处理芯片，其特征在于，所述积分电路还包括第三电容器，所述第三电容器的第一端与第三晶体管的第二端耦合，所述第三晶体管的第二端与所述第四晶体管的第二端耦合。10. The processing chip according to claim 8 or 9, wherein the integration circuit further comprises a third capacitor, a first end of the third capacitor is coupled to the second end of the third transistor, and a second end of the third transistor is coupled to the second end of the fourth transistor. 11.根据权利要求1-10任一项所述的处理芯片，其特征在于，所述插值电路还包括第四电容器和第五电容器，所述第四电容器的第一端与所述第一晶体管的第二端耦合，所述第四电容器的第二端与所述第五电容器的第一端耦合，所述第五电容器的第二端与所述第二晶体管的第二端耦合；11. The processing chip according to any one of claims 1 to 10, wherein the interpolation circuit further comprises a fourth capacitor and a fifth capacitor, wherein a first end of the fourth capacitor is coupled to the second end of the first transistor, a second end of the fourth capacitor is coupled to the first end of the fifth capacitor, and a second end of the fifth capacitor is coupled to the second end of the second transistor; 所述第四电容器与所述第五电容器的耦合点作为所述插值电路的输出端。A coupling point between the fourth capacitor and the fifth capacitor serves as an output end of the interpolation circuit. 12.根据权利要求1-11任一项所述的处理芯片，其特征在于，所述插值器设置有一个或多个；当所述插值器设置多个时，多个所述插值器的输入端并联。12. The processing chip according to any one of claims 1 to 11, characterized in that there are one or more interpolators; when there are multiple interpolators, input ends of the multiple interpolators are connected in parallel. 13.根据权利要求1-12任一项所述的处理芯片，其特征在于，所述处理芯片还包括输出放大器，所述输出放大器的输入端与所述插值器的输出端耦合。13 . The processing chip according to claim 1 , further comprising an output amplifier, wherein an input terminal of the output amplifier is coupled to an output terminal of the interpolator. 14.根据权利要求1-13任一项所述的处理芯片，其特征在于，所述处理芯片为接口芯片或时钟处理芯片。14. The processing chip according to any one of claims 1 to 13, characterized in that the processing chip is an interface chip or a clock processing chip. 15.一种处理芯片，其特征在于，包括时钟源、积分器和插值器；其中，所述积分器包括至少两个积分电路，每个所述积分电路包括第一电容器、第二电容器、第三电流源、第四电流源、第五电流源、第六电流源、第三晶体管、第四晶体管、第五晶体管和第六晶体管；其中，15. A processing chip, comprising a clock source, an integrator, and an interpolator; wherein the integrator comprises at least two integrating circuits, each of the integrating circuits comprising a first capacitor, a second capacitor, a third current source, a fourth current source, a fifth current source, a sixth current source, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor; wherein, 所述第三晶体管的第一端和所述第四晶体管的第一端分别用于与供电源耦合，所述第三晶体管的第二受控端与所述第三电流源的正极端耦合，所述第四晶体管的第二受控端与所述第四电流源的正极端耦合，所述第三电流源的负极端和所述第四电流源的负极端接地；The first end of the third transistor and the first end of the fourth transistor are respectively coupled to a power supply, the second controlled end of the third transistor is coupled to the positive end of the third current source, the second controlled end of the fourth transistor is coupled to the positive end of the fourth current source, and the negative end of the third current source and the negative end of the fourth current source are grounded; 所述第五晶体管的第一端和所述第六晶体管的第一端分别用于输入供电电压，所述第五晶体管的第二端与所述第五电流源的正极端耦合，所述第六晶体管的第二端与所述第六电流源的正极端耦合，所述第五电流源的负极端和所述第六电流源的负极端接地；The first end of the fifth transistor and the first end of the sixth transistor are respectively used to input a supply voltage, the second end of the fifth transistor is coupled to the positive terminal of the fifth current source, the second end of the sixth transistor is coupled to the positive terminal of the sixth current source, and the negative terminal of the fifth current source and the negative terminal of the sixth current source are grounded; 所述第一电容器的第一端与所述第五晶体管的第二端耦合，所述第一电容器的第二端与所述第三晶体管的第二端耦合；所述第二电容器的第一端与所述第六晶体管的第二端耦合，所述第二电容器的第二端与所述第四晶体管的第二端耦合；A first terminal of the first capacitor is coupled to the second terminal of the fifth transistor, and a second terminal of the first capacitor is coupled to the second terminal of the third transistor; a first terminal of the second capacitor is coupled to the second terminal of the sixth transistor, and a second terminal of the second capacitor is coupled to the second terminal of the fourth transistor; 所述第六晶体管的控制端与所述第三晶体管的控制端耦合后作为所述积分电路的正输入端，与所述时钟源的正输出端耦合；所述第五晶体管的控制端与所述第四晶体管的控制端耦合后作为所述积分电路的负输入端，与所述时钟源的负输出端耦合；The control terminal of the sixth transistor is coupled with the control terminal of the third transistor, and serves as a positive input terminal of the integration circuit, and is coupled to the positive output terminal of the clock source; the control terminal of the fifth transistor is coupled with the control terminal of the fourth transistor, and serves as a negative input terminal of the integration circuit, and is coupled to the negative output terminal of the clock source; 所述第三晶体管的第一端作为所述积分电路的正输出端与所述插值器的正输入端耦合，所述第四晶体管的第一端作为所述积分电路的负输出端与所述插值器的负输入端耦合。The first end of the third transistor is coupled to the positive input end of the interpolator as the positive output end of the integration circuit, and the first end of the fourth transistor is coupled to the negative input end of the interpolator as the negative output end of the integration circuit. 16.根据权利要求15所述的处理芯片，其特征在于，所述积分电路还包括第三电容器，所述第三电容器的第一端与第三晶体管的第二端耦合，所述第三晶体管的第二端与所述第四晶体管的第二端耦合。16 . The processing chip according to claim 15 , wherein the integration circuit further comprises a third capacitor, a first terminal of the third capacitor is coupled to the second terminal of the third transistor, and a second terminal of the third transistor is coupled to the second terminal of the fourth transistor. 17.一种芯片系统，其特征在于，包括PCB板和上述权利要求1-16任一项所述的处理芯片，所述处理芯片设置于所述PCB板上。17. A chip system, comprising a PCB board and the processing chip according to any one of claims 1 to 16, wherein the processing chip is arranged on the PCB board. 18.一种电子设备，其特征在于，包括设备壳体和上述权利要求17所述的芯片系统，所述芯片系统的部分或全部设置在所述设备壳体内。18. An electronic device, characterized in that it comprises a device housing and the chip system according to claim 17, wherein part or all of the chip system is arranged in the device housing.
CN202410437378.1A 2024-04-11 2024-04-11 Processing chip, chip system and electronic equipment Pending CN120821331A (en)

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