CN120812967B - A MOSFET structure with gate nanosheets and its fabrication process - Google Patents
A MOSFET structure with gate nanosheets and its fabrication processInfo
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- CN120812967B CN120812967B CN202511271193.9A CN202511271193A CN120812967B CN 120812967 B CN120812967 B CN 120812967B CN 202511271193 A CN202511271193 A CN 202511271193A CN 120812967 B CN120812967 B CN 120812967B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/501—FETs having stacked nanowire, nanosheet or nanoribbon channels
- H10D30/507—FETs having stacked nanowire, nanosheet or nanoribbon channels characterised by inner spacers between adjacent channels
- H10D30/508—FETs having stacked nanowire, nanosheet or nanoribbon channels characterised by inner spacers between adjacent channels characterised by the relative sizes, shapes or dispositions of the inner spacers
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/019—Manufacture or treatment of FETs having stacked nanowire, nanosheet or nanoribbon channels
- H10D30/0195—Manufacture or treatment of FETs having stacked nanowire, nanosheet or nanoribbon channels forming inner spacers between adjacent channels, e.g. changing their shapes or sizes
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
- H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
- H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
- H10D30/6735—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes having gates fully surrounding the channels, e.g. gate-all-around
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- Electrodes Of Semiconductors (AREA)
Abstract
本发明涉及MOS半导体技术领域，且公开了一种具有栅极纳米片的MOSFET结构及其制造工艺，包括若干个相互并列的MOS元胞，单个MOS元胞包括有漏极、半导体外延层、栅极、栅氧化层和源极，半导体外延层包括有N衬底层、N漂移层、N阱层、P+层和P阱层，栅极包括栅极覆盖层和栅极纳米片；单个MOS元胞中栅极纳米片有若干个，并且若干个该栅极纳米片呈水平矩阵分布，栅极纳米片延伸至栅极覆盖层的内部并与其直接接触。本发明通过水平矩阵分布的纳米片栅极与高导电性覆盖层的三维嵌入式接触，显著增强沟道静电控制能力，同时降低栅极电阻，实现更高电流驱动密度和更优开关特性，突破传统平面器件的物理限制。
This invention relates to the field of MOS semiconductor technology and discloses a MOSFET structure with gate nanosheets and its manufacturing process. The structure includes several parallel MOS cells. Each MOS cell includes a drain, a semiconductor epitaxial layer, a gate, a gate oxide layer, and a source. The semiconductor epitaxial layer includes an N-substrate layer, an N-drift layer, an N-well layer, a P+ layer, and a P-well layer. The gate includes a gate capping layer and gate nanosheets. Each MOS cell contains several gate nanosheets arranged in a horizontal matrix, extending into and directly contacting the gate capping layer. This invention significantly enhances channel electrostatic control capabilities and reduces gate resistance through the three-dimensional embedded contact between the horizontally matrix-distributed nanosheet gate and the highly conductive capping layer, achieving higher current drive density and superior switching characteristics, thus overcoming the physical limitations of traditional planar devices.
Description
Technical Field
The invention relates to the technical field of MOS semiconductors, in particular to a MOSFET structure with a grid nano-sheet and a manufacturing process thereof.
Background
As the miniaturization of semiconductor devices approaches physical limits, conventional planar gate and FinFET structures face challenges with reduced gate control capability and significantly exacerbated short channel effects at nodes below 5 nm. Although the gate control capability of the full-surrounding Gate (GAA) nano-sheet transistor is improved through a three-dimensional channel, the conventional structure still has key bottlenecks that firstly, the contact resistance between the nano-sheet gate and an external electrode is high to limit the driving current density, secondly, the high-density nano-sheet array is easy to cause local concentration of an electric field when the high-voltage is applied, so that a drift region is broken down prematurely, and the conventional protection ring design is difficult to achieve both voltage-resistant improvement and on-resistance (Rdson) optimization, thirdly, edge breakdown is induced due to uneven electric field distribution of a device terminal, and high-voltage reliability is limited. In addition, the existing manufacturing process has insufficient cooperative control precision for complex three-dimensional gate integration and custom doping, and influences performance uniformity.
The prior patent discloses a MOSFET (CN 118299423A) with a GAA structure, which comprises a silicon substrate, a semiconductor layer, a gate oxide layer, gate polysilicon, a source electrode and a drain electrode, wherein the semiconductor layer comprises a source region, a drain region and a nanowire channel, the gate polysilicon wraps the nanowire channel in a full-surrounding manner, and the semiconductor layer and the silicon substrate are integrally formed by a silicon wafer. The GAA structure of the prior patent is not optimized for high voltage application, and the uneven electric field distribution of the drift region is easy to cause local breakdown. And the prior patent adopts the traditional polysilicon gate to directly contact with metal, so that the gate resistance is higher.
Disclosure of Invention
The invention provides a MOSFET structure with grid nano-sheets and a manufacturing process thereof for solving the existing technical problems, and solves the problem that local breakdown is easily caused by uneven electric field distribution of a drift region.
In order to solve the above technical problem, according to one aspect of the present invention, a MOSFET structure with a gate nano-sheet includes a plurality of MOS cells arranged in parallel, wherein each MOS cell includes a drain electrode, a semiconductor epitaxial layer, a gate electrode, a gate oxide layer, and a source electrode, the semiconductor epitaxial layer includes an N substrate layer, an N drift layer, an N well layer, a p+ layer, and a P well layer, and the gate electrode includes a gate cover layer and a gate nano-sheet;
And a plurality of grid nano-sheets are arranged in the single MOS unit cell, and are distributed in a horizontal matrix, and extend into the grid covering layer and are in direct contact with the grid covering layer.
Furthermore, the grid nano-sheet is made of P-type polycrystalline silicon.
Further, the gate coating is made of one of titanium nitride and tungsten nitride.
Furthermore, a P-type protection ring is formed in the single MOS cell, in the N drift layer, and under the gate nano-sheet by ion implantation;
the number and the positions of the P-type protection rings only correspond to the number and the positions of the grid nano-sheets in the middle area one by one.
Further, the P-type protection ring further comprises a convex protection ring;
Wherein, the cross-section outline of all convex protection ring areas in a single MOS cell is convex downwards in the middle.
Further, an n+ cover layer is formed by ion implantation inside the N drift layer and below the convex guard ring, and both ends of the n+ cover layer are in direct contact with the P-well layer.
Furthermore, P-type matrix areas are arranged in the single MOS unit cell and positioned on two sides of the N substrate layer, and each P-type matrix area consists of a plurality of P-type grids distributed in an array.
Further, the top end of the P-type gate extends to the inside of the N drift layer, and the bottom end of the P-type gate is in ohmic contact with the drain electrode.
The manufacturing process of the MOSFET structure with the grid nano-sheet comprises the following specific steps:
S1, taking an N-type substrate layer as a starting substrate, sequentially epitaxially growing an N drift layer and an N well layer on the starting substrate, and forming a P well layer and a P+ layer through ion implantation;
S2, depositing and patterning a sacrificial material layer on the epitaxial layer to define a plurality of channel regions distributed in a horizontal matrix, forming a semiconductor material layer serving as a grid nano-sheet in the channel regions through a selective epitaxial or deposition process, and suspending the semiconductor material layer above the epitaxial layer through an etching process;
S3, growing a gate oxide layer on the whole surface of the suspended semiconductor material layer, depositing conductive material of the gate nano sheet, filling and wrapping the suspended structure, and removing redundant material through a back etching process;
Patterning the gate coating by photolithography and etching processes to ensure that the ends of the gate nanoplates extend and are embedded into the patterned gate coating to form direct electrical and physical contact therewith;
s5, ohmic contact areas of a source electrode and a drain electrode are formed on two sides of the gate structure through ion implantation and annealing processes;
S6, depositing an interlayer dielectric layer, forming a contact hole through photoetching and etching, depositing metal to fill the contact hole, and finally forming a covering layer with the source electrode, the drain electrode and the grid electrode.
Compared with the prior art, the MOSFET structure with the grid nanosheets and the manufacturing process thereof provided by the invention have the following effects:
1. According to the invention, through the three-dimensional embedded contact between the nano sheet grid electrodes distributed in the horizontal matrix and the high-conductivity covering layer, the channel static control capability is obviously enhanced, meanwhile, the grid resistance is reduced, higher current driving density and better switching characteristics are realized, and the physical limitation of the traditional planar device is broken through.
2. According to the invention, the P-type protection ring and the convex structure which are selectively arranged cooperatively optimize the electric field distribution of the drift region, the electric field peak below the grid nano-sheet is precisely restrained, the voltage endurance capability of the device is improved, the extra loss of on-resistance is avoided, and the hidden danger of local breakdown of the high-density nano-sheet array is solved.
3. According to the invention, a carrier 'dredging-shielding' double mechanism is formed by the N+ covering layer and the convex protection ring, so that electrons are accelerated to pass through the high-voltage drift region to reduce dynamic resistance, and floating effect is eliminated by connecting the P well layer, thereby remarkably improving the switching stability and high-frequency response characteristic of the device.
4. According to the invention, the terminal electric field distribution of the device is reconstructed through the array type P-type matrix region, the terminal breakdown risk is eliminated through dispersing the peak value of the fringe electric field, the vertical current bypass is provided to reduce the overall on-resistance, and the array heat dissipation advantage is utilized to improve the reliability under the heavy current working condition.
5. The invention realizes high-precision manufacturing of complex three-dimensional structures through collaborative innovation of sacrificial layer release, full-surrounding gate integration and custom doping in the whole process flow, and provides a solution with high density, high voltage resistance and low loss for high-voltage high-power application while ensuring process compatibility.
Drawings
FIG. 1 is a schematic diagram of a first embodiment of the present invention;
FIG. 2 is a schematic diagram of a second embodiment of the present invention;
FIG. 3 is a schematic diagram of a third embodiment of the present invention;
FIG. 4 is a schematic diagram of a fourth embodiment of the present invention;
Fig. 5 is a schematic diagram of a fifth embodiment of the present invention.
In the figure, 1, a drain electrode, 2, a gate covering layer, 3, a gate nano-sheet, 4, a gate oxide layer, 5, a source electrode, 6, an N substrate layer, 7, an N drift layer, 8, an N well layer, 9, a P+ layer, 10, a P well layer, 11, a P type protection ring, 12, an N+ covering layer, 13, a P type matrix region, 1101 and a convex type protection ring.
Detailed Description
In order to make the technical scheme of the invention clearer, the invention is further described in detail below with reference to the attached drawings and specific embodiments.
As shown in fig. 1, a process for manufacturing a MOSFET structure with gate nano-sheets includes the following specific steps:
The first step is to take an N-type substrate layer 6 as a starting substrate, sequentially epitaxially grow an N drift layer 7 and an N well layer 8 on the N drift layer and form a P well layer 10 and a P+ layer 9 through ion implantation, sequentially epitaxially grow (the N drift layer 7 to the N well layer 8) and selectively implant (the P well layer 10 or the P+ layer 9) to form optimized carrier concentration distribution on the N substrate 6, provide a low defect substrate for a nano-sheet channel, and lay a device voltage-withstanding and conduction characteristic foundation at the same time.
A second step of depositing and patterning a sacrificial material layer on the epitaxial layer to define a plurality of channel regions distributed in a horizontal matrix, forming a semiconductor material layer serving as a grid nano-sheet 3 in the channel regions through selective epitaxy or a deposition process and suspending the semiconductor material layer on the epitaxial layer through an etching process, patterning the sacrificial layer to precisely define a horizontal matrix channel position, selectively epitaxial/depositing to ensure lattice quality of nano-sheet materials (converted into the grid nano-sheet 3 later), suspending etching to release the channel regions, creating physical space for wrapping the full-surrounding grid oxide layer, and breaking through plane structure limitation.
Step three, growing a gate oxide layer 4 on the whole surface of the suspended semiconductor material layer, then depositing a conductive material of the gate nano-sheet 3, filling and wrapping the suspended structure, removing redundant materials through a back etching process, growing the gate oxide layer 4 on the surface of the suspended nano-sheet to realize uniform dielectric isolation, filling and wrapping P-type polycrystalline silicon to form a conductive main body of the gate nano-sheet 3, and accurately controlling the thickness/morphology of the nano-sheet through the back etching process, and synchronously guaranteeing the channel electrostatic control force and carrier mobility.
The fourth step is to deposit the material of the gate cover layer 2 on the structure containing the gate nano-sheet 3, pattern the gate cover layer 2 through photolithography and etching process to ensure that the end of the gate nano-sheet 3 extends and is embedded into the patterned gate cover layer 2 to form direct electrical and physical contact therewith, deposit the titanium nitride/tungsten nitride gate cover layer 2 to provide high conductive path, and embed the end of the nano-sheet into the cover layer to form nano-scale ohmic contact by photolithography-etching patterning, thereby remarkably reducing gate resistance (which is reduced by more than 30% compared with the traditional interface), and having strong process compatibility.
Forming ohmic contact areas of the source electrode 5 and the drain electrode 1 on two sides of the gate structure through ion implantation and annealing processes, performing ion implantation by taking the gate structure as a mask to ensure that the source electrode 5/drain electrode 1 is aligned with a channel accurately, enabling the annealing processes to activate impurities and repair damages synchronously, forming an ohmic junction with low contact resistance, and completing electrical activation of customized doped structures such as a protection ring (11/1101).
And step six, depositing an interlayer dielectric layer, forming a contact hole through photoetching and etching, depositing metal to fill the contact hole, and finally forming the source electrode 5, the drain electrode 1 and the gate covering layer 2. The interlayer dielectric is flattened to avoid topology drop, the contact hole lithography precisely exposes the key nodes of the source/drain/gate cover layer 2, the metal filling forms a low-resistance interconnection network, the low resistance advantage of the gate cover layer is continued, and finally the high-efficiency output of the device performance is realized.
Example 1
As shown in fig. 1, according to one aspect of the present invention, there is provided a MOSFET structure having a gate nano-sheet, which includes a plurality of MOS cells juxtaposed with each other, a single MOS cell including a drain electrode 1, a semiconductor epitaxial layer including an N substrate layer 6, an N drift layer 7, an N well layer 8, a p+ layer 9 and a P well layer 10, and a gate including a gate cap layer 2 and a gate nano-sheet 3, wherein the gate nano-sheet 3 in the single MOS cell is a plurality of the gate nano-sheets 3 distributed in a horizontal matrix, and the gate nano-sheet 3 extends into the interior of the gate cap layer 2 and is in direct contact therewith. The grid nano-sheet 3 is made of P-type polycrystalline silicon. The gate coating 2 is made of one of titanium nitride and tungsten nitride.
The grid covering layer 2 made of titanium nitride and tungsten nitride is embedded into the P-type polysilicon grid nano-sheets 3 distributed in a horizontal matrix, so that three-dimensional electrical contact is formed. The nanoplatelet fully surrounding structure provides stronger channel electrostatic control, thereby enhancing gate control capability. The nano sheet is directly contacted with the high-conductivity coating layer to reduce the impedance of a current path and further reduce the contact resistance, and the horizontal matrix distribution realizes higher driving current in unit area and further improves the integration density.
Example 2
As shown in fig. 2, P-type guard rings 11 are formed in the single MOS cell, in the N drift layer 7, and directly under the gate nano-sheets 3 by ion implantation, and the number and positions of the P-type guard rings 11 are in one-to-one correspondence with the number and positions of the gate nano-sheets 3 in the middle region.
And selectively injecting a P-type protection ring 11 into the N drift layer 7 right below the middle gate nano-plate to form a local charge balance region. The design protection ring suppresses the electric field peak below the middle nano sheet to optimize the electric field distribution, and avoids local breakdown, so that the breakdown voltage of the cell is homogenized to improve the voltage endurance capacity, and the design protection ring only aims at the middle area nano sheet with high electric field risk, so that the excessive sacrifice of on-resistance is avoided.
Example 3
As shown in fig. 3, P-type guard rings 11 are formed in the single MOS cell, in the N drift layer 7, and directly under the gate nano-sheets 3by ion implantation, and the number and positions of the P-type guard rings 11 are in one-to-one correspondence with the number and positions of the gate nano-sheets 3 in the middle region. The P-type guard ring 11 further comprises a convex guard ring 1101, wherein the cross-sectional profile of all the convex guard ring 1101 areas in a single MOS cell is convex downward in the middle.
The P-type guard ring 11 is designed as a convex guard ring 1101 protruding downward, forming a three-dimensional charge compensation structure. The convex profile expands the volume of the depletion region, more effectively disperses the electric field, improves the carrier extraction efficiency of the drift region by the curved junction depth to enhance carrier control, and simultaneously realizes by adjusting the ion implantation angle/energy without additional masks.
Example 4
As shown in fig. 4, P-type guard rings 11 are formed by ion implantation in the N drift layer 7 of the single MOS cell and directly below the gate nano-sheets 3, and the number and positions of the P-type guard rings 11 are in one-to-one correspondence with the number and positions of the gate nano-sheets 3 in the middle region. The P-type guard ring 11 further comprises a convex guard ring 1101, wherein the cross-sectional profile of all the convex guard ring 1101 areas in a single MOS cell is convex downward in the middle. An n+ cap layer 12 is formed by ion implantation inside the N drift layer 7 and below the convex guard ring 1101, and both ends of the n+ cap layer 12 are in direct contact with the P-well layer 10.
An n+ cap layer 12 is injected under the convex guard ring 1101, and both ends thereof are connected to the P-well layer 10 to form a carrier acceleration channel. The N+ cover layer 12 provides a low-resistance passage, accelerates electrons to pass through the high-voltage drift region to realize dynamic resistance optimization, the two ends of the N+ cover layer are connected with the P well to avoid floating effect, the stability of the switch is improved to inhibit parasitic effect, and the design and the convex protection ring form an electric field shielding-carrier dredging double mechanism.
Example 5
As shown in fig. 5, P-type matrix regions 13 are disposed in a single MOS cell and on both sides of the N substrate layer 6, and the P-type matrix regions 13 are composed of a plurality of P-type gates distributed in an array. The top of the P-type gate extends into the N drift layer 7, and the bottom of the P-type gate is in ohmic contact with the drain 1.
An array type P-type matrix region 13 is constructed at two sides of the N substrate (6), the top end of the P-type gate extends to the N drift layer 7, and the bottom end of the P-type gate is connected with the drain electrode 1. The P-type matrix region 13 disperses fringe electric fields to eliminate potential terminal breakdown hazards, the P-type grid provides vertical current bypass to reduce overall on-resistance so as to improve on characteristics, and the array distribution avoids local heat concentration to enhance high-current reliability.
The foregoing examples illustrate only a few embodiments of the invention and are described in detail herein without thereby limiting the scope of the invention. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the invention, which are all within the scope of the invention. Accordingly, the scope of protection of the present invention is to be determined by the appended claims.
Claims (8)
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| WO2015053805A1 (en) * | 2013-10-07 | 2015-04-16 | Purdue Research Foundation | Mos-based power semiconductor device having increased current carrying area and method of fabricating same |
| US20200185384A1 (en) * | 2018-12-11 | 2020-06-11 | Qualcomm Incorporated | Horizontal gate-all-around (gaa) field effect transistor (fet) for complementary metal oxide semiconductor (cmos) integration |
| KR20240118100A (en) * | 2021-12-10 | 2024-08-02 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | semiconductor device |
| CN117712173A (en) * | 2023-12-15 | 2024-03-15 | 派恩杰半导体（杭州）有限公司 | Multi-surface gate silicon carbide MOSFET (Metal-oxide-semiconductor field Effect transistor) and preparation method and chip thereof |
| CN120091609B (en) * | 2025-04-30 | 2025-08-12 | 杭州谱析光晶半导体科技有限公司 | Double-gate structure for high-performance MOSFET and optimization method |
| CN120302689B (en) * | 2025-06-10 | 2025-08-19 | 杭州谱析光晶半导体科技有限公司 | A heterojunction-based silicon carbide trench MOSFET device structure and its preparation process |
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| CN118299423A (en) * | 2024-04-01 | 2024-07-05 | 浙江朗德电子科技有限公司 | MOSFET with GAA structure and preparation method thereof |
| CN120264819A (en) * | 2025-06-04 | 2025-07-04 | 杭州谱析光晶半导体科技有限公司 | A vertical D-MOSFET with trench isolation and improved channel structure and preparation method thereof |
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