CN120812955A - Novel ferroelectric capacitor based on MFIS structure and preparation method thereof - Google Patents
Novel ferroelectric capacitor based on MFIS structure and preparation method thereofInfo
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- H—ELECTRICITY
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- H—ELECTRICITY
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Abstract
The invention belongs to the field of semiconductors, and discloses a novel ferroelectric memcapacitor based on an MFIS structure and a preparation method thereof, wherein a substrate of the novel ferroelectric memcapacitor comprises a first doping region and a second doping region, and the doping type of the first doping region is p-type; the insulating layer, the ferroelectric layer and the top electrode layer are arranged on the substrate from bottom to top and cover the first doped region of the substrate; the surface of the substrate is not covered with a second doped region, the doping type of the second doped region is n-type, the bottom electrode layer is positioned in the second doped region of the substrate and far away from the first doped region, the channel is positioned in the second doped region of the substrate and near the first doped region, and a corresponding preparation method is provided.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a novel ferroelectric memcapacitor based on an MFIS structure and a preparation method thereof.
Background
With the rise of artificial intelligence, neuromorphic computation, sensing and edge computation, the traditional von neumann architecture cannot meet the requirements of high-parallelism and low-power processing, and the memristor is an important research object of a next-generation computing and storage fusion system due to the characteristics of low power consumption, non-volatility and the like. Current implementation research of memristors is continually moving towards higher integration, lower power consumption and better stability.
Currently, charge tunneling based memcapacitor, two-dimensional material based memcapacitor, and ferroelectric material based memcapacitor are proposed sequentially. Among them, memristors built with novel ferroelectric materials are of particular interest. The charge tunneling memcapacitor captures charge using a trap state in the dielectric layer, thereby changing the dielectric response to change the capacitance state. The two-dimensional material memcapacitor utilizes two-dimensional semiconductor materials such as black phosphorus, molybdenum disulfide, graphene and the like to construct a heterojunction, and changes a capacitance state through charge transfer between material layers. However, the reliability problems of the two technical schemes cannot be ignored, the stability of the charge tunneling memcapacitor is seriously affected by the defect state density and the charge leakage, and the application of the charge tunneling memcapacitor is limited by the weak adhesion between two-dimensional material layers and the poor environmental stability.
The ferroelectric memcapacitor utilizes the polarization hysteresis characteristic of ferroelectric materials to display the nonlinear response and hysteresis effect of the capacitor under the action of different excitation voltages, thereby realizing the regulation and control of the capacitor state. Compared with the two memcapacitor, the ferroelectric memcapacitor has stable material property, adjustable capacitance value and extremely high application advantage. Currently, a novel ferroelectric material such as hafnium zirconium oxide, hafnium aluminum oxide and the like is mostly adopted in the ferroelectric capacitor. Compared with traditional ferroelectric materials such as PZT and BaTiO 3, the method has the advantages of being fully compatible with the CMOS process and not requiring a high-temperature process, is suitable for large-scale integration, and can meet the requirements of current advanced process nodes.
In the aspect of ferroelectric memcapacitor structure, the ferroelectric memcapacitor with the MFM structure and the ferroelectric memcapacitor with the MFMS structure are widely studied. The ferroelectric memcapacitor with the MFM structure has the advantages of simple preparation process, small working voltage and low power consumption, and has large-scale integration application potential. The capacitance switch ratio of the ferroelectric memcapacitor with the MFM structure depends on the capacitance change of the ferroelectric layer, the switch is smaller, the requirement on the precision of a peripheral control circuit is higher in practical application, and signal misreading is easy to cause.
The ferroelectric memcapacitor of the MFMS structure is characterized in that a layer of semiconductor material (silicon, oxide semiconductor and the like) is introduced below metal, when a forward bias voltage is applied, the total capacitance is mainly influenced by the ferroelectric capacitance, when a reverse bias voltage is applied, the surface of the semiconductor material is partially depleted, a smaller depletion layer capacitance is introduced in the total capacitance, and the total capacitance is influenced by the depletion layer capacitance, so that the capacitance switching ratio of the device is increased. The ferroelectric memcapacitor with the MFMS structure has basically unchanged capacitance when a fixed forward bias voltage is applied, and the total capacitance is reduced by the depletion layer capacitance of the semiconductor interface part depletion when a large reverse bias voltage is applied. The single-layer semiconductor material introduced by the MFMS structure has single polarity, so that one side of the ferroelectric layer cannot be completely turned over during turning over, the thickness of a generated depletion region is limited, the capacity of reducing the total capacitance is limited, the switching ratio increasing capacity is limited, the inherent nonvolatile advantage of the MFMS structure cannot be fully exerted, and meanwhile, in order to form the depletion region, higher voltage is required, and the power consumption is increased.
Therefore, it is necessary to provide a novel ferroelectric capacitor capable of fully turning over a ferroelectric thin film without requiring a large voltage and adjusting the depletion region capacitance of a PN junction on one side of a semiconductor, thereby ensuring low power consumption and obtaining a high capacitance-to-switch ratio.
Disclosure of Invention
Aiming at the technical problems in the background art, the invention aims to provide a novel ferroelectric capacitor based on an MFIS structure and a preparation method thereof. The novel ferroelectric memcapacitor is based on an MFIS (Metal-Ferroelectric-Insulator-Semiconductor) structure, can enable a ferroelectric film to be fully turned over without large voltage, and can adjust the depletion region capacitance of a PN junction at one side of a Semiconductor, so that high capacitance-to-switch ratio is obtained while low power consumption is ensured.
In order to achieve the above purpose, the invention adopts the following technical means:
The invention provides a novel ferroelectric memcapacitor based on an MFIS structure, which comprises a semiconductor substrate, an insulating layer, a ferroelectric layer, a top electrode layer and a bottom electrode layer;
The semiconductor comprises a semiconductor substrate, wherein the semiconductor substrate comprises a first doped region and a second doped region, and the doping type of the first doped region is p-type;
the insulating layer, the ferroelectric layer and the top electrode layer are arranged on the semiconductor substrate from bottom to top and cover the first doped region of the semiconductor substrate;
The uncovered area of the surface of the semiconductor substrate is a second doped area, and the doping type of the second doped area is n-type;
the bottom electrode layer is positioned at the outer edge of the second doped region of the semiconductor substrate;
The channel is located inside the second doped region of the semiconductor substrate.
Further, the semiconductor substrate is an SOI substrate or a Si substrate.
Further, the SOI substrate is formed by stacking a Si layer, a SiO 2 layer and a p-type Si layer.
Further, the insulating layer is an SiO 2 insulating layer, and the thickness is 1 nm-3 nm.
Further, the deposited film material adopted by the ferroelectric layer is one of HfZrO x、HfAlOx, and the thickness of the ferroelectric layer is 3-12 nm.
Further, the top electrode layer and the bottom electrode layer are metal layers formed by sputtering one of metals W, tiN, and the thickness is 10 nm-100 nm.
Further, the channel doping concentration is 1e13 cm -3～1e17 cm-3.
When negative pulse voltage is applied to the top electrode layer, the p-type area under the top electrode layer generates accumulation of holes through band tunneling, the PN junction space charge area widens, PN junction capacitance is reduced, the total capacitance of the device is the sum of ferroelectric capacitance, insulating layer capacitance and PN junction depletion area capacitance in parallel connection, and the total capacitance of the device is low-state capacitance.
The second aspect of the invention provides a preparation method of the novel ferroelectric capacitor based on the MFIS structure, which comprises the following steps:
s1, providing a semiconductor substrate and cleaning the semiconductor substrate;
S2, performing rapid heating oxidation (RTO) treatment to passivate the upper surface of the semiconductor substrate to form a SiO 2 insulating layer;
S3, depositing a ferroelectric layer on the SiO 2 insulating layer by adopting atomic layer deposition ALD;
S4, performing rapid heat treatment RTP in an N 2 atmosphere to crystallize the ferroelectric layer;
S5, sputtering metal on the ferroelectric layer by physical vapor deposition PVD, and depositing to form a top electrode layer;
S6, etching the top electrode layer, the ferroelectric layer and the insulating layer on the top electrode layer through photoetching and plasma to form a window positioned in an active area of the semiconductor substrate;
s7, implanting N-type impurities into the active region window in an ion implantation mode, and forming an N-type active region through doping;
S8, performing rapid thermal processing RTP, and activating doping of the N-type active region;
And S9, performing PVD (physical vapor deposition) sputtering metal on the N-type active region window formed by photoetching, and forming a bottom electrode layer by partial deposition to obtain the novel ferroelectric capacitor, wherein a channel of the novel ferroelectric capacitor is positioned on the semiconductor substrate.
Further, the semiconductor substrate is an SOI substrate or a Si substrate.
Further, the SOI substrate is formed by stacking a Si layer, a SiO 2 layer and a p-type Si layer.
Further, the semiconductor substrate is cleaned by a wet chemical cleaning RCA process.
Further, in step S2, the thickness of the SiO 2 insulating layer is 1nm to 3nm.
Further, in the step S3, the thin film material of the deposited ferroelectric layer is one of HfZrO x、HfAlOx, and the thickness of the deposited ferroelectric layer is 3 nm-12 nm.
Further, in step S4, the temperature of RTP treatment is 300-600 ℃ and the time is 30-60S.
Further, in steps S5 and S9, the sputtered metal is one of W, tiN, and the thickness of the formed metal layer is 10 nm-100 nm.
Further, in step S9, the channel doping concentration is 1e13 cm -3～1e17 cm-3.
Compared with the prior art, the invention has the following beneficial effects:
The novel ferroelectric memcapacitor replaces a unipolar semiconductor layer used in the traditional MFMS structure by introducing a PN junction structure into a Si layer of an SOI substrate, and an n+ doped region is formed in p-type silicon by an ion implantation process by the PN junction, so that an adjustable space charge region is built in a channel region, and an MFIS (metal-ferroelectric layer-insulating layer-semiconductor) stack is built on the SOI substrate.
According to the novel ferroelectric capacitor, the PN junction depletion region exists in the semiconductor layer, the ferroelectric film can be fully turned over by utilizing a band-to-band tunneling mechanism without large voltage, meanwhile, the depletion region capacitance of the PN junction at one side of the semiconductor is regulated, and the high capacitance-to-switch ratio is obtained while the low power consumption is ensured. The low-power consumption ferroelectric polarization control is realized by utilizing the band-to-band tunneling mechanism, the capacitance of the depletion region of the PN junction is regulated to obviously improve the capacitance-to-switch ratio, and the nonvolatile, low-power consumption and high-switch ratio are considered, so that the capacitor structure is a key improvement of the traditional ferroelectric memcapacitor structure.
In the channel, a PN junction space charge region exists between the p-type region and the n+ heavily doped active region, when a forward pulse voltage is applied to the top electrode layer, the inversion of the p-type region below the top electrode layer is an n-type region, the PN junction space charge region disappears, and at the moment, the total capacitance of the device is the sum of the ferroelectric capacitance and the insulating layer capacitance in parallel connection, and the device is in a high capacitance state. When negative pulse voltage is applied to the top electrode layer, a p-type region below the top electrode layer generates accumulation of holes through band tunneling, a PN junction space charge region is widened, PN junction capacitance is reduced, and at the moment, the total capacitance of the device is the sum of ferroelectric capacitance, insulating layer capacitance and PN junction depletion region capacitance in parallel connection, and is low-state capacitance.
Drawings
FIG. 1 is a schematic diagram showing the structure of an MFIS structure ferroelectric capacitor according to a first embodiment of the present invention;
FIG. 2 is a schematic diagram showing the structure of an MFIS structure ferroelectric capacitor according to a second embodiment of the present invention;
FIG. 3 is a flowchart showing a method of manufacturing a ferroelectric capacitor of MFIS structure according to a first embodiment of the present invention;
FIG. 4 is a schematic diagram showing the structure of each stage of the manufacturing method of the ferroelectric memcapacitor with MFIS structure according to the first embodiment of the present invention;
Fig. 5 shows a capacitance equivalent diagram after activation of a positive pulse voltage and a positive pulse voltage in an MFIS structured ferroelectric capacitor application according to a first embodiment of the present invention.
Detailed Description
In order to make the technical problems, technical schemes and beneficial effects solved by the invention more clear, the invention is further described in detail below with reference to the embodiments.
Examples
The following examples are presented herein to demonstrate preferred embodiments of the present invention. It will be appreciated by those skilled in the art that the techniques disclosed in the examples which follow represent techniques discovered by the inventor to function in the practice of the invention, and thus can be considered to constitute preferred modes for its practice. Those of skill in the art should, in light of the present disclosure, appreciate that many changes can be made in the specific embodiments which are disclosed and still obtain a like or similar result without departing from the spirit or scope of the invention.
In the description of the present invention, it should be noted that the azimuth or positional relationship indicated by the terms "upper", "lower", "vertical", "horizontal", etc. are based on the azimuth or positional relationship shown in the drawings, and are merely for convenience of describing the present invention and simplifying the description, and do not indicate or imply that the apparatus or element referred to must have a specific azimuth, be constructed and operated in a specific azimuth, and thus should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
Numerous specific details of the invention, such as device structures, materials, dimensions, processing techniques and technologies, are set forth in the following description in order to provide a thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details, and various parts of the device may be constructed from materials known to those skilled in the art, or materials having similar functions, which may be developed in the future, unless otherwise indicated herein.
A first embodiment of the present application is shown in fig. 1 as a schematic diagram of a novel ferroelectric memcapacitor based on MFIS structure.
As shown in fig. 1, the novel ferroelectric memcapacitor comprises a p-type SOI substrate, an insulating layer 103, a ferroelectric layer 104, a top electrode layer 105 and a bottom electrode layer 107;
In this embodiment, the p-type SOI substrate is formed by stacking a first Si layer 100, a SiO 2 layer 101, and a second Si layer 102, where the doping type of the second Si layer 102 is p-type.
The SOI substrate comprises a first doped region and a second doped region, the insulating layer 104, the ferroelectric layer 105 and the top electrode layer 105 are arranged on the p-type SOI substrate from bottom to top and cover the first doped region of the substrate, and the doping type of the first doped region is p-type.
The insulating layer 103 is an SiO 2 insulating layer, and the thickness of the insulating layer 103 is preferably any one of 1nm, 2nm, 3nm and 1nm to 3 nm.
The ferroelectric layer 104 is a HfAlO x thin film layer deposited using the material HfZrO x, and in another embodiment of the present invention, the ferroelectric layer 104 is a HfAlO x thin film layer deposited using the material HfAlO x. The thickness of the ferroelectric layer 104 is preferably any integer or non-integer value between 3nm and 12 nm.
The surface of the SOI substrate is not covered with an active region, and the active region is implanted with n-type impurities to form an n-type active region 106, namely a second doped region, and the doping type of the second doped region is n-type.
The bottom electrode layer 107 is located within the second doped region of the SOI substrate and away from the first doped region, i.e., the bottom electrode layer is located at the outer edge of the n-type active region 106 of the SOI substrate.
The channel is located within the second doped region of the substrate, adjacent to the first doped region, i.e., the channel is located inside the bottom electrode layer located inside the n-type active region 106 of the substrate.
The channel doping concentration is any integer or non-integer value that is desirable between 1e13 cm -3～1e17 cm-3.
The top electrode layer 105 and the bottom electrode layer 107 are metal layers formed by sputtering one of metals W, tiN, and the thickness is any integer or non-integer value which is preferable between 10nm and 100 nm.
In some embodiments of the present invention, top electrode layer 105 is a metal W-sputtered W metal layer, bottom electrode layer 107 is a metal W-sputtered W metal layer, in another embodiment of the present invention, top electrode layer 105 is a metal TiN-sputtered TiN metal layer, bottom electrode layer 107 is a metal W-sputtered W metal layer, in another embodiment of the present invention, top electrode layer 105 is a metal W-sputtered W metal layer, bottom electrode layer 107 is a metal TiN-sputtered TiN metal layer, in another embodiment of the present invention, top electrode layer 105 is a metal TiN-sputtered TiN metal layer, and bottom electrode layer 107 is a metal TiN-sputtered TiN metal layer.
A second embodiment of the present application is shown in fig. 2, which is a schematic diagram of a novel ferroelectric memcapacitor based on MFIS structure.
As shown in fig. 2, a novel ferroelectric memcapacitor based on MFIS structure comprises a p-type Si substrate 100, an insulating layer 103, a ferroelectric layer 104, a top electrode layer 105 and a bottom electrode layer 107;
The Si substrate comprises a first doped region and a second doped region, the insulating layer 103, the ferroelectric layer 104 and the top electrode layer 105 are arranged on the p-type Si substrate from bottom to top and cover the first doped region of the substrate, and the doping type of the first doped region is p-type.
The insulating layer 103 is an SiO 2 insulating layer, and the thickness of the insulating layer 103 is preferably any one of 1nm, 2nm, 3nm and 1nm to 3 nm.
The deposited film material used for the ferroelectric layer 104 is one of HfZrO x、HfAlOx, in this example, the ferroelectric layer 104 is a HfAlO x film deposited using material HfZrO x, and in another embodiment of the present invention, the , ferroelectric layer 104 is a HfAlO x film deposited using material HfAlO x. The thickness of the ferroelectric layer 104 is preferably any integer or non-integer value between 3nm and 12 nm.
The surface of the Si substrate is not covered with an active region, and the active region is implanted with n-type impurities to form an n-type active region 106, namely a second doped region, and the doping type of the second doped region is n-type.
The bottom electrode layer 107 is located within the second doped region of the Si substrate and away from the first doped region, i.e., the bottom electrode layer 107 is located at the outer edge of the n-type active region 106 of the Si substrate.
The channel is located within the second doped region of the Si substrate, close to the first doped region, i.e. the channel is located inside the n-type active region 106 of the Si substrate at the bottom electrode layer 107.
The channel doping concentration is any integer or non-integer value that is desirable between 1e13 cm -3～1e17 cm-3.
The top electrode layer 105 and the bottom electrode layer 107 are metal layers formed by sputtering one of metals W, tiN, and the thickness is any integer or non-integer value which is preferable between 10nm and 100 nm.
In some embodiments of the present invention, top electrode layer 105 is a metal W-sputtered W metal layer, bottom electrode layer 107 is a metal W-sputtered W metal layer, in another embodiment of the present invention, top electrode layer 105 is a metal TiN-sputtered TiN metal layer, bottom electrode layer 107 is a metal W-sputtered W metal layer, in another embodiment of the present invention, top electrode layer 105 is a metal W-sputtered W metal layer, bottom electrode layer 107 is a metal TiN-sputtered TiN metal layer, in another embodiment of the present invention, top electrode layer 105 is a metal TiN-sputtered TiN metal layer, and bottom electrode layer 107 is a metal TiN-sputtered TiN metal layer.
Fig. 3 is a flow chart showing a method of manufacturing a novel ferroelectric memcapacitor of MFIS structure according to a first embodiment of the present invention, and fig. 4-a to 4-H are structural diagrams showing the semiconductor device of each step in fig. 3. A method of manufacturing a semiconductor device according to a first embodiment of the present disclosure will be specifically described with reference to fig. 4-a to 4-H.
In step S1, a semiconductor substrate is provided and is cleaned by adopting an RCA cleaning process, specifically, as shown in FIG. 4-A, the semiconductor substrate is a p-type SOI substrate, the SOI substrate is formed by superposing a Si layer 100, a SiO 2 layer 101 and a p-type Si layer 102, the RCA cleaning process comprises the steps of sequentially removing organic matters in NH 4OH-H2O2-H2 O solution, removing a natural oxide layer in HF diluent, removing metal ions in HCl-H 2O2-H2 O solution, controlling the temperature at 75-80 ℃ in the cleaning process, and then rinsing with pure water and drying with nitrogen for standby. In some other embodiments, the semiconductor substrate is a p-type Si substrate.
In the step S2, the upper surface of the SOI substrate is passivated by adopting RTO treatment to form a SiO 2 insulating layer, specifically, the rapid thermal oxidation is carried out in dry oxygen atmosphere at 900 ℃ for 30-60S, so that the upper surface of the SOI substrate is passivated to form a SiO 2 insulating layer 103. The thickness of the formed SiO 2 insulating layer is 1 nm-3 nm, and the structure is shown in figure 4-B.
In step S3, a ferroelectric layer 104 is deposited on the SiO 2 insulating layer 103 by ALD, specifically by alternately pulsing hafnium tetramethyl (TDMA-Hf) and zirconium tetramethyl (TDMA-Zr) as precursors, with water vapor as an oxidizer, at a deposition temperature of 250 ℃, about 0.1 nm per ALD cycle, nitrogen as a carrier gas, a flow rate of 100 sccm, a precursor pulse time of 0.5 seconds, and an inert gas purge time between pulses of 10 seconds. The thin film material of the deposited ferroelectric layer 104 is one of HfZrOx, hfAlOx, the thickness of the ferroelectric layer 104 is 3 nm-12 nm, the structure of the ferroelectric layer 104 after formation is shown in fig. 4-C, and in some other embodiments, alternate pulse hafnium tetramethyl (TDMA-Hf) and aluminum precursor trimethylaluminum (TMA, al (CH 3)3) are used as precursors.
In step S4, an RTP process is performed in an N 2 atmosphere to crystallize the ferroelectric layer 104, specifically, in an N 2 atmosphere, the RTP process temperature is 300 ℃ to 600 ℃ and the time is 30S to 60S, and the structure after the process is shown in fig. 4-D.
In step S5, a top electrode layer 105 is formed on the ferroelectric layer 104 by PVD sputtering metal, specifically, the PVD sputtering vacuum degree is 5×10 -7 Torr, the target sputtering metal is W or TiN in an argon atmosphere, the sputtering power is 100W-300W, the chamber temperature is room temperature, the thickness of the formed metal layer is 10 nm-100 nm, and the structure after the top electrode layer 105 is formed by deposition is shown in fig. 4-E.
In step S6, an active region window on the SOI substrate is formed on the top electrode layer 105 by plasma etching, wherein the etching is performed by using a mixed gas of CF 4 and Ar (CF 4 30 sccm,Ar 20 sccm), the radio frequency power is set to be 200W-300W, the etched structure is shown in FIG. 4-F, and in some other embodiments, photoetching is adopted.
In step S7, an N-type impurity is implanted into the active region window by using an ion implantation method, and an N-type active region 106 is formed by doping, specifically, the ion implantation energy is 30-100 kev, the implantation gas is P + or As + ion beam, and the structure after ion implantation is As shown in fig. 4-G.
In step S8, RTP processing is performed, doping is activated at 900-1050 ℃ for 10-30 seconds.
In step S9, metal W or TiN is sputtered on the window of the N-type active region 106 formed by etching by using PVD, the thickness is 10 nm-100 nm, a bottom electrode layer 107 is formed by partial deposition, a channel is formed on the semiconductor substrate, and the structure is shown as figure 4-H, so that the novel ferroelectric capacitor is obtained.
In some embodiments of the present invention, the top electrode layer 105 is a metal-W sputtered W metal layer, the bottom electrode layer 107 is a metal-W sputtered W metal layer, in another embodiment of the present invention, the top electrode layer 105 is a metal-TiN sputtered TiN metal layer, the bottom electrode layer 107 is a metal-W sputtered W metal layer, in another embodiment of the present invention, the top electrode layer 105 is a metal-W sputtered W metal layer, the bottom electrode layer 107 is a metal-TiN sputtered TiN metal layer, in another embodiment of the present invention, the top electrode layer 105 is a metal-TiN sputtered TiN metal layer, and the bottom electrode layer 107 is a metal-TiN sputtered TiN metal layer.
Fig. 5 shows an application of a novel ferroelectric capacitor based on an MFIS structure according to a fourth embodiment of the present invention, when a positive pulse voltage is applied to the top electrode layer 105, the inversion of the p-type region below the top electrode layer 105 is an n-type region, the space charge region of the PN junction disappears, the total capacitance of the device is the sum of the ferroelectric capacitance and the capacitance of the insulating layer in parallel, as shown in fig. 5 (a), and is in a high capacitance state, when a negative pulse voltage is applied to the top electrode layer 105, the p-type region below the top electrode layer 105 generates accumulation of holes by band tunneling, the space charge region of the PN junction widens, the capacitance of the PN junction decreases, and the total capacitance of the device is the sum of the ferroelectric capacitance, the capacitance of the insulating layer, and the capacitance of the depletion region of the PN junction in parallel, as shown in fig. 5 (B), and is in a low capacitance state.
All documents mentioned in this disclosure are incorporated by reference in this disclosure as if each were individually incorporated by reference. Further, it will be appreciated that various changes and modifications may be made by those skilled in the art after reading the above teachings, and such equivalents are intended to fall within the scope of the application as defined in the appended claims.
Claims (10)
1. The novel ferroelectric memristor based on the MFIS structure is characterized by comprising a substrate, an insulating layer, a ferroelectric layer, a top electrode layer and a bottom electrode layer;
The substrate comprises a first doped region and a second doped region, and the doping type of the first doped region is p-type;
The insulating layer, the ferroelectric layer and the top electrode layer are arranged on the substrate from bottom to top and cover the first doped region of the substrate;
The uncovered area of the surface of the substrate is a second doped area, and the doping type of the second doped area is n-type;
the bottom electrode layer is positioned in the second doped region of the substrate and is far away from the first doped region;
the channel is located in the second doped region of the substrate, adjacent to the first doped region.
2. The novel ferroelectric memcapacitor based on MFIS structure according to claim 1, wherein the substrate is an SOI substrate or a Si substrate.
3. The novel ferroelectric memcapacitor based on MFIS structure according to claim 2, wherein the SOI substrate is formed by stacking a Si layer, a SiO 2 layer and a p-type Si layer.
4. The novel ferroelectric capacitor based on the MFIS structure as claimed in claim 1, wherein the insulating layer is an SiO 2 insulating layer with a thickness of 1 nm-3 nm.
5. The novel ferroelectric memcapacitor based on the MFIS structure as claimed in claim 1, wherein the deposited film material adopted by the ferroelectric layer is one of HfZrO x、HfAlOx, and the thickness of the ferroelectric layer is 3-12 nm.
6. The novel ferroelectric capacitor based on the MFIS structure of claim 1, wherein the top electrode layer and the bottom electrode layer are metal layers formed by sputtering one of metals W, tiN, and the thickness is 10 nm-100 nm.
7. The novel ferroelectric memcapacitor based on MFIS structure according to claim 1, wherein the channel doping concentration is 1e13 cm -3～1e17 cm-3.
8. The novel ferroelectric memristor based on the MFIS structure of claim 1, wherein when a positive pulse voltage is applied to the top electrode layer, the inversion of the p-type region below the top electrode layer is an n-type region, the PN junction space charge region disappears, the total capacitance of the device is the sum of the ferroelectric capacitance and the capacitance of the insulating layer in parallel, and is in a high capacitance state, when a negative pulse voltage is applied to the top electrode layer, the p-type region below the top electrode layer generates accumulation of holes through band tunneling, the PN junction space charge region widens, the PN junction capacitance is reduced, the total capacitance of the device is the sum of the ferroelectric capacitance, the capacitance of the insulating layer and the capacitance of the PN junction depletion region in parallel, and is in a low capacitance state.
9. A method for preparing a novel ferroelectric memcapacitor based on MFIS structure according to any one of claims 1-8, comprising the steps of:
s1, providing a semiconductor p-type substrate;
S2, passivating the upper surface of the semiconductor substrate to form an insulating layer;
s3, depositing a ferroelectric layer on the insulating layer;
s4, processing in an N 2 atmosphere to crystallize the ferroelectric layer;
s5, sputtering metal on the ferroelectric layer, and depositing to form a top electrode layer;
S6, forming an active area window on the substrate through etching on the top electrode layer;
s7, implanting n-type impurities into the active region window in an ion implantation mode, and forming an n-type active region through doping;
s8, activating doping;
and S9, sputtering metal on the n-type active region window, forming a bottom electrode layer by local deposition, and forming a channel by the undeposited part to obtain the novel ferroelectric capacitor.
10. The preparation method of the novel ferroelectric capacitor based on the MFIS structure is characterized in that the thickness of the insulating layer is 1-3 nm, the thickness of the ferroelectric layer is 3-12 nm, the thicknesses of the top electrode layer and the bottom electrode layer are 10-100 nm, and the doping concentration of the channel is 1e13 cm -3～1e17 cm-3.
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| US20010019497A1 (en) * | 2000-02-15 | 2001-09-06 | Yasuhiro Shimada | Semiconductor memory device, method for driving the same and method for fabricating the same |
| US20030228712A1 (en) * | 2002-06-11 | 2003-12-11 | Haochieh Liu | Method of forming ferroelectric memory cell |
| US20050280156A1 (en) * | 2004-06-21 | 2005-12-22 | Sang-Yun Lee | Semiconductor device with base support structure |
| KR20130021884A (en) * | 2011-08-24 | 2013-03-06 | 서울시립대학교 산학협력단 | Mfmis-fet, mfmis-ferroelectric memory device, and methods of manufacturing the same |
| CN114628583A (en) * | 2022-02-25 | 2022-06-14 | 中国科学院微电子研究所 | Ferroelectric memory device and method of manufacturing the same |
| WO2023204767A1 (en) * | 2022-04-20 | 2023-10-26 | National University Of Singapore | Inversion-type ferroelectric capacitive memory |
| CN116963504A (en) * | 2023-05-23 | 2023-10-27 | 西安电子科技大学 | A diode type ferroelectric tunneling junction memory and preparation method |
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| US20010019497A1 (en) * | 2000-02-15 | 2001-09-06 | Yasuhiro Shimada | Semiconductor memory device, method for driving the same and method for fabricating the same |
| US20030228712A1 (en) * | 2002-06-11 | 2003-12-11 | Haochieh Liu | Method of forming ferroelectric memory cell |
| US20050280156A1 (en) * | 2004-06-21 | 2005-12-22 | Sang-Yun Lee | Semiconductor device with base support structure |
| KR20130021884A (en) * | 2011-08-24 | 2013-03-06 | 서울시립대학교 산학협력단 | Mfmis-fet, mfmis-ferroelectric memory device, and methods of manufacturing the same |
| CN114628583A (en) * | 2022-02-25 | 2022-06-14 | 中国科学院微电子研究所 | Ferroelectric memory device and method of manufacturing the same |
| WO2023204767A1 (en) * | 2022-04-20 | 2023-10-26 | National University Of Singapore | Inversion-type ferroelectric capacitive memory |
| CN116963504A (en) * | 2023-05-23 | 2023-10-27 | 西安电子科技大学 | A diode type ferroelectric tunneling junction memory and preparation method |
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