CN120811560A - Gray code synchronization detection method, device, equipment and medium - Google Patents
Gray code synchronization detection method, device, equipment and mediumInfo
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- CN120811560A CN120811560A CN202511076711.1A CN202511076711A CN120811560A CN 120811560 A CN120811560 A CN 120811560A CN 202511076711 A CN202511076711 A CN 202511076711A CN 120811560 A CN120811560 A CN 120811560A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
- H04L7/0033—Correction by delay
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/04—Speed or phase control by synchronisation signals
- H04L7/048—Speed or phase control by synchronisation signals using the properties of error detecting or error correcting codes, e.g. parity as synchronisation signal
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Abstract
本发明公开了一种格雷码同步的检测方法、装置、设备以及介质，涉及通信技术领域。自动提取获取时序参数对应的路径信息和时钟到达信息，避免手动检查出现误差，提高检查精度。根据多个格雷码同步路径的时序参数确定对应的路径延迟时间，基于多个路径延迟时间确定最大路径延迟偏差，确定不同异步寄存器对应的不同比特之间的最大延迟偏差，确保格雷码的单比特变化特性。根据最大路径延迟偏差与预设路径延迟偏差的关系确定格雷码同步策略，在大于的情况下，说明存在潜在的多比特翻转风险，导致FIFO的空满状态判断错误，采用该格雷码同步策略对格雷码生成电路进行调整处理，在降低设计中的数据错误风险，为高可靠性设计提供强有力的保障。
The present invention discloses a detection method, device, equipment and medium for Gray code synchronization, and relates to the field of communication technology. Path information and clock arrival information corresponding to timing parameters are automatically extracted to avoid errors in manual inspection and improve inspection accuracy. The corresponding path delay time is determined according to the timing parameters of multiple Gray code synchronization paths, the maximum path delay deviation is determined based on the multiple path delay times, and the maximum delay deviation between different bits corresponding to different asynchronous registers is determined to ensure the single-bit change characteristics of the Gray code. The Gray code synchronization strategy is determined based on the relationship between the maximum path delay deviation and the preset path delay deviation. If it is greater than, it indicates that there is a potential risk of multi-bit flipping, resulting in an error in the judgment of the empty and full state of the FIFO. The Gray code synchronization strategy is used to adjust the Gray code generation circuit, thereby reducing the risk of data errors in the design and providing a strong guarantee for high-reliability design.
Description
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a method, an apparatus, a device, and a medium for detecting gray code synchronization.
Background
Asynchronous first-in first-Out (FIRST IN FIRST Out, FIFO) adopts Gray code to encode the read-write pointer, ensures that only 1bit change exists between adjacent states, and reduces metastable state risk of cross-clock domain transmission. However, there is a combinational logic delay or wiring bias during the synthesis or wiring process, resulting in multiple bit transitions of gray codes in adjacent clock cycles. Delay deviations between different bits of the gray code synchronous chain are ignored in conventional synthesis and timing analysis tools and static timing analysis, resulting in reduced reliability of the gray code synchronous chain and even risk of data errors.
Therefore, how to check the delay deviation between different bits of the gray code synchronization chain to improve the reliability is needed to be solved by those skilled in the art.
Disclosure of Invention
The invention aims to provide a method, a device, equipment and a medium for detecting Gray code synchronization, which are used for solving the problems that the reliability is reduced and the risk of data errors exists due to delay deviation among different bits synchronized by Gray codes.
In order to solve the technical problems, the invention provides a gray code synchronization detection method which is applied to a plurality of gray code generation circuits, comprises a gray code generation register and an asynchronous register, and adopts different clock parameters, wherein the data output end of the gray code generation register is connected with the data input end of the asynchronous register, and the method comprises the following steps:
acquiring time sequence parameters of a plurality of Gray code synchronous paths formed by Gray code generating registers and asynchronous registers in a plurality of Gray code generating circuits;
Determining corresponding path delay time according to timing sequence parameters of a plurality of Gray code synchronous paths, and determining the maximum path delay deviation based on the plurality of path delay time;
and determining a Gray code synchronization strategy according to the relation between the maximum path delay deviation and the preset path delay deviation, and adjusting the Gray code generation circuit based on the Gray code synchronization strategy.
In one aspect, the timing parameter is used for representing a data propagation time parameter between the Gray code generation register and the asynchronous register, and the acquisition process of the timing parameter comprises the following steps:
Acquiring a first level register of an asynchronous register corresponding to an asynchronous first-in first-out write pointer;
Setting bit width parameters of a Gray code generating register, wherein a plurality of first level registers respectively correspond to one bit width parameter;
and polling and collecting data propagation time parameters from the data output ends of the plurality of Gray code generation registers to the data input ends of the corresponding connected first-level registers to serve as the time sequence parameters.
On the other hand, determining the corresponding path delay time according to the timing parameters of the multiple gray code synchronous paths includes:
Determining a first path delay time of a first clock source passing through a clock input end and a data output end of a current Gray code generation register and reaching a data input end of a corresponding first level register;
determining a first clock delay time corresponding to the first clock source reaching the clock input end of the current Gray code generation register;
determining a second clock delay time for a second clock source to reach a clock input of the first level register;
and determining the path delay time of the Gray code synchronous path corresponding to the current Gray code generator based on the first path delay time, the first clock delay time and the second clock delay time.
On the other hand, the determining process of the first path delay time specifically includes:
capturing a path timing report based on a logic synthesis tool, wherein the path timing report is a timing report of a first path from a first clock source through a clock input end and a data output end of a current Gray code generation register and reaching a data input end of a corresponding first level register;
and extracting the arrival time of the first path according to the path timing report to serve as the first path delay time.
On the other hand, determining the path delay time of the gray code synchronization path corresponding to the current gray code generator based on the first path delay time, the first clock delay time and the second clock delay time includes:
adding the first clock delay time and the first path delay time to obtain a first delay time;
and subtracting the first delay time and the second clock delay time to obtain a second delay time serving as the path delay time.
In another aspect, determining a maximum path delay offset based on a plurality of path delay times includes:
determining a maximum path delay time and a minimum path delay time among the plurality of path delay times;
and determining the maximum path delay deviation according to the maximum path delay time and the minimum path delay time.
On the other hand, determining a gray code synchronization strategy according to the relation between the maximum path delay deviation and the preset path delay deviation, and adjusting the gray code generating circuit based on the gray code synchronization strategy, wherein the method comprises the following steps:
Determining that the plurality of Gray code generating circuits are synchronous under the condition that the maximum path delay deviation is smaller than or equal to the preset path delay deviation;
Determining that potential multi-bit overturn risks exist in the multiple Gray code generating circuits under the condition that the maximum path delay deviation is larger than the preset path delay deviation;
Determining a timing constraint synchronization strategy and a path layout strategy based on the multi-bit flip risk, and adjusting the Gray code generation circuit according to the timing constraint synchronization strategy and/or the path layout strategy;
correspondingly, the determining process of the timing constraint synchronization strategy comprises the following steps:
Determining clock deviation corresponding to a first clock source and the second clock source in advance;
adjusting the clock deviation according to a first adjusting step length to determine the adjusted clock deviation;
determining a new first clock source according to the adjusted clock bias and the second clock source;
Applying a new first clock source to the gray code generation register to implement a timing constraint synchronization strategy;
Correspondingly, the determining process of the path layout strategy comprises the following steps:
Determining a path length between a data output of the gray code generating register and a data input of the first level register;
shortening and adjusting the path length according to the second adjusting step length to obtain an adjusted path length;
and carrying out wiring processing on the first level register and the Gray code generating register according to the adjusted path length so as to realize a path layout strategy.
In order to solve the technical problems, the invention also provides a gray code synchronous detection device which is applied to a plurality of gray code generating circuits and comprises a gray code generating register and an asynchronous register, wherein the gray code generating register and the asynchronous register respectively adopt different clock parameters, the data output end of the gray code generating register is connected with the data input end of the asynchronous register, and the device comprises:
The acquisition module is used for acquiring time sequence parameters of a plurality of Gray code synchronous paths formed by Gray code generation registers and asynchronous registers in a plurality of Gray code generation circuits;
the determining module is used for determining corresponding path delay time according to the time sequence parameters of the multiple Gray code synchronous paths and determining the maximum path delay deviation based on the multiple path delay time;
and the processing module is used for determining a Gray code synchronization strategy according to the relation between the maximum path delay deviation and the preset path delay deviation, and adjusting the Gray code generation circuit based on the Gray code synchronization strategy.
In order to solve the above technical problem, the present invention further provides an electronic device, including:
A memory for storing a computer program;
and the processor is used for realizing the steps of the Gray code synchronous detection method when executing the computer program.
In order to solve the above technical problem, the present invention further provides a computer readable storage medium, where a computer program is stored, where the computer program, when executed by a processor, implements the steps of the gray code synchronization detection method.
The invention has the advantages that firstly, automatic time sequence analysis is carried out in a plurality of Gray code generating circuits, the path information and the clock arrival information corresponding to the time sequence parameters are automatically extracted and acquired based on the time sequence parameters of a plurality of Gray code synchronous paths formed by Gray code generating registers and asynchronous registers in the Gray code circuits, the error of manual inspection is avoided, and the inspection precision is improved. And secondly, determining corresponding path delay time according to time sequence parameters of a plurality of Gray code synchronous paths, wherein the path delay time which spans different clock domains can be effectively identified and quantized through clock period judgment, and the accuracy of data acquisition is improved while data statistics errors are prevented. And determining the maximum path delay deviation based on the plurality of path delay times, and determining the maximum delay deviation among different bits corresponding to different asynchronous registers while realizing data transmission across clock domains so as to ensure the single-bit variation characteristic of Gray codes. And finally, determining a Gray code synchronization strategy according to the relation between the maximum path delay deviation and the preset path delay deviation, and indicating that Gray code synchronization is detected under the condition of being smaller than or equal to the preset path delay deviation, so as to meet the design requirement. Under the condition that the gray code is larger than the gray code, the potential multi-bit overturning risk is indicated to exist, so that the empty and full state of the FIFO is judged to be wrong, the gray code generating circuit is adjusted by adopting the gray code synchronization strategy, the data error risk in the design is reduced, and a powerful guarantee is provided for the high-reliability design. In a word, the delay deviation detection process between different bits of the Gray code synchronous chain is filled, the reliability is improved, and meanwhile, the risk of data errors is avoided.
The acquisition process of the time sequence parameters is based on polling paths from N Gray code generating registers to a first level register, so that automatic acquisition is realized, and the accuracy and the flexibility of the acquisition process are improved. Based on the above three delay time determining processes, the delay time of the gray code synchronous path can be actively identified, so as to calculate the maximum delay deviation of the path and ensure the single bit variation characteristic compared with the conventional STA mode. The logic comprehensive tool is used for grabbing the path time sequence report, and the design is ensured to meet the functional requirements and simultaneously the physical functions can be efficiently realized by optimizing the time sequence, the area and the power consumption. And ensuring that the circuit can normally work at the appointed clock frequency through extracting the time sequence parameters of the path time sequence report. Different strategy adjustment and strategy determination processes for adjusting the Gray code generating circuit based on the Gray code synchronization strategy can reduce the maximum path delay deviation and ensure the reliability of the adjustment process.
In addition, the invention also provides a Gray code synchronous detection device, equipment and medium, which have the same beneficial effects as the Gray code synchronous detection method.
Drawings
For a clearer description of embodiments of the present invention, the drawings that are required to be used in the embodiments will be briefly described, it being apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to the drawings without inventive effort for those skilled in the art.
Fig. 1 is a flowchart of a method for detecting gray code synchronization according to an embodiment of the present invention;
Fig. 2 is a schematic structural diagram of a gray code generating circuit according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a gray code synchronization path according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a determination path of a first path delay time according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a determination path of a first clock delay time according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a determination path of a second clock delay time according to an embodiment of the present invention;
Fig. 7 is a block diagram of a gray code synchronization detection device according to an embodiment of the present invention;
Fig. 8 is a block diagram of an electronic device according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by a person of ordinary skill in the art without making any inventive effort are within the scope of the present invention.
The core of the invention is to provide a method, a device, equipment and a medium for detecting Gray code synchronization, so as to solve the problems of reliability reduction and data error risk caused by delay deviation among different bits synchronized by Gray codes.
In order to better understand the aspects of the present invention, the present invention will be described in further detail with reference to the accompanying drawings and detailed description.
In modern digital systems, asynchronous FIFOs are widely used to solve the problem of multi-bit data exchange between different clock domain modules to avoid metastable problems that may arise from data transfers across clock domains. Because there is no fixed phase relation between different clock domains, directly transmitting multi-bit data may cause metastable state in register sampling, thereby affecting system reliability. Therefore, asynchronous FIFO designs typically employ Gray codes (Gray codes) to encode the read and write pointers to ensure that only 1 bit changes between adjacent states, thereby reducing the risk of metastability when transmitting across clock domains.
In FIFO read-write management, the write pointer needs to be synchronized across clock domains to the read clock domain and vice versa. To ensure data stability, a two-stage register synchronous chain is typically employed to achieve cross-clock domain transfer. However, if the synchronization chain experiences excessive combinational logic delays or wiring deviations during Synthesis (Synthesis) or layout (P & R), multiple bit transitions (i.e., non-single bit changes) of the synchronized gray code during adjacent clock cycles may occur, thereby destroying the empty-full state decision logic of the FIFO. Such anomalies may cause the FIFO read or write pointer to enter an unknown state, ultimately causing serious problems with data overwriting (Overwrite) or reading empty (Underflow).
To prevent the risk of synchronization chain delay mismatch, a "max_delay" constraint is typically applied to the synchronization chain in the design to limit the maximum delay difference between different bit gray code signals. However, existing synthesis and timing analysis tools (e.g., synopsys Design Compiler) typically skip timing checks on paths that are declared asynchronous, which means that even if a "max_delay" constraint is applied, if the constraint is not applied correctly, or the P & R tool does not strictly optimize the layout of the synchronization registers, it may still cause the actual delay of the synchronization chain to exceed the standard, thereby destroying the single-bit hopping characteristic of the gray code. Since the static timing analysis (STATIC TIMING ANALYSIS, STA) tool defaults to skipping analysis of the asynchronous path, such problems may not be directly exposed in conventional timing reports, resulting in potential risks not being discovered in time before streaming.
Currently, conventional static timing analysis mainly focuses on timing convergence (Timing Closure), and there is no special checking mechanism for Maximum delay deviation (Maximum DELAY SKEW) between different bits of a gray code synchronous chain. The simulation method, while exposing part of the timing problem under a specific test vector, does not guarantee full coverage of all timing angles (Corner Cases). The Gray code synchronization detection method provided by the invention can solve the technical problems.
Fig. 1 is a flowchart of a gray code synchronization detection method provided in an embodiment of the present invention, as shown in fig. 1, applied to a plurality of gray code generating circuits, including a gray code generating register and an asynchronous register, and each adopting different clock parameters, where a data output end of the gray code generating register is connected to a data input end of the asynchronous register, and the method includes:
S11, acquiring time sequence parameters of a plurality of Gray code synchronous paths consisting of Gray code generating registers and asynchronous registers in a plurality of Gray code generating circuits;
s12, determining corresponding path delay time according to timing sequence parameters of a plurality of Gray code synchronous paths, and determining the maximum path delay deviation based on the plurality of path delay time;
s13, determining a Gray code synchronization strategy according to the relation between the maximum path delay deviation and the preset path delay deviation, and adjusting the Gray code generation circuit based on the Gray code synchronization strategy.
Specifically, a plurality of gray code generating circuits, fig. 2 is a schematic structural diagram of a gray code generating circuit provided in an embodiment of the present invention, and as shown in fig. 2, there are N bit gray code generating circuits, and one gray code generating circuit includes one gray code generating register and one asynchronous register. The gray code generating register and the asynchronous register have different clock source parameters, which are represented by a first clock source (clk_a) and a second clock source (clk_b) in fig. 2, thus constituting an asynchronous FIFO. The gray code generation register is a register which works under a first clock source and is used for generating gray codes, and input signals are converted into the gray codes through coding logic. The asynchronous register at least comprises a first level register, the asynchronous register is synchronous under a second clock source, the asynchronous register is connected with the Gray code generating register through a logic gate, and the logic gate is used for further processing and synchronizing the Gray code when crossing clock domains, so that the stability of data is ensured. The data output end of the Gray code generating register is connected with the data input end of the asynchronous register.
The method comprises the steps of acquiring time sequence parameters of a plurality of Gray code synchronous paths formed by Gray code generating registers and asynchronous registers in a plurality of Gray code generating circuits, wherein one Gray code generating circuit comprises one Gray code synchronous path, the time sequence parameters comprise data arrival time, clock arrival time and the like, and the time sequence parameters are top-level indexes for measuring whether the combination logic time sequence is converged, and can be time required to arrive or arrival time set by different clock sources.
The plurality of timing parameters in step S12 determine the corresponding path delay time, where the path delay time corresponds to the path delay time under N asynchronous registers corresponding to the same clock source as that in fig. 2, that is, N path delay times, and the maximum path delay deviation is determined in the N path delay times. The determination of the path delay time corresponds to the data propagation time from the data output of the gray code generating register to the data input of the first level register.
In step S13, a gray code synchronization strategy is determined according to a relationship between a maximum path delay deviation and a preset path delay deviation, and when the maximum path delay deviation is greater than the preset path delay deviation, it is indicated that there is a risk of multi-bit jump across clock domains, and an adjustment strategy in the aspect of designing gray code synchronization is required. When the maximum path delay deviation is smaller than or equal to the preset path delay deviation, the fact that multi-bit jump does not exist currently is indicated, namely Gray code synchronization is achieved. The gray code generation circuit is subjected to an adjustment process for the adjustment strategy of gray code synchronization, where the adjustment is such as timing constraint or optimization of layout wiring.
In addition, the detection method provided in this embodiment may be performed after the synthesis and timing analysis tool and the static timing analysis, before, during, or the like, and is not limited herein.
The embodiment of the invention has the beneficial effects that firstly, automatic time sequence analysis is carried out in a plurality of Gray code generating circuits, and the path information and the clock arrival information corresponding to the time sequence parameters are automatically extracted and acquired based on the time sequence parameters of a plurality of Gray code synchronous paths formed by Gray code generating registers and asynchronous registers in the Gray code circuits, so that errors caused by manual inspection are avoided, and the inspection precision is improved. And secondly, determining corresponding path delay time according to time sequence parameters of a plurality of Gray code synchronous paths, wherein the path delay time which spans different clock domains can be effectively identified and quantized through clock period judgment, and the accuracy of data acquisition is improved while data statistics errors are prevented. And determining the maximum path delay deviation based on the plurality of path delay times, and determining the maximum delay deviation among different bits corresponding to different asynchronous registers while realizing data transmission across clock domains so as to ensure the single-bit variation characteristic of Gray codes. And finally, determining a Gray code synchronization strategy according to the relation between the maximum path delay deviation and the preset path delay deviation, and indicating that Gray code synchronization is detected under the condition of being smaller than or equal to the preset path delay deviation, so as to meet the design requirement. Under the condition that the gray code is larger than the gray code, the potential multi-bit overturning risk is indicated to exist, so that the empty and full state of the FIFO is judged to be wrong, the gray code generating circuit is adjusted by adopting the gray code synchronization strategy, the data error risk in the design is reduced, and a powerful guarantee is provided for the high-reliability design. In a word, the delay deviation detection process between different bits of the Gray code synchronous chain is filled, the reliability is improved, and meanwhile, the risk of data errors is avoided.
In some embodiments, the timing parameters are used to characterize data propagation time parameters between the Gray code generating register and the asynchronous register, and the acquisition process of the timing parameters includes:
Acquiring a first level register of an asynchronous register corresponding to an asynchronous first-in first-out write pointer;
Setting bit width parameters of a Gray code generating register, wherein a plurality of first level registers respectively correspond to one bit width parameter;
and polling and collecting data propagation time parameters from the data output ends of the plurality of Gray code generation registers to the data input ends of the corresponding connected first-level registers to serve as time sequence parameters.
It should be noted that the set of first level registers in which the asynchronous FIFO write pointer gray code is synchronized is acquired and stored in the list gray_sync_reg_list. Assuming that the Gray code register bit width is N, each register corresponds to one bit of Gray code, and N elements are in the list, the specific contents are gray_sync_reg_list= [ Gray_sync1_REG [0], gray_sync1_REG [1],. The above-mentioned register list is a key part of the gray code synchronous chain around which the subsequent timing analysis will be spread.
The data path delays of the N registers, i.e. the data propagation time from the Q-terminal of the gray code production register to the D-terminal of the gray code first level register, are calculated by for-loop polling all elements in the list gray_sync_reg_list, respectively. Fig. 3 is a schematic diagram of a Gray code synchronization path according to an embodiment of the present invention, taking an ith path as an example, where the path is gray_gen_reg [ i ]/q— > gray_sync1_reg [ i ]/D.
The acquisition process of the time sequence parameters provided by the embodiment is based on polling paths from N Gray code generating registers to a first level register, so that automatic acquisition is realized, and the accuracy and flexibility of the acquisition process are improved.
In some embodiments, determining the corresponding path delay time from timing parameters of the plurality of gray code synchronized paths includes:
determining a first path delay time of a first clock source passing through a clock input end and a data output end of a current Gray code generation register and reaching a data input end of a corresponding first level register;
Determining a first clock delay time corresponding to the first clock source reaching the clock input end of the current Gray code generation register;
determining a second clock delay time for the second clock source to reach the clock input of the first level register;
And determining the path delay time of the Gray code synchronous path corresponding to the current Gray code generator based on the first path delay time, the first clock delay time and the second clock delay time.
Specifically, determining the data arrival path delay, fig. 4 is a schematic diagram of a first path delay time determination path provided in the embodiment of the present invention, as shown in fig. 4, that is, the first path delay time data_arrival at the data input end of the corresponding first level register gray_sync1_reg [ i ]/D passes through the clock input end gray_gen_reg [ i ]/CP and the data output end gray_gen_reg [ i ]/Q of the ith Gray code generating register from the first clock source (clk_a).
Fig. 5 is a schematic diagram of a determining path of the first clock delay time according to an embodiment of the present invention, as shown in fig. 5, that is, the first clock delay time gray_gen_cp_delay corresponding to the clock input terminal gray_gen_reg [ i ]/CP of the i-th Gray code generating register gray_gen_reg [ i ] passes through the first clock source.
Fig. 6 is a schematic diagram showing a determining path of the second clock delay time according to the embodiment of the present invention, as shown in fig. 6, that is, the arrival time data_capture_clk_delay of the clock input port gray_sync1_reg [ i ]/CP of the i-th Gray code generating register gray_sync1_reg [ i ] from the second clock source (clk_b).
And determining the path delay time of the Gray code synchronous path corresponding to the final ith Gray code generator based on the determined three delay times. The calculation process may be addition processing, subtraction processing, or the like, and is not limited thereto.
Compared with the conventional STA method, the method and the device for determining the path delay time based on the three delay time can actively identify the delay time of the Gray code synchronous path so as to calculate the maximum path delay deviation and ensure the single-bit change characteristic.
In some embodiments, the determining of the first path delay time specifically includes:
capturing a path timing report based on a logic synthesis tool, wherein the path timing report is a timing report of a first path from a first clock source through a clock input end and a data output end of a current Gray code generation register and reaching a data input end of a corresponding first level register;
And extracting the arrival time of the first path according to the path timing report to serve as the first path delay time.
Based on the above embodiments, a logic synthesis tool (e.g., a Design Compiler (DC) tool) is used to capture a path timing report, i.e., a timing report of a path delay. Logic synthesis tools are tools that convert design intent into a circuit netlist that can be used for place and route. Timing reports are documents or data files used in digital integrated circuit design to evaluate and verify circuit Timing performance. It provides detailed information about each timing path in the circuit, including delay, clock information, etc., helping the designer ensure that the circuit will function properly at the specified clock frequency.
And extracting the arrival time of the first path according to the path time sequence report to be used as the first path delay time, wherein the first path is a path corresponding to an arrow in fig. 4. The script instructions by the tool command language script (Tool Command Language script, TCL) may be described as set data_arrival_attribute [ get_time_path-to $gray_sync_reg/D ] arrival ].
Similarly, in determining the first clock delay time and the second clock delay time, the method is realized based on the corresponding path timing report. The TCL script instructions are described as set gray_gen_reg_cp [ get_attribute [ get_time_path-to $gray_sync_reg/D ] startpoint;
Set gray_gen_cp_delay[get_attribute[get_timing_path-to$gray_gen_reg_cp-from[get_clocks $gray_gen_reg_clk]]arrival] A first clock delay time is obtained.
data_capture_clk_delay[get_attribute[get_timing_path-to$gray_sync_reg/CP-from[get_clocks $gray_sync_reg_clk]]arrival] A second clock delay time is obtained.
The path time sequence report is grasped through the logic comprehensive tool, and the design can be ensured to meet the functional requirements and simultaneously realize the physical functions with high efficiency by optimizing the time sequence, the area and the power consumption. And ensuring that the circuit can normally work at the appointed clock frequency through extracting the time sequence parameters of the path time sequence report.
In some embodiments, determining the path delay time of the gray code synchronization path corresponding to the current gray code generator based on the first path delay time, the first clock delay time, and the second clock delay time includes:
Adding the first clock delay time and the first path delay time to obtain a first delay time;
And subtracting the first delay time and the second clock delay time to obtain a second delay time serving as a path delay time.
The first delay time is obtained by adding the first clock delay time and the first path delay time, the second delay time is obtained by subtracting the second clock delay time from the first delay time, and the data path delay of Gray_gen_REG [ i ]/Q- (Gray_Sync 1_REG [ i ]/D) is calculated as the path delay time.
The use of the TCL script instruction can be described as set SLack [ expr { $grain_gen_cp_delay + $data_arrival- $data_capture_clk_latency } ].
The specific algorithm processing based on the three delay times provided in the embodiment ensures the accuracy of determining the path delay time under each gray code synchronous path, and is convenient for the subsequent calculation of delay deviation.
In some embodiments, determining the maximum path delay offset based on the plurality of path delay times includes:
determining a maximum path delay time and a minimum path delay time among the plurality of path delay times;
And determining the maximum path delay deviation according to the maximum path delay time and the minimum path delay time.
It should be noted that, the data path delay times of the N first level registers are ordered, the maximum path delay time and the minimum path delay time are extracted, and the maximum path delay deviation is determined by the maximum path delay time and the minimum path delay time, so as to reflect the maximum propagation delay difference between different bits of the gray code synchronous path. With respect to the present embodiment, only the path between the first level register and the gray code generating register is determined, the second level register and the first level register belong to the same clock source, and the path deviation between the two is almost small, and is insufficient to influence the gray code multiple bit transitions, so only the path between the first level register and the gray code generating register is considered.
The determining process for determining the maximum path delay deviation based on the plurality of path delay times provided by the embodiment can reflect the maximum propagation delay difference between different bits of the Gray code synchronous paths, and improves the judgment accuracy and reliability of Gray code synchronization.
In some embodiments, determining a gray code synchronization policy according to a relationship between a maximum path delay deviation and a preset path delay deviation, and adjusting the gray code generation circuit based on the gray code synchronization policy, including:
Determining that the plurality of Gray code generating circuits are synchronous under the condition that the maximum path delay deviation is smaller than or equal to the preset path delay deviation;
under the condition that the maximum path delay deviation is larger than the preset path delay deviation, determining that potential multi-bit overturning risks exist in the multiple Gray code generating circuits;
Determining a timing constraint synchronization strategy and a path layout strategy based on the multi-bit flip risk, and adjusting the Gray code generation circuit according to the timing constraint synchronization strategy and/or the path layout strategy;
correspondingly, the determining process of the timing constraint synchronization strategy comprises the following steps:
determining clock deviation corresponding to the first clock source and the second clock source in advance;
Adjusting the clock deviation according to the first adjusting step length to determine the adjusted clock deviation;
Determining a new first clock source according to the adjusted clock deviation and the second clock source;
Applying a new first clock source to the gray code generation register to implement a timing constraint synchronization strategy;
correspondingly, the determining process of the path layout strategy comprises the following steps:
Determining a path length between a data output of the gray code generating register and a data input of the first level register;
shortening and adjusting the path length according to the second adjusting step length to obtain the adjusted path length;
And carrying out wiring processing on the first grade register and the Gray code generating register according to the adjusted path length so as to realize a path layout strategy.
Specifically, under the condition that the maximum path delay deviation is larger than the preset path delay deviation, determining that the multiple gray code generating circuits have potential multi-bit overturn risks. Based on such a rollover risk, two strategies, one timing constraint synchronization strategy and one path layout strategy, can be determined. And adjusting the Gray code generating circuit according to one strategy or a combination mode of the two strategies.
For a timing constraint synchronization strategy, clock deviations of the first clock source and the second clock source are predetermined, and the clock deviations are adjusted according to the first adjustment step length, so that the clock deviations can be enlarged to determine a new first clock source. After the first clock source is applied to the Gray code generation register, a new round of corresponding path delay time is acquired.
For the path layout strategy, the path length between the data output end of the gray code generating register and the data input end of the first level register needs to be determined, and shortening processing is performed on the path length according to the second adjustment step length so as to shorten the wiring length corresponding to the path between the gray code generating register and the first level register, so that wiring processing is performed.
The preset path delay deviation may be set as a percentage of the normal clock period, for example, 0.9, or may be other parameters, which are not limited herein, and may be modified according to practical situations.
In some embodiments, the adjusting the gray code generating circuit according to the timing constraint synchronization policy and the path layout policy includes:
Acquiring the adjustment times in the time sequence constraint synchronization strategy, and determining that the time sequence constraint synchronization strategy is invalid when the adjustment times reach the preset adjustment times and the new maximum path delay deviation under each adjustment time is larger than the preset path delay deviation;
and applying a new first clock source with the first adjustment times in the time sequence constraint synchronization strategy to the Gray code generation register, performing wiring processing by utilizing the path length which is adjusted for the first time in the path layout strategy to obtain a new maximum path delay deviation, and returning to the step of determining the Gray code synchronization strategy according to the relation between the maximum path delay deviation and the preset path delay deviation.
Specifically, considering that the processing cost of the layout and the wiring is relatively high, the adjustment of the timing constraint synchronization strategy is preferentially performed, and after the adjustment is performed for multiple times, and the adjustment times reach the preset adjustment times, and the maximum path delay deviation under each adjustment time is larger than the preset path delay deviation, the deviation corresponding to each adjustment is indicated to have multi-bit jump. Therefore, a new first clock source corresponding to the first adjustment number of the timing constraint synchronization policy needs to be returned, and the routing process is performed by using the path layout policy and the path length adjusted for the first time, where the adjustment process is the same as the above embodiment, and the limitation is not limited.
The two strategies are used in a mixed mode, under the condition that the time sequence constraint synchronization strategy is invalid is considered, on the basis, wiring processing is conducted on the basis of a new first clock source and the path length adjusted for the first time in the time sequence constraint synchronization strategy, a new maximum path delay deviation is obtained, and the potential multi-bit overturning risk is avoided.
In this embodiment, different policy adjustment and policy determination processes for adjusting the gray code generating circuit based on the gray code synchronization policy reduce the maximum path delay deviation and ensure the reliability of the adjustment process.
The invention further discloses a Gray code synchronization detection device corresponding to the method, and FIG. 7 is a structural diagram of the Gray code synchronization detection device provided by the embodiment of the invention. As shown in fig. 7, the gray code generating circuit comprises a gray code generating register and an asynchronous register, and each uses different clock parameters, wherein the data output end of the gray code generating register is connected with the data input end of the asynchronous register, and the gray code synchronous detecting device comprises:
An acquiring module 11, configured to acquire timing parameters of a plurality of gray code synchronous paths formed by a gray code generating register and an asynchronous register in a plurality of gray code generating circuits;
a determining module 12, configured to determine corresponding path delay times according to timing parameters of the multiple gray code synchronous paths, and determine a maximum path delay deviation based on the multiple path delay times;
And the processing module 13 is used for determining a gray code synchronization strategy according to the relation between the maximum path delay deviation and the preset path delay deviation, and adjusting the gray code generation circuit based on the gray code synchronization strategy.
Since the embodiments of the device portion correspond to the above embodiments, the embodiments of the device portion are described with reference to the embodiments of the method portion, and are not described herein.
For the description of the gray code synchronization detection device provided by the present invention, refer to the above method embodiment, and the present invention is not repeated herein, and has the same beneficial effects as the gray code synchronization detection method.
Fig. 8 is a block diagram of an electronic device according to an embodiment of the present invention, as shown in fig. 8, where the device includes:
A memory 21 for storing a computer program;
a processor 22 for implementing the steps of the method for detecting gray code synchronization when executing the computer program.
The electronic device provided in this embodiment may include, but is not limited to, a smart phone, a tablet computer, a notebook computer, a desktop computer, or the like.
Processor 22 may include one or more processing cores, such as a 4-core processor, an 8-core processor, or the like, among others. The Processor 22 may be implemented in hardware as at least one of a digital signal Processor (DIGITAL SIGNAL Processor, DSP), a Field-Programmable gate array (Field-Programmable GATE ARRAY, FPGA), and a Programmable logic array. The processor 22 may also include a main processor, which is a processor for processing data in an awake state, also referred to as a central processor (Central Processing Unit, CPU), and a coprocessor, which is a low-power processor for processing data in a standby state. In some embodiments, the processor 22 may be integrated with an image processor (Graphics Processing Unit, GPU) that is responsible for rendering and rendering of the content that the display screen is required to display. In some embodiments, the processor 22 may also include an artificial intelligence (ARTIFICIAL INTELLIGENCE, AI) processor for processing computing operations related to machine learning.
Memory 21 may include one or more computer-readable storage media, which may be non-transitory. Memory 21 may also include high-speed random access memory, as well as non-volatile memory, such as one or more magnetic disk storage devices, flash memory storage devices. In this embodiment, the memory 21 is at least used for storing a computer program 211, where the computer program can implement the relevant steps of the gray code synchronization detection method disclosed in any of the foregoing embodiments after being loaded and executed by the processor 22. In addition, the resources stored in the memory 21 may further include an operating system 212, data 213, and the like, and the storage manner may be transient storage or permanent storage. Operating system 212 may include Windows, unix, linux, among other things. The data 213 may include, but is not limited to, data related to a method of detecting gray code synchronization, and the like.
In some embodiments, the electronic device may further include a display screen 23, an input-output interface 24, a communication interface 25, a power supply 26, and a communication bus 27.
Those skilled in the art will appreciate that the structure shown in fig. 8 is not limiting of the electronic device and may include more or fewer components than shown.
The processor 22 invokes the instructions stored in the memory 21 to implement the method for detecting gray code synchronization provided in any of the above embodiments.
For the description of the electronic device provided by the present invention, refer to the above method embodiment, and the present invention is not repeated herein, which has the same beneficial effects as the above gray code synchronization detection method.
Further, the present invention also provides a computer readable storage medium, on which a computer program is stored, which when executed by the processor 22 implements the steps of the above-mentioned gray code synchronization detection method.
It will be appreciated that the methods of the above embodiments, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored on a computer readable storage medium. Based on this understanding, the technical solution of the present invention may be embodied essentially or in part or in whole or in part in the form of a software product stored in a storage medium for performing all or part of the steps of the method according to the embodiments of the present invention. The storage medium includes a U disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a magnetic disk, an optical disk, or other various media capable of storing program codes.
For an introduction to a computer readable storage medium provided by the present invention, please refer to the above method embodiment, the present invention is not described herein, and has the same advantages as the above gray code synchronization detection method.
The method, the device, the equipment and the medium for detecting Gray code synchronization provided by the invention are described in detail. In the description, each embodiment is described in a progressive manner, and each embodiment is mainly described by the differences from other embodiments, so that the same similar parts among the embodiments are mutually referred. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section. It should be noted that it will be apparent to those skilled in the art that the present invention may be modified and practiced without departing from the spirit of the present invention.
It should also be noted that in this specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises an element.
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