CN120803990A

CN120803990A - Test circuit and electronic equipment

Info

Publication number: CN120803990A
Application number: CN202410430373.6A
Authority: CN
Inventors: 戴奇峰; 王能; 罗宇晨
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2024-04-10
Filing date: 2024-04-10
Publication date: 2025-10-17

Abstract

The present application provides a test circuit and electronic device, the test circuit including a main chip, a switch circuit module, and a USB interface, the main chip including a JTAG module and a first IO module, the switch circuit module including a second IO module, a first USB module, and a first switch, the N pins of the JTAG module being connected to the N pins of the USB interface via the first IO module, the second IO module, the first switch, and the first USB module, wherein the test circuit is configured to execute: upon detecting entry into a test mode, controlling the first switch to close so that the JTAG module is connected to a test device via the switch circuit module and the USB interface, thereby performing a JTAG test. The present application can reuse the USB interface of an electronic device as an external interface for JTAG debugging, and JTAG debugging does not rely on a physical card holder, so the achievable scenarios for JTAG debugging are more extensive.

Description

Test circuit and electronic equipment

Technical Field

The present application relates to the field of computer technologies, and in particular, to a test circuit and an electronic device.

Background

Joint test workgroup (Joint Test Action Group, JTAG) technology refers to the use of a JTAG debugger connected to an external interface of a chip to scan various units inside the chip to write or read the state of scan registers, thereby enabling testing and debugging of the chip. Currently, the external debug interface of the main chip of the terminal may be connected to a contact of an entity card holder (for example, a secure digital card (secure digital memory card) or a subscriber identity module (Subscriber Identity Module, SIM) card holder), through which the main chip is tested and debugged, but as the terminal is developed, the entity card holder may not be configured, for example, when the entity SIM card of the terminal is replaced by an electronic SIM card (eSIM), the entity card holder may be cancelled, and thus, the contact cannot be continuously integrated in the entity card holder, resulting in that JTAG debugging of the terminal cannot be performed through the contact of the entity card holder.

Disclosure of Invention

The application discloses a test circuit and electronic equipment, which can reuse a USB interface of the electronic equipment as an external interface for JTAG debugging, wherein JTAG debugging does not depend on an entity card seat, and the JTAG debugging has wider realizable scene.

In a first aspect, an embodiment of the present application provides a test circuit, where the circuit includes a main chip, a switch circuit module and a universal serial bus USB interface, the main chip includes a joint test workgroup JTAG module and a first input/output IO module, the switch circuit module includes a second input/output IO module, a first USB module and a first switch, N pins of the JTAG module are connected to a first end of the first IO module, a second end of the first IO module is connected to a first end of the second IO module, a second end of the second IO module is connected to a first end of the first switch, a second end of the first switch is connected to a first end of the first USB module, a second end of the first USB module is connected to N pins of the USB interface, the USB interface is connected to a test device, and N is a positive integer, where the test circuit is configured to perform:

When the first switch is closed, the JTAG module is connected with the testing device through the switch circuit module and the USB interface;

And when the first switch is closed, the JTAG module performs JTAG test through the test device.

In the above circuit, only the USB interface of the electronic device can be reused as the external interface for testing (i.e., JTAG debugging) without using/passing through the contacts of the physical card holder, and when the electronic device is a foldable device, the USB interface and the SOC are both located at one side of the rotating shaft, so that the thickness of the rotating shaft of the foldable device is reduced, which is more beneficial to the thin design of the rotating shaft, and the aesthetic feeling is improved. In addition, the circuit leads out N debugging signal wires from N pins on the JTAG module and is connected to the switch circuit module, so that JTAG test can be realized based on the USB interface.

In one possible implementation, the test circuit is powered by a first battery, and the switch circuit module is a charging module for charging the first battery.

In the circuit, the test circuit can be powered by the first battery or connected with the first battery, and when the switch circuit module is a charging module, the test circuit multiplexes the original charging module of the electronic equipment, so that devices can not be newly added, and the cost of the electronic equipment is saved.

In a possible implementation manner, the N pins of the JTAG module include a serial clock SWCLK pin and a serial data input/output SWDIO pin, the N pins of the USB interface include a data positive signal line DP pin and a data negative signal line DM pin, and when the first switch is closed, the SWCLK pin and the SWDIO pin are respectively connected to the DP pin and the DM pin through the first switch, so that the JTAG module is connected to the test device through the switch circuit module and the USB interface;

the test circuit is configured to perform:

when the first switch is closed, the JTAG module performs JTAG serial debugging through the SWCLK pin, the SWDIO pin and the testing device.

In the circuit, two debugging signal wires are led out from the SWCLK pin and the SWDIO pin of the JTAG module and are connected to the switch circuit module, so that JTAG serial debugging of the electronic equipment can be realized based on the USB interface, an additional conversion chip is not required to be added, and the cost of the electronic equipment is saved.

In a possible implementation manner, the switch circuit module further includes a configuration pin CC module, the CC module is connected to a CC pin of the USB interface, and the test circuit is configured to perform:

And when the CC module receives the CC signal sent by the USB interface, detecting whether the test mode is entered or not according to the CC signal.

In one possible implementation manner, the main chip includes a second USB module, N pins of the USB interface include a DP pin and a DM pin, the DP pin and the DM pin are both connected to the second USB module, and the test circuit is further configured to perform:

When the test mode is not entered, the first switch is controlled to be turned off;

when the first switch is disconnected, the USB interface respectively sends a DP signal and a DM signal to the second USB module through the DP pin and the DM pin, and the DP signal and the DM signal are used for identifying a charging private protocol.

In the above circuit, when the test mode is entered, the DP pin and the DM pin of the USB interface may be used for JTAG test, and when the test mode is not entered, the DP pin and the DM pin of the USB interface may be used for the main chip to identify the charging proprietary protocol, so as to implement the data transmission function between the USB interface and the main chip.

In one possible implementation, when the JTAG module performs JTAG testing through the testing device, the JTAG module and the testing device transmit signals of a first protocol through the switch circuit module and the USB interface.

In the above circuit, the switch circuit module is not used for converting the signal protocol, but only serves as an intermediate module to forward the signal, that is, the JTAG module, the switch circuit module and the USB interface transmit the same type of signal (for example, the first protocol described above), but the conversion chip converts the protocol, so that the module for converting the signal protocol in the conversion chip is complex, has a larger area, and the device structure of the switch circuit module is simpler, has a smaller area, and saves the cost of the electronic device.

In one possible implementation manner, the switch circuit module includes a USB switch circuit module and an interface chip, the USB switch circuit module includes the second IO module, the first USB module, and the first switch, an input end of the interface chip is connected to a CC pin of the USB interface, an output end of the interface chip is connected to the USB switch circuit module, and the test circuit is configured to perform:

when the interface chip receives a CC signal sent by the USB interface, detecting whether the test mode is entered or not according to the CC signal;

when the test mode is detected to be entered, the interface chip sends a first control signal to the USB switch circuit module, wherein the first control signal is used for controlling the first switch to be closed;

When the test mode is not entered, the interface chip sends a second control signal to the USB switch circuit module, wherein the second control signal is used for controlling the first switch to be disconnected.

In the above circuit, the interface chip and the USB switch circuit module may be integrated together, where the switch circuit module is, for example, a charging module, and the interface chip and the USB switch circuit module may also exist independently, where the interface chip controls a state (for example, on or off) of a first switch in the USB switch circuit module according to the received CC signal, so that the JTAG module is connected to the testing device through the first switch and the USB interface, to implement the JTAG test.

In a possible implementation manner, the N pins of the JTAG module include a SWCLK pin and a SWDIO pin, the N pins of the USB interface include a DP pin and a DM pin, and when the first switch is turned on, the SWCLK pin and the SWDIO pin are connected to the DP pin and the DM pin through the first switch, respectively, so that the JTAG module is connected to the test device through the switch circuit module and the USB interface;

the test circuit is configured to perform:

When the first switch is closed, the JTAG module performs JTAG serial test through the SWCLK pin, the SWDIO pin and the test device.

In one possible implementation manner, the switch circuit module further includes an auxiliary pin SBU module and a second switch, the N pins of the JTAG module include a test clock signal TCK pin, a test mode state TMS pin, a test data input TDI pin, and a test data output TDO pin, the N pins of the USB interface include a DP pin, a DM pin, an auxiliary SBU1 pin, and an SBU2 pin, wherein the second end of the first USB module is connected to the DP pin and the DM pin, the first end of the SBU module is connected to the SBU1 pin and the SBU2 pin, the second end of the SBU module is connected to the first end of the second switch, the second end of the second switch is connected to the second end of the second IO module, and the test circuit is configured to perform:

When the first switch and the second switch are closed, the TCK pin, the TMS pin, the TDI pin and the TDO pin are respectively connected with the DP pin, the DM pin, the SBU1 pin and the SBU2 pin through the first switch and the second switch, so that the JTAG module is connected with the testing device through the switch circuit module and the USB interface;

When the first switch and the second switch are closed, the JTAG module performs JTAG parallel test through the TCK pin, the TMS pin, the TDI pin, the TDO pin, and the test device.

In the above circuit, compared with two debug signal lines of JTAG serial debugging, JTAG parallel debugging is to draw out four debug signal lines from JTAG module, and connect to the switch circuit module (including USB switch circuit module and interface chip), can realize JTAG parallel debugging of the electronic device based on USB interface like this, namely can realize JTAG debug under different modes based on different pin connection modes, make JTAG debug can realize the scene more extensive.

In a second aspect, the application provides an electronic device comprising a transceiver, a processor and a memory, the memory being for storing a computer program, the processor being for invoking the computer program for executing the test circuit in any one of the possible implementations of the first aspect.

In a third aspect, the present application provides an electronic device comprising one or more processors and one or more memories. The one or more memories are coupled to the one or more processors, the one or more memories being operable to store computer program code comprising computer instructions that, when executed by the one or more processors, cause the electronic device to perform the test circuitry in any of the possible implementations of the first aspect described above.

In a fourth aspect, the application provides a computer storage medium storing a computer program which, when executed by a processor, implements a test circuit in performing any one of the possible implementations of the above aspects.

In a fifth aspect, the application provides a computer program product which, when run on an electronic device, causes the electronic device to execute the test circuit in any of the possible implementations of the first aspect.

In a sixth aspect, the present application provides an electronic device comprising means or apparatus for performing the method or apparatus described in any implementation manner of the first aspect of the present application. The electronic device is, for example, a chip.

Drawings

The drawings to which the present application is applied are described below.

FIG. 1 is a pin-out schematic diagram of a JTAG parallel test provided by the present application;

FIG. 2 is a pin-out schematic diagram of a JTAG serial test provided by the present application;

Fig. 3 is a schematic structural diagram of a card holder and a card holder of an electronic device according to the present application;

FIG. 4 is a schematic diagram of a card holder, and a structure of the card holder and the card holder according to the present application;

FIG. 5 is a circuit diagram of JTAG debug of an electronic device provided by the present application;

FIG. 6 is a schematic diagram of a foldable electronic device provided by the present application;

FIG. 7 is a schematic diagram of a Type-C interface in an electronic device according to the present application;

FIG. 8 is a schematic diagram of a Type-C interface provided by the present application;

FIG. 9 is a circuit diagram of a USB interface and a main chip of an electronic device according to the present application;

FIG. 10 is a circuit diagram illustrating JTAG debug of yet another electronic device provided by the present application;

FIG. 11 is two views of an electronic device provided by the present application;

Fig. 12 is a schematic diagram of a hardware structure of an electronic device according to the present application;

fig. 13 is a circuit configuration diagram of an electronic device provided by the present application;

Fig. 14 is a circuit configuration diagram of still another electronic device provided by the present application;

Fig. 15 is a circuit configuration diagram of still another electronic device provided by the present application.

Detailed Description

The technical scheme in the embodiment of the application will be described below with reference to the accompanying drawings. In the description of the embodiment of the present application, unless otherwise indicated, "/" means or, for example, a/B may represent a or B, and "and/or" in the text is merely an association relationship describing an association object, which means that three relationships may exist, for example, a and/or B, and that three cases of a alone, a and B together, and B alone exist, and further, in the description of the embodiment of the present application, "a plurality" means two or more.

The terms "first," "second," and the like, are used below for descriptive purposes only and are not to be construed as implying or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature, and in the description of embodiments of the application, unless otherwise indicated, the meaning of "a plurality" is two or more.

Joint test workgroup (Joint Test Action Group, JTAG) technology refers to the use of a JTAG debugger connected to an external interface of a chip to scan various units inside the chip to write or read the state of scan registers, thereby enabling testing and debugging of the chip. JTAG technology mainly adds a shift register unit inside the tested device near the input/output (I/O) pins of the core circuit, and during testing, the shift register unit can control the states of the input pins, such as applying test stimulus, and reading the states of the output pins to retrieve test response, i.e. realize testing and debugging of the tested device. During testing, the shift register cells may implement a "virtual probe" like function so that the circuitry of the device/device under test is not affected by these newly added shift register cells during normal operation. JTAG testing typically uses a standard test connection Port (TEST ACCESS Port, TAP), which is a universal Port through which all data registers (DATA REGISTER, DR) and instruction registers (Instruction Register, IR) provided by the chip are accessible.

The JTAG Test modes may include JTAG parallel testing (which may be referred to as conventional JTAG testing) and JTAG serial testing, wherein under JTAG parallel testing, the chip needs to draw four pins, such as a Test Clock signal pin (TCK), a Test mode status pin (Test Mode Selection pin, TMS), a Test data input pin (Test Data Input pin, TDI), and a Test data output pin (Test Data Output pin, TDO), where TCK is a JTAG Test reference Clock provided by a JTAG debugger to the device under Test. TMS can be used for selecting a test mode, and is output to a tested device by a JTAG debugger, when the TCK signal is in a rising edge, the tested device can sample the TMS signal and judge whether the TMS signal is in a normal mode or a JTAG test mode currently according to a sampling result, for example, TMS= "0" is in the normal mode, and TMS= "1" is in the JTAG test mode. The TDI of the JTAG debugger may be connected to the TDO of the device under test, and the JTAG debugger may sample the TDI signal while the TCK signal is on the rising edge. The TDO of the JTAG debugger may be connected to the TDI of the device under test, and the JTAG debugger may output the TDO signal when the TCK signal is on a falling edge. Optionally, the chip may also draw out an nTRST pin for resetting the TAP state machine during power-up, so as to ensure normal operation of the chip. Fig. 1 illustrates a pin-out schematic diagram of JTAG parallel testing, and fig. 1 may include 10 pins, for example, 1 to 10 pins, where 1 pin is nTRST pin, 3 pin is TDI pin, 5 pin is TDO pin, 7 pin is TMS pin, 9 pin is TCK pin, and 2, 4, 6, 8, and 10 pins are all grounded.

Under JTAG serial test, the chip needs to draw out two pins, such as a serial Clock pin (SERIAL WIRE Clock pin, SWCLK) and a serial data Input/Output pin (SERIAL WIRE DATA Input/Output pin, SWDIO), where SWCLK is a serial JTAG test Clock provided by a JTAG debugger to the device under test. SWDIO may be used to transfer data signals bi-directionally, for example SWDIO may transfer 1 bit (bit) of data when SWCLK is on a rising edge. Optionally, the chip may also lead out a serial debug Output pin (SWO), which may be used to Output debug information of the chip. Fig. 2 illustrates a pin-out schematic diagram of a JTAG serial test, and fig. 2 may include 6 pins, such as a VCC pin, two GND pins, SWDIO pins, a SWCLK pin, and a SWO pin.

Fig. 3 illustrates a schematic structure of a card holder and a card holder of an electronic device, where the electronic device may include the card holder, the card holder may be used to insert the card holder, and the card holder may be used to place an SD card and/or a SIM card, as shown in fig. 3. At present, the external debug interface of the main chip of the terminal may be connected to a contact of an entity card holder (for example, SD card or SIM card holder), for example, a contact on the card holder shown in fig. 3, through which the main chip is tested and debugged, but as the entity SIM card of the terminal is replaced by sSIM, the entity card holder is also completely removed, so that the contact cannot be continuously integrated in the entity card holder, and thus JTAG debug cannot be performed on the terminal through the contact of the entity card holder. Examples of the card holder, and the structure of the card holder and the card holder may be seen in fig. 4 (a), fig. 4 (B), and fig. 4 (C), and a circuit connection diagram of JTAG debug performed by the physical card holder may be seen in fig. 5.

Fig. 5 illustrates a circuit diagram of JTAG debugging of an electronic device, which may include a main Chip/System On Chip (SOC) and a SIM card module, as shown in fig. 5, where the SOC may include a JTAG module, an IO module, and an SD/sim_io module, and the JTAG module may be connected with an on-board test point through the IO module, and the on-board test point may be used for JTAG debugging of an independent Chip. The JTAG module may be used for JTAG debugging. The JTAG module may be connected to the SD/SIM_IO module, and the SD/SIM_IO module may include a switch circuit that may be used to switch a circuit between the JTAG module and the SD/SIM_IO module, for example, may switch to connect to a SIM card socket circuit when detecting that the SIM card is inserted, may switch to connect to a SD card socket circuit when detecting that the SD card is inserted, and may switch to connect to the JTAG module when not detecting that the SIM card is inserted, at this time, the JTAG module may be connected through the SD/SIM_IO module and the SIM card module to realize JTAG debugging of the electronic device through contacts on the SIM card module. In one embodiment, when conventional JTAG debug is performed, JTAG modules may be connected to SIM card modules through four pins TCK, TMS, TDI, TDO shown in FIG. 1, which may be understood as being connected between JTAG modules and SD/SIM_IO modules, and SD/SIM_IO modules and SIM card modules through four signal lines. In another embodiment, when serial JTAG debug is performed, the JTAG module may be connected to the SIM card module through two pins SWDIO and SWCLK shown in fig. 2, which may be understood as the connection between the JTAG module and the SD/sim_io module, and the SD/sim_io module and the SIM card module through two signal lines.

In addition, when the electronic device is a foldable electronic device, the JTAG module and the SIM card module of the SOC are respectively located at two sides of the rotating shaft, signal lines between the JTAG module and the SIM card module need to be connected from one side to the other side of the rotating shaft, and as a specific example, see the foldable electronic device shown in fig. 6, a shaft-penetrating flexible circuit board (Flexible Printed Circuit, FPC) in fig. 6 is connected from a main board circuit board (Printed Circuit Board, PCB) to an auxiliary board PCB, the main board PCB and the auxiliary board PCB are respectively located at two sides of the rotating shaft, the JTAG module may be located on the main board PCB, and the SIM card module may be located on the auxiliary board PCB, so that the FPC at the rotating shaft may become thicker and wider due to bearing the signal lines, which results in an increase in thickness of the rotating shaft, and affects the thin design and the appearance at the rotating shaft.

Currently, an electronic device may also be tested through a universal serial bus (universal serial bus, USB) interface, for example, but not limited to, including a USB Type-C interface, where the Type-C interface may be referred to in fig. 7, and fig. 8 illustrates a schematic diagram of the Type-C interface, and as illustrated in fig. 8, the USB interface may include 24 pins, where the A6 pin and the B7 pin are Data Positive (DP) pins, the A7 pin and the B6 pin are Data negative (DM) pins, the DP pin may be used to provide a DP signal, the DM pin may be used to provide a DM signal, and the DP signal and the DM signal may be used to identify a charging proprietary protocol. The A5 pin is a Configuration pin (Configuration CHANNEL PIN, CC 1), the B8 pin is a CC2 pin, the CC1 pin and the CC2 pin may be used to provide a CC signal, the CC signal may be used to identify a Type-C protocol supported by the add signal line, for example, the Type-C protocol is USB2.0 or USB3.0, and may also be used to identify a charging power supported by the add signal line. The A8 pin is an auxiliary pin (Sideband use pin, SBU 1), the B5 pin is an SBU2 pin, and the SBU1 pin and the SBU2 pin are standby pins of the Type-C interface, which can be used for supporting additional functions, such as audio transmission, video transmission and the like.

Fig. 9 illustrates a circuit connection diagram of a USB interface and a main chip of an electronic device, where the electronic device may include an SOC, a charging (Charger) module, and a USB interface, as shown in fig. 9, where the USB interface may be connected to the USB module of the charging module and the USB module of the SOC, respectively, and specifically, a USB module of the charging module and a USB module of the SOC may be connected to a DM pin and a DP pin of the USB interface, respectively, where a line 1 and a line 3 connected to the DM pin may be DM lines (may be understood as a line 1 and a line 3 share the DM pin), a line 2 and a line 4 connected to the DP pin may be DP lines (may be understood as a line 2 and a line 4 share the DP pin), the DM lines may be used for transmitting DM signals, and the DP lines may be used for transmitting DP signals. The USB interface can be connected with a CC module of the charging module through a wire 5, in particular to a CC module of the charging module through CC1/CC2 pins of the USB interface, wherein the wire 5 connected with the CC1/CC2 pins can be a CC wire, and the wire 5 can be used for transmitting CC signals. IO2 module and the USB module in the module that charges can be connected through switch K1, and the IO2 module of the module that charges and the IO2 module of SOC can be connected through line 6, and line 6 can be the UART line for the error log of transmission SOC when carrying out the test through the USB interface. The I2C module of the charging module and the I2C module of the SOC may be connected by a line 7, and the line 7 may be an I2C line for the SOC to control the charging module. The JTAG module of the SOC can be connected with the on-board test point through the IO module, and the on-board test point can be used for JTAG debugging of an independent chip. The JTAG module may be connected to the SD/SIM_IO module to enable JTAG debug of the electronic device through an entity cartridge (not shown in FIG. 9, see SIM card module in FIG. 5) to which the SD/SIM_IO module is connected.

In one embodiment, the charging module may be connected to a battery of the electronic device, and a circuit structure (not shown in fig. 9) related to charging and discharging of the battery is integrated in the charging module, and the charging module may be used to identify a type and a protocol of the charger, switch to a circuit matched with the charger, and charge the battery, and may also be used to adjust an output voltage of the battery during discharging of the battery, so as to supply power to other modules in the circuit.

When the electronic device uses the USB interface to perform the test, the error log of the SOC may be transmitted through the UART line (line 6) in fig. 9, but the test performed through the USB interface is generally a test that does not require a conversion protocol, and JTAG debug needs to involve a conversion of a signal protocol, so the JTAG test cannot be performed directly through the USB interface. In order to cope with this situation, a conversion chip may be added between the USB interface and the SOC, the USB signal protocol is converted into the serial signal protocol by the conversion chip, and then the serial signal protocol is connected to the interface of the JTAG module by the conversion chip, and a specific example may be referred to a circuit connection diagram for JTAG debug of the electronic device shown in fig. 10.

As shown in fig. 10, the USB interface may be connected to the USB module of the conversion chip through the DM pin and the DP pin, and the USB interface may be connected to the CC module of the conversion chip through the CC1/CC2 pin. The IO2 module and the USB module in the conversion chip can be connected through the switch K2, the IO2 module of the conversion chip is connected with the IO2 module of the SOC, and the IO2 module of the SOC is connected with the JTAG module. Through the connection mode, the USB signal protocol input to the conversion chip by the USB interface can be converted into the serial port signal protocol through the conversion chip, and then the serial port signal protocol is input to the JTAG module through the IO2 module of the SOC, so that JTAG debugging is realized. However, this method adds a conversion chip with a complex device structure and a large area, which increases the cost of the electronic device.

In the present application, the electronic device may be a smart home device such as a mobile phone, a tablet computer, a handheld computer, a desktop computer, a laptop computer, a super mobile personal computer (ultra-mobile personal computer, UMPC), a netbook, a cellular phone, a Personal Digital Assistant (PDA), a smart television, a wearable device such as a smart bracelet, a smart watch, a smart glasses, an augmented reality (augmented reality, AR), a Virtual Reality (VR), a Mixed Reality (MR), an extended reality (XR) device, a vehicle-mounted device, or a smart city device, etc., and the present application is not limited to a specific type of electronic device, for example, the electronic device is a mobile phone, and a perspective view of the mobile phone may be referred to in fig. 11 (a), and a front view of the mobile phone may be referred to in fig. 11 (B).

Next, the structure of an exemplary electronic device provided by an embodiment of the present application will be described.

Fig. 12 exemplarily shows a hardware configuration diagram of an electronic device.

As shown in fig. 12, the electronic device may include an SOC, a charging module, and a USB interface, where the SOC, the charging module, and the USB interface are electrically connected to each other, and the electrical connection manner includes, for example, but not limited to, a PCB circuit and an FPC circuit. Wherein:

The SOC may be used to send instructions to various modules within the electronic device and process data transmitted by the various modules to the SOC, which may include multiple processing units, such as a central processing unit (Central Processing Unit, CPU), a graphics processor (graphics processing unit, GPU), an image signal processor (IMAGE SIGNAL processor, ISP), a controller, a video codec, a motion processor, and so forth. Wherein the different processing units may be separate devices or may be integrated in one or more processors. In one embodiment, the SOC may include a JTAG module for enabling JTAG debugging of the electronic device.

The charging module can be electrically connected with a battery of the electronic equipment, a circuit structure related to charging and discharging of the battery is integrated in the charging module, the charging module can be used for identifying the type and protocol of a charger, switching to a circuit matched with the charger and charging the battery, and the charging module can also be used for adjusting the output voltage of the battery in the discharging process of the battery so as to supply power for other modules in the circuit.

In one embodiment, the USB interface may be externally connected to a charger, and charge a battery of the electronic device through the connected charging module. The USB interface can realize a charging function through CC signals, DM signals and DP signals. For example, the USB interface may send a CC signal to the charging module through a CC1/CC2 pin, and the charging module may identify, according to the CC signal, a Type-C protocol supported by the add signal line and a supported charging power. For another example, the USB interface may send DM signals and DP signals to the SOC via DM pins and DP pins, respectively, and the SOC may identify the charging proprietary protocol according to the DM signals and DP signals.

In one embodiment, the USB interface may also be externally connected to a data line and transmit data through the connected SOC. For example, the USB interface may implement a data transmission function through a CC signal, a DM signal, and a DP signal.

In one embodiment, a JTAG module of the SOC may lead out a plurality of debug signal lines to be connected to a charging module, and the charging module may be connected to a USB interface to use pins on the USB interface as external interfaces of the JTAG debug circuit, specifically, CC1/CC2 pins of the USB interface are connected to the charging module, and other pins of the USB interface may be connected to the plurality of debug signal lines led out by the JTAG module through the charging module. The USB interface can be connected with a JTAG debugging controller, and the JTAG debugging controller is connected with the JTAG module of the SOC through the USB interface, the charging module and the JTAG module of the SOC to perform JTAG testing.

It should be understood that the structure illustrated in the embodiments of the present application does not constitute a specific limitation on the electronic device. In other embodiments of the application, the electronic device may include more or less components than illustrated, or certain components may be combined, or certain components may be split, or different arrangements of components. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

Fig. 13 exemplarily shows a circuit configuration diagram of an electronic device.

The circuit structure of the electronic device shown in fig. 13 is similar to that of the electronic device shown in fig. 9, except that the JTAG module in fig. 13 is not connected to the SD/sim_io module, but is connected to the IO2 module in the SOC via the line 8 and the line 9, specifically, the SWCLK pin and SWDIO pin of the JTAG module are connected to the IO2 module of the charging module via the two debug signal lines of the IO2 module outgoing line 8 and the line 9 of the SOC, the line 8 is, for example, the SWCLK signal line, which can be used for transmitting the SWCLK signal, the line 9 is, for example, the SWDIO signal line, which can be used for transmitting the SWDIO signal.

In one embodiment, the USB interface may send a CC signal to the CC module of the charging module through line 5, after the charging module receives the CC signal, the electronic device may determine whether to enter the JTAG debug mode currently according to the CC signal, for example, when the signal voltage of the CC line is greater than or equal to a first threshold and less than or equal to a second threshold, the first threshold is less than the second threshold, and the electronic device may determine that the JTAG debug mode is currently entered. For another example, the electronic device may confirm that a JTAG-capable debug mode is currently entered when the waveform characterized by the CC signal corresponds to a preset waveform. For another example, the private protocol mode is entered according to the CC signal, and then the specific signal is transmitted through the DM pin (corresponding line 3) and the DP pin (corresponding line 4) based on the private protocol to enter the JTAG debug mode.

In one embodiment, when it is determined that the JTAG-capable debug mode is entered, the electronic device may control switch K1 in the charging module to be closed, at which time SWCLK signal line (line 8) and SWCLK signal line (line 9) are connected to DM pin and DP pin of the USB interface, which may be understood as SWCLK pin and SWDIO pin of the JTAG module being connected to DM pin and DP pin, respectively, through the charging module, for example, SWCLK pin being connected to DM pin through the charging module, SWDIO pin being connected to DP pin through the charging module, line 8 being connected to line 3 through switch K1, line 9 being connected to line 4 through switch K1, and line 1 and line 2 being shorted, at which time DM pin and DP pin of the USB interface are used for performing JATG serial debugging of the electronic device, JTAG debugging of the electronic device may be performed through line 8 and line 3, line 9 and line 4. In another embodiment, the SWCLK pin is connected to the DP pin through the charging module, the SWDIO pin is connected to the DM pin through the charging module, the line 8 is connected to the line 4 through the switch K1, and the line 9 is connected to the line 3 through the switch K1.

In one embodiment, when it is determined that the JTAG-capable debug mode is not entered, the electronic device may control switch K1 in the charging module to open, at which time the DM pin and the DP pin of the USB interface may be used to send DM signals and DP signals to the SOC to cause the SOC to identify the charging proprietary protocol.

In the circuit structure shown in fig. 13, only the USB interface of the electronic device can be reused as the external interface for JTAG debugging without using/passing through the contacts of the physical card holder, and when the electronic device is a foldable device, the USB interface and the SOC are both located at one side of the rotating shaft, so that the thickness of the rotating shaft of the foldable device is reduced, which is more beneficial to the thin design of the rotating shaft, and the aesthetic feeling is improved. In addition, aiming at the problem of signal protocol conversion between the USB interface and the SOC, an additional conversion chip is not needed, two debugging signal lines are led out of the JTAG module and are connected to the original charging module of the electronic equipment, JTAG serial debugging of the electronic equipment can be realized based on the USB interface, and it can be understood that the charging module does not need to convert the signal protocol, signals of the same type (such as a first protocol) are transmitted among the JTAG module, the charging module and the USB interface, the first protocol is such as SWD protocol (namely two-line JTAG protocol), and the multiplexing charging module can not add devices newly, so that the cost of the electronic equipment is saved.

Fig. 14 exemplarily shows a circuit configuration diagram of still another electronic apparatus.

The circuit configuration of the electronic device shown in fig. 14 and 13 is similar, except that fig. 14 does not include a charging module, but includes a USB switch circuit module and an interface chip, the USB switch circuit module may include an IO2 module and a USB module, the IO2 module of the USB switch circuit module and the USB module of the USB switch circuit module may be connected through a switch K3, the CC1/CC2 pin of the USB interface in fig. 14 is connected to the interface chip, i.e., the CC line (line 5) is connected to the interface chip, the interface chip and the USB switch circuit module are connected, the USB interface may be connected to the USB module of the USB switch circuit module through a line 3 and a line 4, particularly, the USB module of the USB switch circuit module is connected through a DM pin and a DP pin of the USB interface, the JTAG module is connected to the IO2 module of the USB switch circuit module through a line 8 and a line 9, particularly two debug signal lines are led out of the IO2 module from SWCLK pin and SWDIO pin of the JTAG module through the SOC and the IO2 module of the line 9.

In one embodiment, the USB interface may send a CC signal to the interface chip through the line 5, after the interface chip receives the CC signal, the electronic device may determine whether to currently enter a JTAG debug mode according to the CC signal, and send a switch control signal to the USB switch circuit module according to the determination result, where the USB switch circuit module may control the switch K3 to be turned on or turned off according to the switch control signal.

In some examples, when it is determined that the JTAG-capable debug mode is entered, the electronic device may send a signal to the USB switch circuit module indicating that the switch is closed, after the USB switch circuit module receives the signal, control switch K3 to close, at which time SWCLK signal line (line 8) and SWCLK signal line (line 9) are connected with DM pin and DP pin of the USB interface, it may be understood that SWCLK pin and SWDIO pin of the JTAG module are connected with DM pin and DP pin through the USB switch circuit module, respectively, for example, SWCLK pin is connected with DM pin through the USB switch circuit module, SWDIO pin is connected with DP pin through the USB switch circuit module, line 8 is connected with line 3 through switch K3, line 9 is connected with line 4 through switch K3, and line 1 and line 2 are short-circuited, at which time DM pin and DP pin of the USB interface are used for JATG serial debug of the electronic device, JTAG serial debug of the electronic device may be performed through line 8 and line 3, line 9 and line 4. In another embodiment, the SWCLK pin is connected to the DP pin through the USB switch circuit module, the SWDIO pin is connected to the DM pin through the USB switch circuit module, the line 8 is connected to the line 4 through the switch K3, and the line 9 is connected to the line 3 through the switch K3.

In other examples, when it is determined that the JTAG-capable debug mode is not entered, the electronic device may send a signal to the USB switch circuit module indicating that the switch is turned off, and after receiving the signal, the USB switch circuit module controls the switch K3 to be turned off, at which time the DM pin and the DP pin of the USB interface may be used to send DM signals and DP signals to the SOC to enable the SOC to identify the charging proprietary protocol.

It will be appreciated that the interface chip shown in fig. 14 may also be integrated in a USB switch circuit module, and the interface chip and the USB switch circuit module may be collectively referred to as a switch circuit module.

In the circuit structure shown in fig. 14, the original charging module of the electronic device may not be reused, for example, the functional effect of the original charging module of the electronic device is ensured, for example, the electronic device does not include the charging module, and a switch circuit module (including a USB switch circuit module and an interface chip) may be newly added to implement JTAG serial debugging, where the USB module and the IO2 module in the switch circuit module are not used for converting a signal protocol, but only serve as intermediate modules to forward the signal, and the conversion chip converts the signal through other modules (the other modules are not shown in the conversion chip of fig. 10), so that the other modules for performing signal protocol conversion in the conversion chip are relatively complex and have a larger area, and the device structure of the switch circuit module is simpler and has a smaller area, thereby saving the cost of the electronic device.

Fig. 15 exemplarily shows a circuit configuration diagram of still another electronic apparatus.

The circuit structures of the electronic devices shown in fig. 15 and 14 are similar, except that the USB switch circuit module in fig. 15 further includes an SBU module, where the USB interface may be connected to the SBU module through an SBU1 pin (e.g., corresponding line 14) and an SBU2 pin (e.g., corresponding line 15), and the SBU module may be connected to the IO2 module of the USB switch circuit module through a switch K4. The JTAG module in fig. 15 is connected with the IO2 module of the USB switch circuit module, specifically, four pins TCK, TMS, TDI, TDO of the JTAG module are connected to the IO2 module of the USB switch circuit module through four debug signal lines of the IO2 module outgoing line 10, the line 11, the line 12 and the line 13 of the SOC, the line 10 is, for example, a TCK signal line, may be used for transmitting a TCK signal, the line 11 is, for example, a TMS signal line, may be used for transmitting a TMS signal, the line 12 is, for example, a TDI signal line, may be used for transmitting a TDI signal, the line 13 is, for example, a TDO signal line, and may be used for transmitting a TDO signal.

In one embodiment, the USB interface may send a CC signal to the interface chip through the line 5, after the interface chip receives the CC signal, the electronic device may determine whether to currently enter the JTAG debug mode according to the CC signal, and send a switch control signal to the USB switch circuit module according to the determination result, where the USB switch circuit module may control the states (e.g. on or off) of the switch K3 and the switch K4 according to the switch control signal.

In some examples, when it is determined that a JTAG-capable debug mode is entered, the electronic device may send a signal to the USB switch circuit module indicating that the switch is closed, after the USB switch circuit module receives the signal, control switch K3 and switch K4 to be closed, at which time the TCK signal line (line 10) and the TMS signal line (line 11) are connected to the DM pin and the DP pin of the USB interface, the TDI signal line (line 12) and the TDO signal line (line 13) are connected to the SBU1 pin and the SBU2 pin of the USB interface, which may be understood as that the TCK pin and the TMS pin of the JTAG module are respectively connected to the DM pin and the DP pin through the USB switch circuit module, the TDI pin and the TDO pin of the JTAG module are respectively connected to the SBU1 pin and the SBU2 pin through the USB switch circuit module, for example, TCK pin is connected to DM pin through USB switch circuit module, TMS pin is connected to DP pin through USB switch circuit module, TDI pin is connected to SBU1 pin through USB switch circuit module, TDO pin is connected to SUB2 pin through USB switch circuit module, line 10 is connected to line 3 through switch K3, line 11 is connected to line 4 through switch K3, line 12 is connected to line 14 through switch K4, line 13 is connected to line 15 through switch K4, and line 1 and line 2 are short-circuited, DM pin, DP pin, SBU1 pin and SBU2 pin of USB interface are used for JATG parallel debugging of electronic device, JTAG parallel debugging of electronic device can be performed through line 10 and line 3, line 11 and line 4, line 12 and line 14, line 13 and line 15. The application is not limited to this, and the specific connection mode between the four pins (TCK pin, TMS pin, TDI pin, TDO pin) of the JTAG module and the four pins (DM pin, DP pin, SBU1 pin, SBU2 pin) of the USB interface is not limited.

In other examples, when it is determined that the JTAG-capable debug mode is not entered, the electronic device may send a signal to the USB switch circuit module indicating that the switch is turned off, and after receiving the signal, the USB switch circuit module controls the switch K3 and the switch K4 to be turned off, at which time the DM pin and the DP pin of the USB interface may be used to send the DM signal and the DP signal to the SOC, so that the SOC identifies the charging proprietary protocol.

In the circuit structure shown in fig. 15, compared with two debug signal lines of the JTAG serial debug, four debug signal lines are led out from the JTAG module and connected to a newly added switch circuit module (including a USB switch circuit module and an interface chip), so that the JTAG parallel debug of the electronic device can be realized based on the USB interface, and at this time, the protocols transmitted between the JTAG module, the charging module and the USB interface are, for example, the JTAG protocol (i.e., the four-wire JTAG protocol), that is, the JTAG debug in different modes can be realized based on different pin connection modes, so that the achievable scene of the JTAG debug is wider.

The method provided by the embodiments of the present application may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, produces a flow or function in accordance with embodiments of the present application, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, a network device, a user device, or other programmable apparatus. The computer instructions may be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another computer readable storage medium, for example, the computer instructions may be transmitted from one website, computer, server, or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (digital subscriber line, DSL), or wireless (e.g., infrared, wireless, microwave, etc.) means to another website, computer, server, or data center, the computer readable storage medium may be any available medium that can be accessed by a computer or a data storage device including one or more available media integrated servers, data centers, etc., the available medium may be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., digital video disc (digital video disc, DWD), or semiconductor medium (e.g., solid state disk (solid STATE DISK, SSD)), the foregoing embodiments are merely illustrative of the present application, and the foregoing embodiments are not limited by the foregoing, and the foregoing embodiments may be implemented without departing from the spirit or modifying the scope of the application by the foregoing general technical description.

Claims

1. A test circuit, characterized in that the circuit includes a main chip, a switch circuit module, and a universal serial bus (USB) interface, the main chip including a Joint Test Action Group (JTAG) module and a first input/output (IO) module, the switch circuit module including a second input/output (IO) module, a first USB module, and a first switch, wherein N pins of the JTAG module are connected to a first end of the first IO module, a second end of the first IO module is connected to a first end of the second IO module, a second end of the second IO module is connected to a first end of the first switch, a second end of the first switch is connected to a first end of the first USB module, and a second end of the first USB module is connected to N pins of the USB interface, the USB interface is connected to a test device, and N is a positive integer. The test circuit is configured to perform:

When entering the test mode is detected, controlling the first switch to be closed; when the first switch is closed, the JTAG module is connected to the test device through the switch circuit module and the USB interface;

When the first switch is closed, the JTAG module performs a JTAG test through the testing device.

2. The circuit according to claim 1, wherein the test circuit is powered by a first battery, the switch circuit module is a charging module, and the charging module is used to charge the first battery.

3. The circuit according to claim 1 or 2, wherein the N pins of the JTAG module include a serial clock SWCLK pin and a serial data input/output SWDIO pin, and the N pins of the USB interface include a data positive signal line DP pin and a data negative signal line DM pin,

When the first switch is closed, the SWCLK pin and the SWDIO pin are connected to the DP pin and the DM pin respectively through the first switch, so that the JTAG module is connected to the test device through the switch circuit module and the USB interface;

The test circuit is used to perform:

When the first switch is closed, the JTAG module performs a JTAG serial test through the SWCLK pin, the SWDIO pin, and the test device.

4. The circuit according to any one of claims 1 to 3, wherein the switch circuit module further comprises a configuration pin CC module, the CC module being connected to a CC pin of the USB interface, and the test circuit is configured to perform:

When the CC module receives the CC signal sent by the USB interface, it detects whether to enter the test mode according to the CC signal.

5. The circuit according to any one of claims 1 to 4, wherein the main chip includes a second USB module, the N pins of the USB interface include a DP pin and a DM pin, the DP pin and the DM pin are both connected to the second USB module, and the test circuit is further configured to perform:

When it is detected that the test mode has not been entered, controlling the first switch to be disconnected;

When the first switch is turned off, the USB interface sends a DP signal and a DM signal to the second USB module through the DP pin and the DM pin respectively, where the DP signal and the DM signal are used to identify a private charging protocol.

6 . The circuit according to claim 1 , wherein when the JTAG module is subjected to a JTAG test by the test device, the JTAG module and the test device transmit signals of a first protocol through the switch circuit module and the USB interface.

7. The circuit according to claim 6, wherein the switch circuit module comprises a USB switch circuit module and an interface chip, the USB switch circuit module comprises the second IO module, the first USB module, and the first switch, an input end of the interface chip is connected to a CC pin of the USB interface, an output end of the interface chip is connected to the USB switch circuit module, and the test circuit is configured to perform:

When the interface chip receives the CC signal sent by the USB interface, detecting whether to enter the test mode according to the CC signal;

When entering the test mode, the interface chip sends a first control signal to the USB switch circuit module, where the first control signal is used to control the first switch to be closed;

When it is detected that the test mode has not been entered, the interface chip sends a second control signal to the USB switch circuit module, where the second control signal is used to control the first switch to be disconnected.

8. The circuit according to claim 6 or 7, wherein the N pins of the JTAG module include an SWCLK pin and an SWDIO pin, and the N pins of the USB interface include a DP pin and a DM pin,

The test circuit is used to perform:

9. The circuit according to claim 6 or 7, wherein the switch circuit module further comprises an auxiliary pin SBU module and a second switch, the N pins of the JTAG module include a test clock signal TCK pin, a test mode state TMS pin, a test data input TDI pin, and a test data output TDO pin, and the N pins of the USB interface include a DP pin, a DM pin, an auxiliary SBU1 pin, and an SBU2 pin, wherein a second end of the first USB module is connected to the DP pin and the DM pin, a first end of the SBU module is connected to the SBU1 pin and the SBU2 pin, a second end of the SBU module is connected to a first end of the second switch, and a second end of the second switch is connected to a second end of the second IO module, and the test circuit is configured to perform:

When entering the test mode is detected, controlling the first switch and the second switch to be closed; when the first switch and the second switch are closed, the TCK pin, the TMS pin, the TDI pin, and the TDO pin are connected to the DP pin, the DM pin, the SBU1 pin, and the SBU2 pin, respectively, through the first switch and the second switch, so that the JTAG module is connected to the test device through the switch circuit module and the USB interface;

When the first switch and the second switch are closed, the JTAG module performs a JTAG parallel test through the TCK pin, the TMS pin, the TDI pin, the TDO pin, and the test device.