CN120803551A

CN120803551A - USB low-power consumption awakening system, method, chip module and terminal

Info

Publication number: CN120803551A
Application number: CN202511312723.XA
Authority: CN
Inventors: 许林华; 刘文强; 崔亮亮; 吴雄鹏
Original assignee: Xiamen Ziguang Zhanrui Technology Co ltd
Current assignee: Xiamen Ziguang Zhanrui Technology Co ltd
Priority date: 2025-09-15
Filing date: 2025-09-15
Publication date: 2025-10-17

Abstract

The invention discloses a USB low-power consumption wake-up system, a method, a chip module and a terminal, wherein the system comprises: the system comprises a USB physical layer interface for receiving a differential signal DP/DM of a USB bus, a wake-up signal generating circuit for generating a hardware wake-up signal in a USB low-power state, a system interrupt controller for receiving the hardware wake-up signal and outputting a system wake-up interrupt, a USB controller for entering or exiting the low-power state under the control of on-chip processing logic, and on-chip processing logic for restoring a clock and a power supply to the USB controller in response to the system wake-up interrupt. The USB controller shuts down the master clock in a USB low power state, leaving only a small amount of holding power for saving register context. According to the invention, the USB controller in a low power consumption state is bypassed, and the system is directly connected to the interrupt pin of the chip, so that the system is firstly interrupted and waken up and then powered on/off, and the Suspend power consumption is reduced to the minimum.

Description

USB low-power consumption awakening system, method, chip module and terminal

Technical Field

The present invention relates to the field of integrated circuits, and in particular, to a system, a method, a chip module, and a terminal for waking up USB with low power consumption, in which a main clock and a main power supply of a USB controller are turned off in a USB low power consumption state, and the USB controller is directly woken up through a hardware line state.

Background

In USB communication, to save power consumption, the device supports Suspend state. When the bus is in Idle (J state) for more than 3ms, the specification (USB 2.0) requires that the USB host (host) or device should complete entering into Suspend state within 7 ms. In this state, the USB host or device may reduce current consumption, e.g., in the suspend state, the current from VBUS for the low power device may be less than or equal to 500 μA. Existing wake mechanisms include two wake approaches, host initiated wake (host driven Resume) and device initiated Remote wake (Remote Wakeup).

In the wake-up initiated by the host, when the host needs to communicate with the device again, the host drives a Resume signal (Resume signaling) on the bus to pull the differential pair from J state to K state of opposite polarity and keep the differential pair equal to or larger than 20ms on the low speed/full speed link. The high-speed link also completes 20ms Resume in full-speed electrical layer K state before performing a high-speed handshake to return to high-speed mode. After detecting the recovery signal on the bus, the device exits from Suspend and returns to the normal working state without re-enumeration.

In device initiated remote wakeup, if the device has been declared in the configuration descriptor at enumeration and has been enabled by the host, the device may initiate wakeup itself when the bus is idle, with the device driving the K state for at least 1ms (no more than 15 ms) and then continuing to drive by the downstream port until the host takes over. The downstream hub or root port, upon receipt of this signal, continues to drive the Resume signal until the host takes over. Typical scenarios for this mode are a mouse movement on standby notebook, keyboard keys, or USB hub detecting a device insertion at the downstream port.

Both host initiated wake-up and device initiated remote wake-up mechanisms require the USB controller to remain clocked and powered during Suspend in order to detect the Resume signal at any time, resulting in no further reduction in power consumption.

The invention patent with publication number CN113094105A in the prior art discloses a method for ensuring the low power consumption state of USB equipment and waking up the USB equipment, which is characterized in that a double-pole double-throw analog switch is added on a USB path between a processor and a host, the double-pole double-throw analog switch is used for ensuring the signal integrity of a USB2.0 bus and maintaining a suspend state on the USB bus, and the method is realized through the double-pole double-throw analog switch, when the USB equipment receives the suspend signal sent by the host and enters a lower power consumption suspend state, namely, the processor enters the suspend state, the processor shuts down the power supply, the clock and the bus of a kernel, and the processor detects the K or SE0 signal sent by the host to the USB equipment through the USB bus and is used as an interrupt signal of the processor to enable the processor to exit the suspend state, and the USB bus is restored, so that the USB equipment exits the suspend state.

The invention patent CN113094105A is applied to a host initiated wake-up mechanism, and mainly wakes up USB devices (slave devices) through devices (double pole double throw switches) outside the SoC chip. The application scene is that the USB equipment needs to be used as a slave, is similar to the USB equipment connected with a PC to be used as transmission data, or is powered off when being charged, so that a low-power consumption state of the USB is achieved. In the patent, when a host transmits a K or SE0 signal, the edge of a DP signal is changed from high to low, the DP signal is used as an interrupt signal to enable a processor to exit from a sleep state, a control signal of a change-over switch is transmitted within the longest response time of a USB2.0 bus protocol, the connection between D+ and HSD2+ is disconnected, the connection between D+ and HSD1+ is changed into the connection between D+ and HSD1-, the connection between D-and HSD 1-is restored, the USB bus between the host and the processor is restored, and the USB device is restored to work. The USB2.0 bus protocol specifies that after the host sends a wake-up signal, the host should respond for 20ms, or else the host will clear the signal, after the switch is completed, the entire system of the USB device is related to wake-up and powered up, then the USB controller is configured with a clock and a power supply, and then the state of the USB controller is still stable, and the K state/SE 0 signal sent by the host may be processed. Said invention uses the off-chip double-pole double-throw switch to convert the edge change of DP/DM into GPIO interrupt for waking up MCU. However, since the MCU is powered on again and the USB controller is time-consuming to initialize, the current scheme is difficult to meet the 20ms Resume time required by the USB2.0 in the actual test, and therefore cannot be popularized and applied.

Disclosure of Invention

The following presents a simplified summary of embodiments of the invention in order to provide a basic understanding of some aspects of the invention. It should be understood that the following summary is not an exhaustive overview of the invention. It is not intended to identify key or critical elements of the invention or to delineate the scope of the invention. Its purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later.

In view of the defects of the prior art, the invention aims at improving a remote wake-up mechanism initiated by equipment, and provides a hardware wake-up path for directly connecting a USB line state change signal to a system interrupt controller, wherein the system can reach a deep sleep state under a Suspend state by the USB controller, so that the system power consumption is obviously reduced.

According to a first aspect of the present application, there is provided a USB low-power wake-up system comprising:

a USB physical layer interface (USB PHY) configured to receive differential signals DP/DM of the USB bus;

the wake-up signal generation circuit is coupled with the USB physical layer interface and is configured to generate a hardware wake-up signal when the bus is detected to be changed from a J state to a K state in a USB low-power consumption state;

A system interrupt controller (INTC) directly connected with the wake-up signal generating circuit to receive the hardware wake-up signal and output a system wake-up interrupt;

A USB controller (USB controller) coupled with the USB physical layer interface, a main power supply controlled by the on-chip processing logic to enter or exit a USB low power consumption state, a main clock and a main power supply of the USB controller being turned off in the USB low power consumption state, a register context being stored by a power domain which is normally open by the chip, and

And the on-chip processing logic responds to the system wakeup interrupt and restores a main clock and a main power supply for the USB controller so as to enable the USB controller to complete a bus wakeup sequence and enter a normal working state.

The On-chip processing logic is powered by the holding power domain and is used for processing interrupt and controlling the power-On, power-off, clock gating and wake-up sequences of all the functional power domains in the SoC.

The wake-up signal generating circuit is divided into the following two schemes which can be selected independently according to the implementation mode:

The first mode is that the USB physical layer interface integrates a wake-up detection function, the hardware wake-up signal is directly output in a power domain, the USB physical layer interface is in a low-power monitoring mode in a USB low-power state, only bias current and terminal resistance required by DP/DM detection are maintained, and other modules are powered off. At this time, the main power supply of the USB controller is turned off (clock is kept), only the necessary power supply for the subsequent USB controller and the system to function normally is maintained, and the register context is kept by the always-on keeping power supply domain of the chip. The full link of the USB controller works normally, and at the moment, the system can ignore that the USB controller enters a deep state, so that a low-power consumption scene of the whole system is maintained. The hardware wake-up signal is directly output by the USB physical layer interface, when the wake-up signal exists, the USB controller can directly receive the wake-up signal and send the wake-up signal to the on-chip processing logic for processing, and the on-chip processing logic responds to the wake-up interrupt to restore the main power supply of the USB controller.

In the second mode, the USB physical layer interface only outputs a line state signal LINESTATE, which is sent to an External Interrupt Controller (EIC) (External Interrupt Controller ) or General Purpose Input/Output (GPIO), the EIC or GPIO completes edge detection in a power-holding domain and generates the hardware wake-up signal, the USB physical layer interface is completely powered off except for a termination resistor and LINESTATE buffer in a USB low power consumption state, and the USB controller master clock is turned off, so that only necessary power supplies for maintaining normal functions of the subsequent USB controller and the system are reserved. The whole system is awakened by the EIC and the GPIO, and then the system powers on and clocks the USB controller through on-chip processing logic in the awakening process, so that the USB controller can normally respond and complete a bus awakening sequence.

The first mode is suitable for a USB physical layer interface with a power-down awakening capability and direct interrupt output. The second mode is a preferred mode, and the hardware wake-up signal is an interrupt request signal generated by the EIC or GPIO after the USB physical layer interface sends the current state of the USB data line to the EIC or GPIO. The scheme has universality, the USB physical layer interface does not need to have power-down awakening capability, only needs to output a line state signal (LINESTATE), the awakening capability is provided by EIC/GPIO, the requirement on the USB physical layer interface is lower, the USB physical layer interface can be completely powered off except for a terminal resistor and a line state signal (LINESTATE), only the EIC/GPIO is kept to be monitored, and the power consumption is lower. Furthermore, the GPIO/EIC should be provided with a Schmitt trigger or filter to prevent false triggers.

Further, the wake-up signal generating circuit includes a line state detecting unit and an edge detecting unit;

the line state detection unit is used for converting the DP/DM differential signal output by the USB physical layer interface into a digital line state signal;

and the edge detection unit is realized by EIC/GPIO in the SoC and is used for generating a hardware wake-up signal when detecting that the line state signal jumps from the J state to the K state.

The line status detection unit is powered by the keep-alive (Always-On) power domain, and the remaining analog and digital modules are powered down.

Further, the system interrupt controller is a programmable GPIO module or a dedicated external interrupt controller EIC, and the hardware wake-up signal is directly input to the GPIO module or EIC through a chip pin, without going through internal logic of the USB controller.

Further, the USB controller is a USB host controller or a USB device controller integrated in the SoC, and in the Suspend state, its register context is kept in the keep power domain, while the master clock and the master power are completely turned off.

According to a second aspect of the present application, there is provided a USB low-power wake-up method applied to the low-power wake-up system, including the steps of:

a) The on-chip processing logic turns off the main clock and the main power supply of the USB controller, and the register context of the USB controller is stored by a normally-open power domain of the chip;

b) Continuously monitoring the state of the USB line by a wake-up signal generating circuit;

c) When the line state is detected to be changed from the J state to the K state, directly generating a hardware wake-up signal;

d) The system interrupt controller receives the hardware wake-up signal and sends a wake-up interrupt to on-chip processing logic;

e) On-chip processing logic responds to the wake-up interrupt to recover the main clock and the main power supply of the USB controller;

f) The USB controller resumes the register context from the keep-alive power domain, performs a wake-up sequence defined by the USB specification, and resumes normal data communication.

In the step c), the generation of the hardware wake-up signal is divided into the following two schemes which can be selected independently:

a) The first scheme is that the USB physical layer interface integrates a wake-up detection function, and directly outputs the hardware wake-up signal in a power domain, wherein the USB physical layer interface is in a low power consumption monitoring mode, only maintains bias current and terminal resistance required by detecting DP/DM, and other modules are powered off, namely the USB physical layer interface keeps the lowest power consumption and directly outputs line state change;

b) The USB physical layer interface only outputs a line state signal LINESTATE, the line state signal is sent to an external interrupt controller EIC or general purpose input/output GPIO, the EIC or GPIO completes edge detection in a power-holding domain and generates the hardware wake-up signal, the USB physical layer interface is completely powered off except for a terminal resistor and LINESTATE buffer in a USB low-power state, the USB controller main clock and the main power supply are turned off, and the register context is saved by the power-holding domain.

According to a third aspect of the present application, a chip is provided, the above system being integrated on the same silicon chip.

According to a fourth aspect of the present application, a chip module is provided, comprising the chip and a USB connector.

According to a fifth aspect of the present application, there is provided a terminal comprising the chip module, the terminal being configured to enter a Suspend state when a USB bus is idle and resume USB communication when a bus wakeup event is received.

The invention bypasses the USB controller in the power-off state through the hardware direct connection mode (the passage in the SoC chip), is directly connected to the interrupt pin (EIC/GPIO) of the chip, so that the system is firstly interrupted and waken up and then powered on/off, the USB controller can thoroughly power off and sleep, thereby minimizing the Suspend power consumption, realizing microampere-level suspension current, and being applicable to battery-powered USB equipment, factory test jigs and low-power terminals.

Drawings

The invention may be better understood by referring to the following description in conjunction with the accompanying drawings in which like or similar reference numerals are used to indicate like or similar elements throughout the several views. The accompanying drawings, which are included to provide a further illustration of the preferred embodiments of the invention and together with a further understanding of the principles and advantages of the invention, are incorporated in and constitute a part of this specification. In the drawings:

FIG. 1 is a diagram illustrating a wake-up path according to embodiment 1 of the present invention;

FIG. 2 is a diagram illustrating a wake-up path according to embodiment 2 of the present invention;

Fig. 3 is a flow chart of a low power consumption wake-up method according to embodiment 2 of the present invention.

Detailed Description

Embodiments of the present invention will be described below with reference to the accompanying drawings. Elements and features described in one drawing or embodiment of the invention may be combined with elements and features shown in one or more other drawings or embodiments. It should be noted that the illustration and description of components and processes known to those skilled in the art, which are not relevant to the present invention, have been omitted in the drawings and description for the sake of clarity.

In the description of the present invention, it should be understood that the terms "mounted," "connected," and "coupled" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected, mechanically connected, electrically connected, directly connected, or indirectly connected through an intermediate medium, or may be communication between two elements. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.

The following terms used in the present application are collectively described as follows:

IP Intellectual Property, an IP asset commonly purchased in the chip industry, also known as an IP core (Intellectual Property Core), refers to the mature design of circuit modules in a chip that have independent functionality, are reusable, and have proprietary intellectual property functionality. Generally, they are classified into soft core, hard core and solid core.

USB lowpower state-means that in USB communication, the device enters a mode of reduced power consumption to save battery life or reduce heat generation.

And in the Suspend state, the device enters a low-power-consumption pause state, and the host reduces the bus power consumption.

Resume State-the device resumes from the low power State (Suspend State) and reenters the active State (ACTIVE STATE).

In the USB interface, DP (Data Plus) and DM (Data Minus) are respectively the D-and D+ Data lines of USB, which are two signal lines for Data transmission and are responsible for realizing the high-efficiency communication between devices.

Linestate the current state of the USB data line describes different states of connection between the device and the host, including states of SE0, J, K and the like;

USB J state and K state are defined in terms of differential signals at low speed and full speed/high speed, as shown in the following table:

Example 1

Referring to fig. 1, the present embodiment provides a low power consumption wake-up system for USB, which includes a USB physical layer interface, a wake-up signal generating circuit, a system interrupt controller, a USB controller, and on-chip processing logic. The wake-up signal generating circuit generates a hardware wake-up signal when detecting that the bus is changed from the J state to the K state, wakes up the whole system through the system interrupt controller, and then resumes the USB controller and the on-chip processing logic. The hardware wake-up signal is generated inside the USB physical layer interface, and after passing through wake-up detection logic inside the USB controller, the hardware wake-up signal outputs an interrupt request to the system interrupt controller.

The wake-up path of the embodiment is that a wake-up signal sequentially passes through a USB INTERFACE (USB INTERFACE), a USB physical layer INTERFACE USB PHY, a USB Controller, a system interrupt Controller INTC and SoC. In this embodiment, INT_REQ is generated directly from inside the USB PHY and the interrupt line is pulled directly to the INTC. This path requires that the USB controller still maintain a certain clock during Suspend and only retains the power necessary to maintain proper functioning of the subsequent USB controller and system in order to detect the Resume signal at any time.

Example 2

Referring to fig. 2, the present embodiment provides a low power consumption wake-up system for USB, which includes a USB physical layer interface, a wake-up signal generating circuit, a system interrupt controller, a USB controller, and on-chip processing logic. The USB physical layer interface receives the differential signal of the USB DP/DM and outputs a line state signal. The wake-up signal generating circuit performs edge detection on the line state signal, and generates a hardware wake-up signal when the continuous K state is detected. The hardware wake-up signal is directly input to the GPIO/EIC of the chip without going through the USB controller. The GPIO/EIC generates a system interrupt that wakes up on-chip processing logic that immediately powers up the USB controller and resumes clocks. The USB controller then executes the Resume sequence defined by the USB specification, completes a handshake with the host, and enters a normal transmission state. During Suspend, the critical modules of the USB controller only reserve a small amount of holding power for saving register context.

Unlike embodiment 1, the wake-up signal generating circuit in this embodiment includes a line state detecting unit and an edge detecting unit. The circuit state detection unit is used for converting the DP/DM differential signal output by the USB PHY into a digital LINESTATE signal, and the edge detection unit is realized by EIC/GPIO in the SoC and used for generating a hardware wake-up signal when detecting that the LINESTATE signal jumps from the J state to the K state.

When the USB is in the Active state from the Suspend state, the linestate signal is changed into the K state (a Resume signal) from the J state, and the Resume signal is connected to the EIC or the GPIO to wake up the system, so that the power supply and the clock of each module are restored after the system is started, and the USB Controller starts to work to process the Resume event and then carries out the next data processing.

In the wake-up path of this embodiment, the USB PHY sends LINESTATE to the EIC/GPIO, which generates a wake-up interrupt. In this embodiment, compared with embodiment 1, the clock in embodiment 1 is further turned off, and compared with embodiment 1, the USB PHY only needs to output LINESTATE, and the wake-up capability is provided by EIC/GPIO, so that the rest of the USB PHY is completely powered off (the rest of the USB PHY except for the termination resistor and LINESTATE output buffer is powered off), only the EIC/GPIO remains monitored, and the power consumption is lower. The EIC/GPIO is the EIC/GPIO on the SoC side, no additional hardware is needed, an on-chip passage of the SoC is realized, a wake-up signal can be responded more quickly, and the signal can be processed in time.

Example 3

Referring to fig. 3, the embodiment provides a low-power consumption wake-up method for a USB, which includes the steps of entering Suspend, turning off a main clock and a main power supply of a USB controller, monitoring a line state, generating a hardware wake-up signal, recovering power supply, executing a wake-up sequence, and the like. Which comprises the following steps:

a) Entering a USB low-power consumption state Suspend, closing a main clock and a main power supply of a USB controller, and storing a register context of the USB controller by a normally-open power-maintaining domain of a chip, wherein EIC/GPIO is enabled;

b) Continuously monitoring the USB line status signal LINESTATE by EIC/GPIO;

c) When the USB line state signal LINESTATE is detected to be changed from the J state to the K state, a hardware wake-up signal is directly generated;

Wherein prior to step a) entry into Suspend is indicated by the USB controller via a software set register. The hardware wakeup signal in step c) remains at an active level throughout the period of the USB controller's main power off until step e) completes the main clock and main power recovery. After step f), the register is cleared by the USB controller to exit the Suspend state.

Example 4

The present embodiment provides a chip implementation scheme in which all or part of the functional modules of the low power wake-up system of embodiment 1 or embodiment 2 are integrated within a single SoC.

Example 5

The embodiment of the invention provides a chip module, which comprises the chip of the embodiment 4 and a USB connector electrically coupled with the chip.

Example 6

An embodiment of the present invention provides a terminal including the chip module of embodiment 5, the terminal configured to enter a Suspend state when the USB bus is idle, and resume USB communication when a bus wakeup event is received.

The person skilled in the art can judge whether the technical scheme of the invention is adopted by other products or not by the following modes:

1. measuring the Suspend current of the chip in the suspended state of the USB bus, and if the Suspend current is obviously lower than the existing scheme, the chip is possibly adopted;

2. monitoring a line state signal output by the USB PHY by using an oscilloscope, and if the signal is found to be directly connected to a GPIO/EIC pin of a chip and a main power supply of the USB controller is turned off, only a small amount of maintenance power supply is reserved for storing a register context, initially confirming the use of the scheme;

3. Through chip dissection and netlist analysis, infringement can be directly proved if a wake-up signal generation circuit and a GPIO/EIC direct connection path which are independent of the USB controller are found.

In the foregoing description of specific embodiments of the invention, features that are described and/or illustrated with respect to one embodiment may be used in the same or a similar way in one or more other embodiments in combination with or instead of the features of the other embodiments.

It should be emphasized that the term "comprises/comprising" when used herein is taken to specify the presence of stated features, elements, steps or components, but does not preclude the presence or addition of one or more other features, elements, steps or components.

Furthermore, the methods of the present invention are not limited to being performed in the time sequence described in the specification, but may be performed in other time sequences, in parallel or independently. Therefore, the order of execution of the methods described in the present specification does not limit the technical scope of the present invention.

While the invention has been disclosed in the context of specific embodiments, it should be understood that all embodiments and examples described above are illustrative rather than limiting. Various modifications, improvements, or equivalents of the invention may occur to persons skilled in the art and are within the spirit and scope of the following claims. Such modifications, improvements, or equivalents are intended to be included within the scope of this invention.

Claims

1. A USB low-power consumption wake-up system is characterized by comprising:

a USB physical layer interface configured to receive differential signals DP/DM of a USB bus;

A wake-up signal generation circuit coupled to the USB physical layer interface and configured to generate a hardware wake-up signal in a USB low power state;

the system interrupt controller is directly connected with the wake-up signal generating circuit to receive the hardware wake-up signal and output a system wake-up interrupt;

The USB controller is coupled with the USB physical layer interface, a main power supply of the USB controller is controlled by on-chip processing logic to enter or exit a USB low-power consumption state, a main clock and the main power supply of the USB controller are closed in the USB low-power consumption state, a register context is stored by a normally-open power domain of a chip, and

2. The USB low-power consumption wake-up system of claim 1, wherein the wake-up signal generating circuit comprises a first implementation as follows:

The USB physical layer interface integrates a wake-up detection function, directly outputs the hardware wake-up signal in a power domain, and is in a low-power monitoring mode in a USB low-power state.

3. The USB low power consumption wake up system of claim 1, wherein the wake up signal generating circuit comprises a second implementation as follows:

The USB physical layer interface only outputs a line state signal, the line state signal is sent to an external interrupt controller EIC or general purpose input/output GPIO, the EIC or GPIO completes edge detection in a power holding domain and generates the hardware wake-up signal, at the moment, the USB physical layer interface is completely powered off except for a terminal resistor and line state signal buffering, a main clock and a main power supply of the USB controller are closed, and a register context is stored by the power holding domain.

4. The USB low power consumption wake up system of claim 3 wherein said hardware wake up signal is directly input to said GPIO or EIC via a chip pin without going through USB controller internal logic.

5. The USB low power consumption wake-up system of claim 3, wherein the wake-up signal generating circuit comprises a line state detecting unit and an edge detecting unit;

6. A low power consumption wake-up method for a USB, which is applied to the low power consumption wake-up system according to any one of claims 1 to 5, and is characterized by comprising the following steps:

c) When the line state is detected to be changed from the J state to the K state, the wake-up signal generating circuit generates a hardware wake-up signal;

7. The method of waking up USB memory device with low power consumption as claimed in claim 6, wherein the hardware wake-up signal in step c) is generated in a manner corresponding to the wake-up signal generating circuit defined in claim 2 or 3.

8. A chip is characterized in that all or part of functional modules of the low-power consumption wake-up system as claimed in any one of claims 1 to 5 are integrated on the same silicon chip.

9. The chip module is characterized by comprising:

The chip of claim 8, and

A USB connector electrically coupled to the chip for interfacing with an external host or device.

10. A terminal comprising the chip module of claim 9, wherein the terminal is configured to enter a Suspend state when a USB bus is idle and resume USB communication when a bus wake event is received.