CN120803236A - Chip, power state control method and device - Google Patents
Chip, power state control method and deviceInfo
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- CN120803236A CN120803236A CN202511270423.XA CN202511270423A CN120803236A CN 120803236 A CN120803236 A CN 120803236A CN 202511270423 A CN202511270423 A CN 202511270423A CN 120803236 A CN120803236 A CN 120803236A
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
- G06F1/3215—Monitoring of peripheral devices
- G06F1/3221—Monitoring of peripheral devices of disk drive devices
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
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Abstract
The embodiment of the application provides a chip, a power state control method and equipment, wherein the chip comprises a plurality of control units, a plurality of sensing units and a plurality of power domains, each control unit is connected with at least one sensing unit, and the sensing units connected with the same control unit are connected with at least one functional module in the same power domain. The sensing unit can be used for determining the power supply state required by the functional module according to the state indication information of the functional module and sending a power supply state jump request to the control unit. The control unit may be configured to determine, according to the power state jump requests of the sensing units, a target power state required by the corresponding power domain, and send a target control request to the PMIC to trigger the PMIC to control the power state of the power domain. By the chip, independent control of each power domain can be realized without influencing response speed and power consumption cost, control granularity is finer, and control precision is improved.
Description
Technical Field
The embodiment of the application relates to the technical field of chips, in particular to a chip, a power state control method and equipment.
Background
The multi-core processor comprises a plurality of power domains, and the power states of different power domains can be controlled respectively in the running process of the multi-core processor. However, the current power state control scheme for the power domain has the problems of high power consumption overhead, low response speed, coarse control granularity and the like.
Disclosure of Invention
In view of the above, embodiments of the present application provide a chip, a power state control method and a device for at least partially solving the above-mentioned problems.
According to a first aspect of the embodiment of the application, a chip is provided, which comprises a plurality of control units, a plurality of sensing units and a plurality of power domains, wherein each control unit is connected with at least one sensing unit, and the sensing units connected with the same control unit are connected with at least one functional module in the same power domain;
the sensing unit is used for determining the power supply state required by the connected functional module according to the state indication information of the connected functional module;
The sensing unit is further used for sending a power state jump request to the connected control unit according to the power state required by the connected functional module;
the control unit is used for determining a target power state required by a power domain corresponding to each connected sensing unit according to the power state jump request sent by each connected sensing unit;
And the control unit is further used for sending a target control request to the off-chip power management chip PMIC according to the target power states required by the power domains corresponding to the connected sensing units, wherein the target control request is used for controlling the power states of the power domains by the off-chip power management chip.
According to a second aspect of an embodiment of the present application, there is provided a power state control method applied to the chip as described in the first aspect, the method including:
the sensing unit determines the power supply state required by the currently connected functional module according to the state indication information of the currently connected functional module;
the sensing unit sends a power state jump request to the connected control unit according to the power state required by the currently connected functional module;
The control unit determines a target power state required by a power domain corresponding to each connected sensing unit according to the power state jump request sent by each connected sensing unit;
and the control unit sends a target control request to the off-chip power management chip PMIC according to the target power states required by the power domains corresponding to the connected sensing units, wherein the target control request is used for controlling the power states of the power domains by the off-chip power management chip.
According to a third aspect of embodiments of the present application, there is provided an electronic device comprising a chip as described in the first aspect for performing the method as described in the second aspect.
According to a fourth aspect of embodiments of the present application, there is provided a computer storage medium having stored thereon a computer program which, when executed by a processor, implements a method as described in the second aspect.
According to the technical scheme provided by the embodiment of the application, the load conditions of different power domains can be automatically perceived based on a hardware mode, and the power state switching is automatically initiated based on the hardware mode, so that a register is not required to be queried or configured in a software mode, and the response time of a system is shortened. In addition, under the condition that the response speed and the power consumption expense are not affected excessively, the scheme can realize independent control of each power domain, the control granularity is finer, and the control precision is improved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments described in the embodiments of the present application, and other drawings may be obtained according to these drawings for a person having ordinary skill in the art.
FIG. 1 is a schematic diagram of a power domain in a multi-core processor according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a chip according to an embodiment of the present application;
fig. 3 is a schematic structural diagram of a sensing unit according to an embodiment of the present application;
FIG. 4 is a schematic diagram of another structure of a chip according to an embodiment of the present application;
FIG. 5 is a flowchart of a power state control method according to an embodiment of the present application;
fig. 6 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
In order to better understand the technical solutions in the embodiments of the present application, the following description will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the accompanying drawings in the embodiments of the present application, and it is obvious that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which are derived by a person skilled in the art based on the embodiments of the present application, shall fall within the scope of protection of the embodiments of the present application.
The terminology used in the embodiments of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is to be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with one another without conflict.
It should also be noted that the term "first\second\third" in relation to embodiments of the present application is used merely to distinguish similar objects and does not represent a particular ordering for the objects, it being understood that the "first\second\third" may be interchanged in a particular order or sequence, where allowed, to enable embodiments of the present application described herein to be practiced in an order other than that illustrated or described herein.
In addition, the term "and/or" in the embodiment of the present application is merely an association relationship describing the association object, and indicates that three relationships may exist, for example, a and/or B may indicate that a exists alone, and a and B exist together, and B exists alone. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship.
In order to facilitate understanding of the technical solutions of the embodiments of the present application, the following description describes related technologies of the embodiments of the present application, and the following related technologies may be optionally combined with the technical solutions of the embodiments of the present application as alternatives, which all belong to the protection scope of the embodiments of the present application.
The multi-core processor-based chip includes a plurality of processing units, each of which may include a separate processor and a plurality of specific function execution modules. A chip based on a multi-core processor may include a plurality of power domains, and fig. 1 shows an example of a division of the power domains of the multi-core processor, and as shown in fig. 1, the multi-core processor may include a plurality of independent power domains, such as a power domain 1, a power domain 2, a power domain 3, and a normally-on power domain. The power states of the power domains are mutually independent, so that the power consumption of the multi-core processor can be reduced, and the performance of the multi-core processor can be improved.
In the running process of the multi-core processor, the power state of each power domain in the multi-core processor can be dynamically adjusted by monitoring the performance and the load condition of each functional module (including the processor in any processing unit and each functional execution module) in the multi-core processor and based on the performance and the load condition of each functional module, so that the dynamic power consumption control of each power domain is realized, and the power supply requirements of different functional modules in the multi-core processor are met.
In a common technical scheme, the working states of all functional modules are queried in a software mode, so that the power state control of different power domains is realized. However, the above solution requires frequent software inquiry and register configuration, which has high power consumption overhead and slow response speed, and because the software configuration required for performing power state control and power-down operation of the power domain in a software manner is long, the response speed is slow, so that only a plurality of power domains can be controlled in a unified manner, and the problem of coarse control granularity is caused.
The present application has been made to solve the above-mentioned problems.
In the embodiment of the application, a Chip based on a multi-core processor can be provided, and the Chip can be a System on Chip (SoC) which can respond to the load change of each functional module in each power domain based on a hardware mode, so as to dynamically change the power state of each power domain in the Chip and realize independent control of each power domain. By the method provided by the embodiment of the application, the power consumption expense caused by the redundant register configuration of software inquiry can be avoided, and the problems of slow response speed and coarse control granularity of power state control of a power domain in the related technology can be solved.
The chip and the functional implementation of the chip provided by the embodiment of the application are described in detail below with reference to the related drawings.
Fig. 2 is a schematic structural diagram of a chip according to the present application. As shown in fig. 2, the chip provided by the embodiment of the application may include a plurality of control units, a plurality of sensing units, and a plurality of power domains. Each control unit is connected with at least one sensing unit, and the at least one sensing unit connected with each control unit is respectively connected with at least one functional module in the same power domain. It should be noted that, the functional module connected to the sensing unit may be a processor itself or a specific functional execution module.
Based on the chip with the structure shown in fig. 2, the sensing unit may be configured to receive status indication information sent by each currently connected functional module, and determine, according to the received status indication information, a power supply status required by each currently connected functional module. In one possible implementation manner, the number of the functional modules connected to each sensing unit is one, and then one sensing unit can obtain the state indication information sent by one specific functional module in a targeted manner so as to determine the power supply state required by the functional module. In another possible implementation manner, the number of the functional modules connected to each sensing unit is multiple, and then one sensing unit may simultaneously acquire state indication information of multiple functional modules, and determine power states required by the multiple functional modules respectively.
The status indication information may specifically include working status indication information and load status indication information. The operation state indication information may be used to describe an operation state of the corresponding functional module, and the operation state indication information may include, for example, idle state indication information and active state indication information. The Idle state indication information may be used to indicate that the functional module enters an Idle (Idle) state, and the Active state indication information may be used to indicate that the functional module enters an Active (Active) state. The load status indication information may be used to describe a load condition of the corresponding functional module, and may include, for example, at least one instruction retirement (Instruction Retirement) count information. Such as a floating point instruction retire counter, a memory access instruction retire counter, and the like. The more instruction retirement counts, the more instructions the functional module has executed within a particular time period, the more load the functional module is loaded within the particular time period.
Based on the state indication information, on one hand, the sensing unit may be configured to predict the working state of the currently connected functional module according to the working state indication information of the currently connected functional module. Specifically, the sensing unit may determine the duration of the idle state of the currently connected functional module according to the idle state indication information and the active state indication information output by the currently connected functional module. For example, the sensing unit may determine the idle state duration according to an interval duration of the received idle state indication information and the next adjacent active state indication information. Furthermore, the sensing unit can predict the working state of the currently connected functional module according to the duration of the idle state of the currently connected functional module. Illustratively, the longer the duration of the idle state of a currently connected functional module, the more likely the operating state of the functional module is to be idle for the next period of time. The shorter the duration of the idle state of the currently connected functional module, the more likely the operating state of the functional module is to be active for the next period of time.
On the other hand, the sensing unit may be configured to predict a load state of the currently connected functional module according to load state indication information of the currently connected functional module. Specifically, the sensing unit may determine the load index of the currently connected functional module according to the target algorithm according to at least one instruction retirement count information output by the currently connected functional module. For example, the sensing unit may perform linear weighted calculation on each instruction retirement count information to obtain a weighted value of each count result, where the weighted value may be used as a load index. Furthermore, the sensing unit can predict the load state of the currently connected functional module according to the load index of the currently connected functional module. For example, the obtained load index may be compared with a preset threshold, and when the load index is greater than the set threshold, the load level of the functional module is predicted to be high for the next period, whereas when the load index is less than the set threshold, the load level of the functional module is predicted to be low for the next period.
Further, the sensing unit may determine a power state required by the currently connected functional module according to the predicted working state and the load state of the functional module, and send a power state jump request to the connected control unit according to the power state.
Specifically, in the embodiment of the present application, multiple power states may be predefined for the current power domain. By way of example, the various Power states may include normal operating voltage gear, clock Off, memory Sleep (Memory Sleep), memory Power Off (Memory Power-Off), power Switch (Power Switch) Off, off-chip Power management chip (Power MANAGEMENT IC, PMIC) Off, and so on. The Power Switch (Power Switch) is turned off, and the Power supply of a specific functional module in the Power domain is cut off through the on-chip Power Switch, which belongs to Power management inside a chip. The turning-off of the PMIC refers to turning off the power supply of a specific power domain through the whole external PMIC, belongs to system-level power management, and requires the cooperation of the chip and the external PMIC.
Different working states and load states of the functional modules can be pre-corresponding to different power states. Then, the sensing unit can determine the matched power supply state, namely the power supply state required by the next period of the functional module according to the predicted working state and the load state. When the load index is determined to be smaller than the set threshold value and the duration of the idle state exceeds the set threshold value based on the method, the load level of the functional module is predicted to be low and the working state is the idle state in the next period, then the currently matched power states including low working voltage gear, clock shutdown, memory sleep, power shutdown, including memory power failure, power switch shutdown and off-chip power management chip can be determined according to different working states and preset mapping relations between the load state and different power states. Thereby entering a low power consumption state. Furthermore, the sensing unit can generate a corresponding power state jump request and send the power state jump request to the control unit, so that the control unit executes a subsequent flow according to the power state jump request and finally realizes the switching of the power state of the functional module.
Fig. 3 is a schematic structural diagram of a sensing unit according to an embodiment of the present application. As shown in fig. 3, the sensing unit may include a first sensing unit, a second sensing unit, and an output unit. The first sensing unit may be a working state estimation module, and the first sensing unit may be configured to implement the above-mentioned function of predicting the working state of the functional module according to the working state indication information of the functional module. The second sensing unit may be a load state estimation module, and the second sensing unit may be configured to implement the above-mentioned related function of predicting the load state according to the load state indication information of the functional module. The output unit can be used for executing the related functions of determining the power state required by the functional module according to the working state and the load state and sending a power state jump request to the control unit according to the power state.
Further, as shown in fig. 3, the sensing unit may further include a wake-up module, and the wake-up module may be configured to wake up the corresponding functional module in response to receiving the interrupt wake-up signal. The interrupt wake-up signal may come from an associated functional module inside the chip or may come from an associated functional module outside the chip. In case of a related functional module from outside the chip, the external module can send an interrupt wake-up signal to the above mentioned wake-up module in the sensing unit based on the external interface.
Based on the chip with the structure shown in fig. 2, further, the control unit may be configured to determine, according to the power state jump request sent by each connected sensing unit, a target power state required by a power domain corresponding to each connected sensing unit.
In the embodiment of the application, the sensing units connected with each control unit are connected with the functional modules in the same power domain, so that for any one control unit, the target power state required by the corresponding power domain can be determined according to the power state indicated by each power state jump request received from each sensing unit. The control unit may determine, according to the power state jump request sent by each sensing unit, a power state required by the functional module connected to each sensing unit, and may further arbitrate, according to a preset arbitration principle, the power state required by each functional module, to determine a target power state required by a power domain in which each functional module is located. The preset arbitration principle may be, for example, to take a power state with lower power consumption from power states required by each functional module as a target power state. Or may follow any other possible arbitration principle, such as taking the power state that makes the chip perform best as the target power state, which is not limited by the embodiment of the present application.
And the control unit is further used for sending a target control request to the PMIC according to the target power states required by the power domains corresponding to the connected sensing units, wherein the target control request is used for controlling the power states of the power domains by the PMIC.
Specifically, the control unit may be configured to generate a target control signal according to a target power state required by a power domain corresponding to each connected sensing unit, where the target control signal may be a control signal in the chip, and may include a power signal, a clock signal, a reset signal, and the like. And the control unit is further configured to generate a target control request according to the target control signal, and send the target control request to the PMIC. The target control request may be an instruction that the PMIC can understand, and the target control request may be used to instruct the PMIC to perform a corresponding power state control operation on the power domain, so as to switch the power state of the power domain to the target power state.
In another possible implementation manner of the embodiment of the present application, the control unit may include a first control unit and a second control unit. The first control unit may be a power state control unit, and the first control unit may be configured to implement the above-mentioned function of determining a target power state required by a corresponding power domain according to the power state jump request sent by each connected sensing unit, and may also be configured to implement the above-mentioned function of generating a target control signal according to the target power state required by the corresponding power domain. The second control unit may be a PMIC control unit, and the second control unit may be configured to implement the above-described related function of generating the target control request according to the target control signal, and transmitting the target control request to the PMIC. The second control unit responds to the target control signal sent by the first control unit, and can automatically trigger to send a target control request to the PMIC according to a format of a PMIC protocol under the condition of no software intervention, so that the PMIC controls the power state of the power domain.
The chip provided by the embodiment of the application can automatically sense the load conditions of different power domains based on a hardware mode, and automatically initiate power state switching based on the hardware mode, so that a register is not required to be queried or configured in a software mode, and the response time of a system is shortened. In addition, under the condition that the response speed and the power consumption expense are not affected excessively, the scheme can realize independent control of each power domain, the control granularity is finer, and the control precision is improved.
Fig. 4 is a schematic diagram of another structure of a chip according to an embodiment of the present application. As shown in fig. 4, the chip may include a plurality of power domains, where the plurality of power domains may include a normally-open power domain, where the normally-open power domain refers to a power domain that always maintains a power-on state, and the normally-open power domain may include a PMIC control unit, a power state control unit, and a sensing unit provided by the embodiment of the present application. Wherein, each power state control unit can be connected with a PMIC control unit respectively, and the PMIC control unit can be connected with an external PMIC. And each power state control unit can also be respectively provided with a plurality of sensing units, and each sensing unit connected with each power control unit can be respectively connected with different functional modules under the same power domain.
It will be understood that in the chip with the structure shown in fig. 4, the sensing units are in one-to-one correspondence with the functional units, and the power state control units are in one-to-one correspondence with the power domains. Through the chip of structure as shown in fig. 4, the sensing chip can dynamically monitor the load state of the power domain with the granularity of the functional module, the flexibility is higher, and the power state control unit can realize the independent control of the power states of all the power domains with the granularity of the power domain, and the control granularity is smaller.
Based on the chip with the structure shown in fig. 4, in the embodiment of the present application, each sensing unit may be used to obtain the status indication information of the connected specific functional module, and determine the power status required by each functional module in the subsequent period according to the obtained status indication information. Further, a power state jump request may be sent to the power state control unit according to the desired power state. Reference may be made to the foregoing embodiments for specific functional implementation, which are not described herein.
Furthermore, for any one power state control unit, the power state required by each functional module can be determined according to the power state jump request sent by each sensing unit, and further, the power state required by each functional module can be arbitrated according to a preset arbitration principle, and the target power state required by the corresponding power domain is determined from each predefined power state. In the embodiment of the application, the power state supported by the power state control unit can be configured in a software mode, for example, the configurable power state control unit supports all power states or the configurable power state control unit supports part of power states. Furthermore, the power state control unit may send a PMIC power control request to the PMIC control unit according to the target power state obtained by the arbitration, so as to trigger the PMIC control unit to send a PMIC control command to the PMIC. The PMIC control command may be used to trigger the PMIC to perform power state control on the power domain, so that the corresponding power domain is switched to the target power state. Specific functional implementation may refer to the foregoing embodiments, and will not be described herein.
The external PMIC independent of the chip can be used for controlling the Power state of the whole Power domain, and in the embodiment of the application, the Power state of each functional unit can be independently controlled in a Power Switch (Power Switch) mode in each Power domain. The Power state control unit may control the Power state switching of the corresponding functional unit through a Power Switch (Power Switch) inside the corresponding Power domain after receiving the Power state jump request sent by any one of the sensing units. In this way, a smaller granularity of power state control may be achieved.
In other implementations, the chip may also have other structures, and for example, the power state control unit and the sensing unit may be connected in a one-to-one manner, that is, one power state control unit may be connected to one sensing unit. Meanwhile, the sensing units and the functional units can be connected in a one-to-many mode, namely, one sensing unit is connected with all the functional modules in the same power domain at the same time. In this way, the status indication information of each functional module in the same power domain can be sent to the same sensing unit, the same sensing unit respectively determines the power status required by each functional unit, and sends a power status jump request corresponding to each functional unit to the power control unit. Through the implementation mode, the chip structure can be simplified, and the monitoring of the load states of different functional units in the power domain can be realized through fewer sensing units.
In another embodiment, a power state control method is also provided, and the power state control method can be applied to the chip described in the above embodiment. Fig. 5 is a flowchart of a power state control method according to an embodiment of the present application, where, as shown in fig. 5, the power state control method according to an embodiment of the present application includes:
Step 101, determining, by the sensing unit, a power supply state required by the currently connected functional module according to state indication information of the currently connected functional module.
Step 102, the sensing unit sends a power state jump request to the connected control unit according to the power state required by the currently connected functional module.
Step 103, the control unit determines the target power state required by the power domain corresponding to each connected sensing unit according to the power state jump request sent by each connected sensing unit.
Step 104, the control unit sends a target control request to the PMIC according to the target power states required by the power domains corresponding to the connected sensing units, wherein the target control request is used for controlling the power states of the power domains by the PMIC.
In a possible implementation manner, the control unit comprises a first control unit and a second control unit, the method comprises the steps that the first control unit determines a target power state required by a power domain corresponding to each connected sensing unit according to a power state jump request sent by each connected sensing unit, a target control signal is generated according to the target power state required by the power domain corresponding to each connected sensing unit, the target control signal comprises a power signal, a clock signal and a reset signal, and the second control unit generates a target control request according to the target control signal and sends the target control request to an off-chip power management chip.
In a possible implementation manner, the first control unit determines a target power state required by a power domain corresponding to each connected sensing unit according to a power state jump request sent by each connected sensing unit, and the first control unit determines the power state required by a functional module connected to each sensing unit according to the power state jump request sent by each connected sensing unit, and arbitrates the power state required by the functional module connected to each sensing unit according to a preset arbitration principle to obtain the target power state required by the power domain corresponding to each sensing unit.
In a possible implementation mode, the state indication information comprises working state indication information and load state indication information, the sensing unit comprises a first sensing unit, a second sensing unit and an output unit, the method comprises the steps that the first sensing unit predicts the working state of a currently connected functional module according to the working state indication information of the currently connected functional module, and the second sensing unit predicts the load state of the currently connected functional module according to the load state indication information of the currently connected functional module. The output unit determines the power state required by the currently connected functional module according to the working state and the load state of the currently connected functional module, and sends a power state jump request to the connected control unit according to the power state required by the currently connected functional module.
In one possible implementation, the operating state indication information includes idle state indication information and active state indication information, and the load state indication information includes at least one instruction retirement count information.
In a possible implementation manner, the first sensing unit predicts the working state of the currently connected functional module according to the working state indication information of the currently connected functional module, and the method comprises the steps of determining the duration of the idle state of the currently connected functional module according to the idle state indication information and the active state indication information output by the currently connected functional module by the first sensing unit, and predicting the working state of the currently connected functional module according to the duration of the idle state of the currently connected functional module.
In one possible implementation manner, the second sensing unit predicts the load state of the currently connected functional module according to the load state indication information of the currently connected functional module, and the method comprises the steps of determining the load index of the currently connected functional module by using a target algorithm according to at least one instruction retirement counting information output by the currently connected functional module by the second sensing unit, wherein the target algorithm comprises a linear weighting algorithm, and predicting the load state of the currently connected functional module according to the load index of the currently connected functional module.
In a possible implementation manner, the sensing unit further comprises a wake-up module, and the method further comprises the step that the wake-up module wakes up the corresponding functional module in response to receiving an interrupt wake-up signal.
Since details of the power state control method are described in the above chip embodiment section in detail with reference to the structural schematic diagram, specific processes can be referred to in the above chip embodiment, and no further description is given here.
The power state control method provided by the embodiment of the application can automatically sense the load conditions of different power domains based on a hardware mode, and automatically initiate the power state switching based on the hardware mode, so that a register is not required to be queried or configured in a software mode, and the response time of a system is shortened. In addition, under the condition that the response speed and the power consumption expense are not affected excessively, the scheme can realize independent control of each power domain, the control granularity is finer, and the control precision is improved.
Fig. 6 is a schematic structural diagram of an electronic device according to an embodiment of the present application, where a chip provided by the embodiment of the present application may be configured, and the chip may be used to execute the power state control method provided by the embodiment of the present application, and the specific embodiment of the present application is not limited to specific implementation of the electronic device.
As shown in FIG. 6, the electronic device may include a processor 502, a communication interface (CommunicationsInterface) 504, a memory 506, and a communication bus 508.
Wherein the processor 502, the communication interface 504, and the memory 506 communicate with each other via a communication bus 508. A communication interface 504 for communicating with other electronic devices or servers. The processor 502 is configured to execute the program 510, and may specifically perform relevant steps in the above-described power state control method embodiment.
In particular, program 510 may include program code including computer-operating instructions.
The processor 502 may be a processor CPU, or a specific integrated circuit ASIC (ApplicationSpecificIntegratedCircuit), or one or more integrated circuits configured to implement embodiments of the present application. The one or more processors included in the smart device may be the same type of processor, such as one or more CPUs, or different types of processors, such as one or more CPUs and one or more ASICs.
A memory 506 for storing a program 510. Memory 506 may comprise high-speed RAM memory or may also include non-volatile memory (non-volatilememory), such as at least one disk memory.
The program 510 may be specifically configured to cause the processor 502 to perform operations, in an alternative embodiment, the program 510 is further configured to cause the processor 502 to perform the steps in the program 510 to be specifically implemented by referring to corresponding steps in the above embodiment of the power state control method and corresponding descriptions in the system, which are not repeated herein. It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the apparatus and modules described above may refer to corresponding procedure descriptions in the foregoing method embodiments, which are not repeated herein.
The embodiment of the application also provides a computer program product, which comprises computer instructions, wherein the computer instructions instruct a computing device to execute the operations corresponding to any one of the power state control methods in the method embodiments. It should be noted that, according to implementation requirements, each component/step described in the embodiments of the present application may be split into more components/steps, or two or more components/steps or part of operations of the components/steps may be combined into new components/steps, so as to achieve the objects of the embodiments of the present application.
The embodiments of the present application also provide a computer-readable storage medium, and the above-described method according to the embodiments of the present application may be implemented in hardware, firmware, or as software or computer code storable in a recording medium such as a CDROM, RAM, floppy disk, hard disk, or magneto-optical disk, or computer code originally stored in a remote recording medium or a non-transitory machine-readable medium and to be stored in a local recording medium downloaded through a network, so that the method as described herein may be processed by such software on a recording medium using a general purpose computer, a special purpose processor, or programmable or dedicated hardware such as an ASIC or FPGA. It is understood that a computer, processor, microprocessor controller, or programmable hardware includes a memory component (e.g., RAM, ROM, flash memory, etc.) that can store or receive software or computer code that, when accessed and executed by the computer, processor, or hardware, implements the power state control methods described herein. Further, when the general-purpose computer accesses code for implementing the power state control method shown herein, execution of the code converts the general-purpose computer into a special-purpose computer for executing the power state control method shown herein.
Those of ordinary skill in the art will appreciate that the elements and method steps of the examples described in connection with the embodiments disclosed herein can be implemented as electronic hardware, or as a combination of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the embodiments of the present application.
It should be noted that, in the present application, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
In addition, it should be noted that, the information related to the user (including, but not limited to, user equipment information, user personal information, etc.) and the data related to the embodiment of the present application (including, but not limited to, sample data for training the model, data for analyzing, stored data, presented data, etc.) are information and data authorized by the user or sufficiently authorized by each party, and the collection, use and processing of the related data need to comply with the related laws and regulations and standards of the related country and region, and provide a corresponding operation entry for the user to select authorization or rejection.
The foregoing embodiment numbers of the present application are merely for the purpose of description, and do not represent the advantages or disadvantages of the embodiments.
The methods disclosed in the method embodiments provided by the application can be arbitrarily combined under the condition of no conflict to obtain a new method embodiment.
The features disclosed in the several product embodiments provided by the application can be combined arbitrarily under the condition of no conflict to obtain new product embodiments.
The features disclosed in the embodiments of the method or the apparatus provided by the application can be arbitrarily combined without conflict to obtain new embodiments of the method or the apparatus.
The above embodiments are only for illustrating the embodiments of the present application, but not for limiting the embodiments of the present application, and various changes and modifications may be made by one skilled in the relevant art without departing from the spirit and scope of the embodiments of the present application, so that all equivalent technical solutions also fall within the scope of the embodiments of the present application, and the scope of the embodiments of the present application should be defined by the claims.
Claims (10)
1. The chip is characterized by comprising a plurality of control units, a plurality of sensing units and a plurality of power domains, wherein each control unit is connected with at least one sensing unit, and the sensing units connected with the same control unit are connected with at least one functional module in the same power domain;
The sensing unit is used for determining the power supply state required by the connected functional module according to the state indication information of the connected functional module, wherein the state indication information comprises working state indication information and load state indication information;
The sensing unit is further used for sending a power state jump request to the connected control unit according to the power state required by the connected functional module;
the control unit is used for determining a target power state required by a power domain corresponding to each connected sensing unit according to the power state jump request sent by each connected sensing unit;
And the control unit is further used for sending a target control request to the off-chip power management chip PMIC according to the target power states required by the power domains corresponding to the connected sensing units, wherein the target control request is used for controlling the power states of the power domains by the off-chip power management chip.
2. The chip of claim 1, wherein the control unit comprises a first control unit and a second control unit;
The first control unit is specifically configured to determine a target power state required by a power domain corresponding to each connected sensing unit according to a power state jump request sent by each connected sensing unit, and generate a target control signal according to the target power state required by the power domain corresponding to each connected sensing unit, where the target control signal includes a power signal, a clock signal and a reset signal;
The second control unit is specifically configured to generate a target control request according to the target control signal, and send the target control request to the off-chip power management chip.
3. The chip of claim 2, wherein the first control unit is specifically configured to:
determining the power supply state required by the functional module connected with each sensing unit according to the power supply state jump request sent by each sensing unit connected with each sensing unit;
And according to a preset arbitration principle, arbitrating the power supply state required by the functional module connected with each sensing unit to obtain the target power supply state required by the power supply domain corresponding to each sensing unit.
4. The chip of claim 1, wherein the sensing unit comprises a first sensing unit, a second sensing unit, and an output unit;
The first sensing unit is used for predicting the working state of the connected functional module according to the working state indication information of the connected functional module;
the second sensing unit is used for predicting the load state of the connected functional module according to the load state indication information of the connected functional module;
The output unit is used for determining the power state required by the connected functional module according to the working state and the load state of the connected functional module, and sending a power state jump request to the connected control unit according to the power state required by the connected functional module.
5. The chip of claim 4, wherein the operating state indication information comprises idle state indication information and active state indication information, and wherein the load state indication information comprises at least one instruction retirement count information.
6. The chip of claim 5, wherein the first sensing unit is specifically configured to:
Determining the duration of the idle state of the connected functional module according to the idle state indication information and the active state indication information output by the connected functional module;
And predicting the working state of the connected functional module according to the idle state duration of the connected functional module.
7. The chip of claim 5, wherein the second sensing unit is specifically configured to:
Determining a load index of the connected functional module by using a target algorithm according to at least one instruction retirement count information output by the connected functional module, wherein the target algorithm comprises a linear weighting algorithm;
And predicting the load state of the connected functional module according to the load index of the connected functional module.
8. The chip of claim 4, wherein the sensing unit further comprises a wake-up module for waking up a corresponding functional module in response to receiving an interrupt wake-up signal.
9. A power state control method, characterized in that it is applied to the chip according to any one of claims 1 to 8, and comprises:
the sensing unit determines the power supply state required by the connected functional module according to the state indication information of the connected functional module;
and sending a power state jump request to the connected control unit by the sensing unit according to the power state required by the connected functional module;
The control unit determines a target power state required by a power domain corresponding to each connected sensing unit according to the power state jump request sent by each connected sensing unit;
and the control unit sends a target control request to the off-chip power management chip PMIC according to the target power states required by the power domains corresponding to the connected sensing units, wherein the target control request is used for controlling the power states of the power domains by the off-chip power management chip.
10. An electronic device comprising a chip as claimed in any one of claims 1 to 8 for performing the method as claimed in claim 9.
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